LXR uboot/arch/arm/cpu/armv7/omap-common/syslib.c

   1/*
   2 * (C) Copyright 2008
   3 * Texas Instruments, <www.ti.com>
   4 *
   5 * Richard Woodruff <r-woodruff2@ti.com>
   6 * Syed Mohammed Khasim <khasim@ti.com>
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#include <common.h>
  25#include <asm/io.h>
  26#include <asm/arch/sys_proto.h>
  27
  28/************************************************************
  29 * sdelay() - simple spin loop.  Will be constant time as
  30 *  its generally used in bypass conditions only.  This
  31 *  is necessary until timers are accessible.
  32 *
  33 *  not inline to increase chances its in cache when called
  34 *************************************************************/
  35void sdelay(unsigned long loops)
  36{
  37        __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
  38                          "bne 1b":"=r" (loops):"0"(loops));
  39}
  40
  41/*****************************************************************
  42 * sr32 - clear & set a value in a bit range for a 32 bit address
  43 *****************************************************************/
  44void sr32(void *addr, u32 start_bit, u32 num_bits, u32 value)
  45{
  46        u32 tmp, msk = 0;
  47        msk = 1 << num_bits;
  48        --msk;
  49        tmp = readl((u32)addr) & ~(msk << start_bit);
  50        tmp |= value << start_bit;
  51        writel(tmp, (u32)addr);
  52}
  53
  54/*********************************************************************
  55 * wait_on_value() - common routine to allow waiting for changes in
  56 *   volatile regs.
  57 *********************************************************************/
  58u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
  59                  u32 bound)
  60{
  61        u32 i = 0, val;
  62        do {
  63                ++i;
  64                val = readl((u32)read_addr) & read_bit_mask;
  65                if (val == match_value)
  66                        return 1;
  67                if (i == bound)
  68                        return 0;
  69        } while (1);
  70}
  71