1/*-----------------------------------------------------------------------------+ 2 | This source code is dual-licensed. You may use it under the terms of the 3 | GNU General Public License version 2, or under the license below. 4 | 5 | This source code has been made available to you by IBM on an AS-IS 6 | basis. Anyone receiving this source is licensed under IBM 7 | copyrights to use it in any way he or she deems fit, including 8 | copying it, modifying it, compiling it, and redistributing it either 9 | with or without modifications. No license under IBM patents or 10 | patent applications is to be implied by the copyright license. 11 | 12 | Any user of this software should understand that IBM cannot provide 13 | technical support for this software and will not be responsible for 14 | any consequences resulting from the use of this software. 15 | 16 | Any person who transfers this source code or any derivative work 17 | must include the IBM copyright notice, this paragraph, and the 18 | preceding two paragraphs in the transferred software. 19 | 20 | COPYRIGHT I B M CORPORATION 1995 21 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M 22 +-----------------------------------------------------------------------------*/ 23/*-----------------------------------------------------------------------------+ 24 | 25 | File Name: miiphy.c 26 | 27 | Function: This module has utilities for accessing the MII PHY through 28 | the EMAC3 macro. 29 | 30 | Author: Mark Wisner 31 | 32 | Change Activity- 33 | 34 | Date Description of Change BY 35 | --------- --------------------- --- 36 | 05-May-99 Created MKW 37 | 01-Jul-99 Changed clock setting of sta_reg from 66MHz to 50MHz to 38 | better match OPB speed. Also modified delay times. JWB 39 | 29-Jul-99 Added Full duplex support MKW 40 | 24-Aug-99 Removed printf from dp83843_duplex() JWB 41 | 19-Jul-00 Ported to esd cpci405 sr 42 | 23-Dec-03 Ported from miiphy.c to 440GX Travis Sawyer TBS 43 | <travis.sawyer@sandburst.com> 44 | 45 +-----------------------------------------------------------------------------*/ 46 47#include <common.h> 48#include <miiphy.h> 49#include "IxOsal.h" 50#include "IxEthAcc.h" 51#include "IxEthAcc_p.h" 52#include "IxEthAccMac_p.h" 53#include "IxEthAccMii_p.h" 54 55/***********************************************************/ 56/* Dump out to the screen PHY regs */ 57/***********************************************************/ 58 59void miiphy_dump (char *devname, unsigned char addr) 60{ 61 unsigned long i; 62 unsigned short data; 63 64 65 for (i = 0; i < 0x1A; i++) { 66 if (miiphy_read (devname, addr, i, &data)) { 67 printf ("read error for reg %lx\n", i); 68 return; 69 } 70 printf ("Phy reg %lx ==> %4x\n", i, data); 71 72 /* jump to the next set of regs */ 73 if (i == 0x07) 74 i = 0x0f; 75 76 } /* end for loop */ 77} /* end dump */ 78 79 80/***********************************************************/ 81/* (Re)start autonegotiation */ 82/***********************************************************/ 83int phy_setup_aneg (char *devname, unsigned char addr) 84{ 85 unsigned short ctl, adv; 86 87 /* Setup standard advertise */ 88 miiphy_read (devname, addr, PHY_ANAR, &adv); 89 adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 | 90 PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD | 91 PHY_ANLPAR_10); 92 miiphy_write (devname, addr, PHY_ANAR, adv); 93 94 /* Start/Restart aneg */ 95 miiphy_read (devname, addr, PHY_BMCR, &ctl); 96 ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); 97 miiphy_write (devname, addr, PHY_BMCR, ctl); 98 99 return 0; 100} 101 102 103int npe_miiphy_read (const char *devname, unsigned char addr, 104 unsigned char reg, unsigned short *value) 105{ 106 u16 val; 107 108 ixEthAccMiiReadRtn(addr, reg, &val); 109 *value = val; 110 111 return 0; 112} /* phy_read */ 113 114 115int npe_miiphy_write (const char *devname, unsigned char addr, 116 unsigned char reg, unsigned short value) 117{ 118 ixEthAccMiiWriteRtn(addr, reg, value); 119 return 0; 120} /* phy_write */ 121