LXR uboot/board/delta/lowlevel

   1/*
   2 * (C) Copyright 2006 DENX Software Engineering
   3 *
   4 * See file CREDITS for list of people who contributed to this
   5 * project.
   6 *
   7 * This program is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU General Public License as
   9 * published by the Free Software Foundation; either version 2 of
  10 * the License, or (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the Free Software
  19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 * MA 02111-1307 USA
  21 */
  22
  23#include <config.h>
  24#include <version.h>
  25#include <asm/arch/pxa-regs.h>
  26
  27DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
  28
  29.macro wait time
  30        ldr             r2, =OSCR
  31        mov             r3, #0
  32        str             r3, [r2]
  330:
  34        ldr             r3, [r2]
  35        cmp             r3, \time
  36        bls             0b
  37.endm
  38
  39.globl lowlevel_init
  40lowlevel_init:
  41        /* Set up GPIO pins first */
  42        mov      r10, lr
  43
  44        /*  Configure GPIO  Pins 97, 98 UART1 / altern. Fkt. 1 */
  45        ldr             r0, =GPIO97
  46        ldr             r1, =0x801
  47        str             r1, [r0]
  48
  49        ldr             r0, =GPIO98
  50        ldr             r1, =0x801
  51        str             r1, [r0]
  52
  53        /* tebrandt - ASCR, clear the RDH bit */
  54        ldr             r0, =ASCR
  55        ldr             r1, [r0]
  56        bic             r1, r1, #0x80000000
  57        str             r1, [r0]
  58
  59mem_init:
  60        /* Configure ACCR Register - enable DMEMC Clock at 260 / 2 MHz */
  61        ldr             r0, =ACCR
  62        ldr             r1, [r0]
  63        orr             r1, r1, #0x3000
  64        str             r1, [r0]
  65        ldr             r1, [r0]
  66
  67        /* 2. Programm MDCNFG, leaving DMCEN de-asserted */
  68        ldr             r0, =MDCNFG
  69        ldr             r1, =(MDCNFG_DMAP | MDCNFG_DTYPE | MDCNFG_DTC_2 | MDCNFG_DCSE0 | MDCNFG_DRAC_13)
  70        /* ldr          r1, =0x80000403 */
  71        str             r1, [r0]
  72        ldr             r1, [r0]        /* delay until written */
  73
  74        /* 3. wait nop power up waiting period (200ms)
  75         * optimization: Steps 4+6 can be done during this
  76         */
  77        wait #0x300
  78
  79        /* 4. Perform an initial Rcomp-calibration cycle */
  80        ldr             r0, =RCOMP
  81        ldr             r1, =0x80000000
  82        str             r1, [r0]
  83        ldr             r1, [r0]        /* delay until written */
  84        /* missing: program for automatic rcomp evaluation cycles */
  85
  86        /* 5. DDR DRAM strobe delay calibration */
  87        ldr             r0, =DDR_HCAL
  88        ldr             r1, =0x88000007
  89        str             r1, [r0]
  90        wait            #5
  91        ldr             r1, [r0]        /* delay until written */
  92
  93        /* Set MDMRS */
  94        ldr             r0, =MDMRS
  95        ldr             r1, =0x60000033
  96        str             r1, [r0]
  97        wait    #300
  98
  99        /* Configure MDREFR */
 100        ldr             r0, =MDREFR
 101        ldr             r1, =0x00000006
 102        str             r1, [r0]
 103        ldr             r1, [r0]
 104
 105        /* Enable the dynamic memory controller */
 106        ldr             r0, =MDCNFG
 107        ldr             r1, [r0]
 108        orr             r1, r1, #MDCNFG_DMCEN
 109        str             r1, [r0]
 110
 111#ifndef CONFIG_SYS_SKIP_DRAM_SCRUB
 112        /* scrub/init SDRAM if enabled/present */
 113        ldr     r8, =CONFIG_SYS_DRAM_BASE       /* base address of SDRAM (CONFIG_SYS_DRAM_BASE) */
 114        ldr     r9, =CONFIG_SYS_DRAM_SIZE       /* size of memory to scrub (CONFIG_SYS_DRAM_SIZE) */
 115        mov     r0, #0                  /* scrub with 0x0000:0000 */
 116        mov     r1, #0
 117        mov     r2, #0
 118        mov     r3, #0
 119        mov     r4, #0
 120        mov     r5, #0
 121        mov     r6, #0
 122        mov     r7, #0
 12310:     /* fastScrubLoop */
 124        subs    r9, r9, #32     /* 8 words/line */
 125        stmia   r8!, {r0-r7}
 126        beq     15f
 127        b       10b
 128#endif /* CONFIG_SYS_SKIP_DRAM_SCRUB */
 129
 13015:
 131        /* Mask all interrupts */
 132        mov     r1, #0
 133        mcr     p6, 0, r1, c1, c0, 0    @ ICMR
 134
 135        /* Disable software and data breakpoints */
 136        mov     r0, #0
 137        mcr     p15,0,r0,c14,c8,0  /* ibcr0 */
 138        mcr     p15,0,r0,c14,c9,0  /* ibcr1 */
 139        mcr     p15,0,r0,c14,c4,0  /* dbcon */
 140
 141        /* Enable all debug functionality */
 142        mov     r0,#0x80000000
 143        mcr     p14,0,r0,c10,c0,0  /* dcsr */
 144
 145endlowlevel_init:
 146        mov     pc, lr
 147