uboot/board/esd/cms700/cms700.c
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   1/*
   2 * (C) Copyright 2005-2007
   3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#include <common.h>
  25#include <asm/processor.h>
  26#include <asm/io.h>
  27#include <command.h>
  28#include <malloc.h>
  29
  30DECLARE_GLOBAL_DATA_PTR;
  31
  32extern void lxt971_no_sleep(void);
  33
  34int board_early_init_f (void)
  35{
  36        /*
  37         * IRQ 0-15  405GP internally generated; active high; level sensitive
  38         * IRQ 16    405GP internally generated; active low; level sensitive
  39         * IRQ 17-24 RESERVED
  40         * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
  41         * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
  42         * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
  43         * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
  44         * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
  45         * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
  46         * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
  47         */
  48        mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
  49        mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
  50        mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
  51        mtdcr(UIC0PR, 0xFFFFFF80);       /* set int polarities */
  52        mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
  53        mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
  54        mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
  55
  56        /*
  57         * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
  58         */
  59        mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
  60
  61        /*
  62         * Reset CPLD via GPIO12 (CS3) pin
  63         */
  64        out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_PLD_RESET);
  65        udelay(1000); /* wait 1ms */
  66        out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_PLD_RESET);
  67        udelay(1000); /* wait 1ms */
  68
  69        return 0;
  70}
  71
  72int misc_init_r (void)
  73{
  74        /* adjust flash start and offset */
  75        gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
  76        gd->bd->bi_flashoffset = 0;
  77
  78        /*
  79         * Setup and enable EEPROM write protection
  80         */
  81        out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
  82
  83        return (0);
  84}
  85
  86
  87/*
  88 * Check Board Identity:
  89 */
  90#define LED_REG (CONFIG_SYS_PLD_BASE + 0x1000)
  91int checkboard (void)
  92{
  93        char str[64];
  94        int flashcnt;
  95        int delay;
  96
  97        puts ("Board: ");
  98
  99        if (getenv_f("serial#", str, sizeof(str))  == -1) {
 100                puts ("### No HW ID - assuming CMS700");
 101        } else {
 102                puts(str);
 103        }
 104
 105        printf(" (PLD-Version=%02d)\n",
 106               in_8((void *)(CONFIG_SYS_PLD_BASE + 0x1001)));
 107
 108        /*
 109         * Flash LEDs
 110         */
 111        for (flashcnt = 0; flashcnt < 3; flashcnt++) {
 112                out_8((void *)LED_REG, 0x00); /* LEDs off */
 113                for (delay = 0; delay < 100; delay++)
 114                        udelay(1000);
 115                out_8((void *)LED_REG, 0x0f); /* LEDs on */
 116                for (delay = 0; delay < 50; delay++)
 117                        udelay(1000);
 118        }
 119        out_8((void *)LED_REG, 0x70);
 120
 121        return 0;
 122}
 123
 124/* ------------------------------------------------------------------------- */
 125
 126#if defined(CONFIG_SYS_EEPROM_WREN)
 127/* Input: <dev_addr>  I2C address of EEPROM device to enable.
 128 *         <state>     -1: deliver current state
 129 *                     0: disable write
 130 *                     1: enable write
 131 *  Returns:           -1: wrong device address
 132 *                      0: dis-/en- able done
 133 *                   0/1: current state if <state> was -1.
 134 */
 135int eeprom_write_enable (unsigned dev_addr, int state)
 136{
 137        if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
 138                return -1;
 139        } else {
 140                switch (state) {
 141                case 1:
 142                        /* Enable write access, clear bit GPIO_SINT2. */
 143                        out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
 144                        state = 0;
 145                        break;
 146                case 0:
 147                        /* Disable write access, set bit GPIO_SINT2. */
 148                        out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
 149                        state = 0;
 150                        break;
 151                default:
 152                        /* Read current status back. */
 153                        state = (0 == (in_be32((void *)GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
 154                        break;
 155                }
 156        }
 157        return state;
 158}
 159
 160int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 161{
 162        int query = argc == 1;
 163        int state = 0;
 164
 165        if (query) {
 166                /* Query write access state. */
 167                state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
 168                if (state < 0) {
 169                        puts ("Query of write access state failed.\n");
 170                } else {
 171                        printf ("Write access for device 0x%0x is %sabled.\n",
 172                                CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
 173                        state = 0;
 174                }
 175        } else {
 176                if ('0' == argv[1][0]) {
 177                        /* Disable write access. */
 178                        state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
 179                } else {
 180                        /* Enable write access. */
 181                        state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
 182                }
 183                if (state < 0) {
 184                        puts ("Setup of write access state failed.\n");
 185                }
 186        }
 187
 188        return state;
 189}
 190
 191U_BOOT_CMD(eepwren,     2,      0,      do_eep_wren,
 192        "Enable / disable / query EEPROM write access",
 193        ""
 194);
 195#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
 196
 197/* ------------------------------------------------------------------------- */
 198
 199void reset_phy(void)
 200{
 201#ifdef CONFIG_LXT971_NO_SLEEP
 202
 203        /*
 204         * Disable sleep mode in LXT971
 205         */
 206        lxt971_no_sleep();
 207#endif
 208}
 209