1#ifndef ZUMA_PBB_H 2#define ZUMA_PBB_H 3 4#define MAX_NUM_BUFFER_PER_RING 32 5 6#ifdef __BIG_ENDIAN 7#define cpu_bits _be_s_bits /* use with le32_to_cpu only */ 8#define pci_bits _be_bits /* may contain swapped bytes, 9 but dont need le32_to_cpu */ 10#endif 11 12#ifdef __LITTLE_ENDIAN 13#define cpu_bits _le_bits 14#define pci_bits _le_bits 15#endif 16 17#define VENDOR_ID_ZUMA 0x1172 18#define DEVICE_ID_ZUMA_PBB 0x0004 19 20#define RXDBP(chan) (&sip->rx_desc[chan].base) /* ch*8 */ 21#define RXDP(chan) (&sip->rx_desc[chan].current) /* ch*8 + 4 */ 22#define TXDBP(chan) (&sip->tx_desc[chan].base) /* ch*8 + 64 */ 23#define TXDP(chan) (&sip->tx_desc[chan].current) /* ch*8 + 68 */ 24 25#define PBB_DMA_OWN_BIT 0x80000000 26#define PBB_DMA_LAST_BIT 0x40000000 27 28#define EOF_RX_FLAG 1 /* bit 0 */ 29#define EOB_RX_FLAG 2 /* bit 1 */ 30#define EOF_TX_FLAG 4 /* bit 2 */ 31#define EOB_TX_FLAG 8 /* bit 3 */ 32 33#define TX_MODE(m) (((m)&7) << 16) 34 35#define RX_DESC(i) (cs->rx_desc[i]) 36#define TX_DESC(i) (cs->tx_desc[i]) 37 38#define RX_CONTROL(i) (RX_DESC(i).control.word) 39#define RX_CONTROL_SIZE(i) (RX_DESC(i).control.rx.size) 40#define TX_CONTROL(i) (TX_DESC(i).control.word) 41 42#define RX_DATA_P(i) (&RX_DESC(i).ptr) 43#define TX_DATA_P(i) (&TX_DESC(i).ptr) 44 45typedef volatile unsigned char V8; 46typedef volatile unsigned short V16; 47typedef volatile unsigned int V32; 48 49/* RAM descriptor layout */ 50typedef struct _tag_dma_descriptor { 51 V32 ptr; 52 union { 53 struct { 54 V32 owner:1; 55 V32 last:1; 56 V32 reserved0: 10; 57 V32 tx_mode: 4; 58 59 V32 reserved1: 5; 60 V32 size: 11; 61 } tx; 62 struct { 63 V32 owner:1; 64 V32 last:1; 65 V32 reserved0: 14; 66 67 V32 reserved1: 5; 68 V32 size: 11; 69 } rx; 70 V32 word; 71 } control; 72} DMA_DESCRIPTOR; 73 74/* 75 * NOTE: DO NOT USE structure to write non-word values... all registers 76 * MUST be written 4 bytes at a time in SI version 0. 77 * Non-word writes will result in "unaccessed" bytes written as zero. 78 * 79 * Byte reads are allowed. 80 * 81 * V32 pads are because the registers are spaced every 8 bytes (64 bits) 82 * 83 */ 84 85/* NOTE!!! 4 dwords */ 86typedef struct _tag_dma_descriptor_ring { 87 DMA_DESCRIPTOR *base; 88 V32 pad1; /* skip high dword */ 89 volatile DMA_DESCRIPTOR *current; 90 V32 pad3; /* skip high dword */ 91} DMA_DESCRIPTOR_RING; 92 93/* 1 dword */ 94typedef union _tag_dma_generic { 95 struct { /* byte 3 2 1 0 */ 96 V32 chan7:4; /* bits 31-28 */ 97 V32 chan6:4; /* bits 27-24 */ 98 V32 chan5:4; /* bits 23-20 */ 99 V32 chan4:4; /* bits 19-16 */ 100 V32 chan3:4; /* bits 15-12 */ 101 V32 chan2:4; /* bits 11-8 */ 102 V32 chan1:4; /* bits 7-4 */ 103 V32 chan0:4; /* bits 3-0 */ 104 } _be_s_bits; 105 struct { /* byte 0 1 2 3 */ 106 V32 chan1:4; /* bits 7-4 */ 107 V32 chan0:4; /* bits 3-0 */ 108 V32 chan3:4; /* bits 15-12 */ 109 V32 chan2:4; /* bits 11-8 */ 110 V32 chan5:4; /* bits 23-20 */ 111 V32 chan4:4; /* bits 19-16 */ 112 V32 chan7:4; /* bits 31-28 */ 113 V32 chan6:4; /* bits 27-24 */ 114 } _be_bits; 115 struct { /* byte 0 1 2 3 */ 116 V32 chan0:4; /* bits 0-3 */ 117 V32 chan1:4; /* bits 4-7 */ 118 V32 chan2:4; /* bits 8-11 */ 119 V32 chan3:4; /* bits 12-15 */ 120 V32 chan4:4; /* bits 16-19 */ 121 V32 chan5:4; /* bits 20-23 */ 122 V32 chan6:4; /* bits 24-27 */ 123 V32 chan7:4; /* bits 28-31 */ 124 } _le_bits; 125 V8 byte[4]; 126 V32 word; 127} DMA_RXTX_ENABLE, DMA_RX_DELETE, 128 DMA_INT_STATUS, DMA_INT_MASK, 129 DMA_RX_LEVEL_STATUS, DMA_RX_LEVEL_INT_MASK; 130 131/* 1 dword */ 132typedef union _tag_dma_rx_timer{ 133 struct { 134 V32 res0:8; /* bits 32-24 */ 135 V32 res1:7; /* bits 23-17 */ 136 V32 enable:1; /* bit 16 */ 137 V32 value:16; /* bits 15-0 */ 138 } _be_s_bits; 139 struct { 140 /* crosses byte boundary. must use swap. */ 141 V32 s_value:16; /* bits 7-0,15-8 */ 142 V32 enable:1; /* bit 16 */ 143 V32 res1:7; /* bits 23-17 */ 144 V32 res0:8; /* bits 32-24 */ 145 } _be_bits; 146 struct { 147 V32 value:16; /* bits 0-15 */ 148 V32 enable:1; /* bit 16 */ 149 V32 res1:7; /* bits 17-23 */ 150 V32 res0:8; /* bits 24-32 */ 151 } _le_bits; 152 V8 byte[4]; 153 V32 word; 154} DMA_RX_TIMER; 155 156/* NOTE!!!: 2 dwords */ 157typedef struct _tag_dma_desc_level{ 158 union { 159 struct { 160 V32 res1:8; /* bits 31-24 */ 161 V32 res0:7; /* bits 23-17 */ 162 V32 write:1; /* bit 16 */ 163 V32 thresh:8; /* bits 15-8 */ 164 V32 level:8; /* bits 7-0 */ 165 } _be_s_bits; 166 struct { 167 V32 level:8; /* bits 7-0 */ 168 V32 thresh:8; /* bits 15-8 */ 169 V32 res0:7; /* bits 30-17 */ 170 V32 write:1; /* bit 16 */ 171 V32 res1:8; /* bits 31-24 */ 172 } _be_bits; 173 struct { 174 V32 level:8; /* bits 0-7 */ 175 V32 thresh:8; /* bits 8-15 */ 176 V32 write:1; /* bit 16 */ 177 V32 res0:7; /* bit 17-30 */ 178 V32 res1:8; /* bits 24-31 */ 179 } _le_bits; 180 V8 byte[4]; 181 V32 word; 182 } desc; 183 V32 pad1; 184} DMA_DESC_LEVEL; 185 186typedef struct _tag_pbb_dma_reg_map { 187 /* 0-15 (0x000-0x078) */ 188 DMA_DESCRIPTOR_RING rx_desc[8]; /* 4 dwords each, 128 bytes tot. */ 189 190 /* 16-31 (0x080-0x0f8) */ 191 DMA_DESCRIPTOR_RING tx_desc[8]; /* 4 dwords each, 128 bytes tot. */ 192 193 /* 32/33 (0x100/0x108) */ 194 V32 reserved_32; 195 V32 pad_32; 196 V32 reserved_33; 197 V32 pad_33; 198 199 /* 34 (0x110) */ 200 DMA_RXTX_ENABLE rxtx_enable; 201 V32 pad_34; 202 203 /* 35 (0x118) */ 204 DMA_RX_DELETE rx_delete; 205 V32 pad_35; 206 207 /* 36-38 (0x120-0x130) */ 208 DMA_INT_STATUS status; 209 V32 pad_36; 210 DMA_INT_STATUS last_status; 211 V32 pad_37; 212 DMA_INT_MASK int_mask; 213 V32 pad_38; 214 215 /* 39/40 (0x138/0x140) */ 216 union { 217 /* NOTE!! 4 dwords */ 218 struct { 219 V32 channel_3:8; 220 V32 channel_2:8; 221 V32 channel_1:8; 222 V32 channel_0:8; 223 V32 pad1; 224 V32 channel_7:8; 225 V32 channel_6:8; 226 V32 channel_5:8; 227 V32 channel_4:8; 228 V32 pad3; 229 } _be_s_bits; 230 struct { 231 V32 channel_0:8; 232 V32 channel_1:8; 233 V32 channel_2:8; 234 V32 channel_3:8; 235 V32 pad1; 236 V32 channel_4:8; 237 V32 channel_5:8; 238 V32 channel_6:8; 239 V32 channel_7:8; 240 V32 pad3; 241 } _be_bits, _le_bits; 242 V8 byte[16]; 243 V32 word[4]; 244 } rx_size; 245 246 /* 41/42 (0x148/0x150) */ 247 V32 reserved_41; 248 V32 pad_41; 249 V32 reserved_42; 250 V32 pad_42; 251 252 /* 43/44 (0x158/0x160) */ 253 DMA_RX_LEVEL_STATUS rx_level_status; 254 V32 pad_43; 255 DMA_RX_LEVEL_INT_MASK rx_level_int_mask; 256 V32 pad_44; 257 258 /* 45 (0x168) */ 259 DMA_RX_TIMER rx_timer; 260 V32 pad_45; 261 262 /* 46 (0x170) */ 263 V32 reserved_46; 264 V32 pad_46; 265 266 /* 47 (0x178) */ 267 V32 mbox_status; 268 V32 pad_47; 269 270 /* 48/49 (0x180/0x188) */ 271 V32 mbox_out; 272 V32 pad_48; 273 V32 mbox_in; 274 V32 pad_49; 275 276 /* 50 (0x190) */ 277 V32 config; 278 V32 pad_50; 279 280 /* 51/52 (0x198/0x1a0) */ 281 V32 c2a_ctr; 282 V32 pad_51; 283 V32 a2c_ctr; 284 V32 pad_52; 285 286 /* 53 (0x1a8) */ 287 union { 288 struct { 289 V32 rev_major:8; /* bits 31-24 */ 290 V32 rev_minor:8; /* bits 23-16 */ 291 V32 reserved:16; /* bits 15-0 */ 292 } _be_s_bits; 293 struct { 294 V32 s_reserved:16; /* bits 7-0, 15-8 */ 295 V32 rev_minor:8; /* bits 23-16 */ 296 V32 rev_major:8; /* bits 31-24 */ 297 } _be_bits; 298 struct { 299 V32 reserved:16; /* bits 0-15 */ 300 V32 rev_minor:8; /* bits 16-23 */ 301 V32 rev_major:8; /* bits 24-31 */ 302 } _le_bits; 303 V8 byte[4]; 304 V32 word; 305 } version; 306 V32 pad_53; 307 308 /* 54-59 (0x1b0-0x1d8) */ 309 V32 debug_54; 310 V32 pad_54; 311 V32 debug_55; 312 V32 pad_55; 313 V32 debug_56; 314 V32 pad_56; 315 V32 debug_57; 316 V32 pad_57; 317 V32 debug_58; 318 V32 pad_58; 319 V32 debug_59; 320 V32 pad_59; 321 322 /* 60 (0x1e0) */ 323 V32 timestamp; 324 V32 pad_60; 325 326 /* 61-63 (0x1e8-0x1f8) */ 327 V32 debug_61; 328 V32 pad_61; 329 V32 debug_62; 330 V32 pad_62; 331 V32 debug_63; 332 V32 pad_63; 333 334 /* 64-71 (0x200 - 0x238) */ 335 DMA_DESC_LEVEL rx_desc_level[8]; /* 2 dwords each, 32 bytes tot. */ 336 337 /* 72-98 (0x240 - 0x2f8) */ 338 /* reserved */ 339 340 /* 96-127 (0x300 - 0x3f8) */ 341 /* mirrors (0x100 - 0x1f8) */ 342 343} PBB_DMA_REG_MAP; 344 345 346#endif /* ZUMA_PBB_H */ 347