1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23#include <common.h>
24#include <ioports.h>
25#include <mpc8260.h>
26#include <asm/io.h>
27#include <asm/immap_8260.h>
28
29int hwc_flash_size (void);
30int hwc_local_sdram_size (void);
31int hwc_main_sdram_size (void);
32int hwc_serial_number (void);
33int hwc_mac_address (char *str);
34int hwc_manufact_date (char *str);
35int seeprom_read (int addr, uchar * data, int size);
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52const iop_conf_t iop_conf_tab[4][32] = {
53
54
55 {
56 {0, 1, 0, 0, 0, 0},
57 {0, 1, 0, 1, 0, 0},
58 {0, 1, 0, 1, 0, 0},
59 {0, 1, 0, 0, 0, 0},
60 {0, 1, 0, 0, 0, 0},
61 {0, 1, 0, 1, 0, 0},
62 {0, 1, 0, 1, 0, 1},
63 {0, 1, 0, 1, 0, 1},
64 {0, 1, 0, 1, 0, 1},
65 {0, 1, 0, 1, 0, 1},
66 {0, 1, 0, 1, 0, 1},
67 {0, 1, 0, 1, 0, 1},
68 {0, 1, 0, 1, 0, 1},
69 {0, 1, 0, 1, 0, 1},
70 {0, 1, 0, 0, 0, 0},
71 {0, 1, 0, 0, 0, 0},
72 {0, 1, 0, 0, 0, 0},
73 {0, 1, 0, 0, 0, 0},
74 {0, 1, 0, 0, 0, 0},
75 {0, 1, 0, 0, 0, 0},
76 {0, 1, 0, 0, 0, 0},
77 {0, 1, 0, 0, 0, 0},
78 {0, 1, 1, 1, 0, 1},
79 {0, 1, 1, 0, 0, 0},
80 {0, 0, 0, 0, 0, 0},
81 {0, 1, 1, 0, 0, 1},
82 {0, 0, 0, 1, 0, 0},
83 {0, 0, 0, 1, 0, 0},
84 {0, 0, 0, 1, 0, 0},
85 {0, 0, 0, 1, 0, 0},
86 {0, 0, 0, 1, 0, 0},
87 {0, 0, 0, 1, 0, 0}
88 },
89
90 {
91 {0, 0, 0, 1, 0, 0},
92 {0, 0, 0, 1, 0, 0},
93 {0, 0, 0, 1, 0, 0},
94 {0, 0, 0, 0, 0, 0},
95 {0, 1, 1, 0, 0, 1},
96 {0, 1, 1, 0, 0, 0},
97 {0, 0, 0, 1, 0, 0},
98 {0, 1, 1, 0, 0, 1},
99 {0, 0, 0, 1, 0, 0},
100 {0, 1, 0, 1, 0, 1},
101 {0, 1, 0, 0, 0, 0},
102 {0, 1, 0, 0, 0, 0},
103 {0, 1, 0, 0, 0, 0},
104 {0, 0, 0, 1, 0, 0},
105 {1, 1, 0, 0, 0, 0},
106 {1, 1, 0, 0, 0, 0},
107 {1, 1, 0, 1, 0, 0},
108 {1, 1, 0, 1, 0, 0},
109 {1, 1, 0, 0, 0, 0},
110 {1, 1, 0, 0, 0, 0},
111 {1, 1, 0, 0, 0, 0},
112 {1, 1, 0, 0, 0, 0},
113 {1, 1, 0, 0, 0, 0},
114 {1, 1, 0, 0, 0, 0},
115 {1, 1, 0, 1, 0, 1},
116 {1, 1, 0, 1, 0, 1},
117 {1, 1, 0, 1, 0, 1},
118 {1, 1, 0, 1, 0, 1},
119 {0, 0, 0, 0, 0, 0},
120 {0, 0, 0, 0, 0, 0},
121 {0, 0, 0, 0, 0, 0},
122 {0, 0, 0, 0, 0, 0},
123 },
124
125 {
126 {0, 1, 0, 0, 0, 1},
127 {0, 0, 0, 1, 0, 0},
128 {0, 1, 0, 0, 0, 1},
129 {0, 0, 0, 1, 0, 1},
130 {0, 1, 0, 0, 0, 1},
131 {0, 0, 0, 1, 0, 1},
132 {0, 1, 1, 1, 0, 1},
133 {1, 0, 0, 1, 0, 0},
134 {1, 0, 0, 1, 0, 0},
135 {0, 1, 0, 0, 0, 1},
136 {0, 0, 0, 1, 0, 0},
137 {0, 1, 0, 0, 0, 1},
138 {0, 1, 0, 0, 0, 1},
139 {1, 1, 0, 0, 0, 1},
140 {0, 1, 0, 0, 0, 0},
141 {1, 1, 0, 0, 0, 1},
142 {0, 1, 1, 0, 0, 0},
143 {0, 1, 1, 0, 0, 0},
144 {0, 1, 1, 0, 0, 0},
145 {0, 1, 1, 0, 0, 0},
146 {0, 0, 0, 1, 0, 0},
147 {0, 0, 0, 1, 0, 0},
148 {0, 0, 0, 1, 0, 1},
149 {0, 0, 0, 1, 0, 1},
150 {0, 1, 1, 0, 0, 0},
151 {0, 1, 1, 0, 0, 0},
152 {0, 0, 0, 1, 0, 0},
153 {0, 0, 0, 1, 0, 0},
154 {0, 0, 0, 1, 0, 0},
155 {0, 0, 0, 1, 0, 0},
156 {0, 0, 0, 0, 0, 1},
157 {0, 0, 0, 1, 0, 1},
158 },
159
160 {
161 {0, 0, 0, 1, 0, 1},
162 {0, 0, 0, 1, 0, 0},
163 {0, 1, 1, 0, 0, 0},
164 {0, 1, 1, 0, 0, 1},
165 {0, 1, 1, 0, 0, 0},
166 {0, 1, 1, 0, 0, 1},
167 {0, 0, 0, 1, 0, 1},
168 {0, 0, 0, 1, 0, 1},
169 {1, 0, 0, 1, 0, 1},
170 {0, 1, 1, 0, 0, 1},
171 {0, 1, 1, 0, 0, 0},
172 {0, 1, 1, 0, 0, 1},
173 {0, 0, 0, 1, 0, 0},
174 {0, 0, 0, 1, 0, 0},
175 {0, 1, 0, 1, 0, 0},
176 {0, 0, 0, 1, 0, 0},
177 {0, 0, 0, 1, 0, 0},
178 {0, 0, 0, 1, 0, 1},
179 {0, 0, 0, 1, 0, 1},
180 {0, 0, 0, 1, 0, 1},
181 {0, 0, 0, 1, 0, 0},
182 {0, 0, 0, 1, 0, 0},
183 {1, 1, 0, 1, 0, 1},
184 {1, 1, 0, 0, 0, 1},
185 {0, 1, 1, 0, 0, 0},
186 {0, 0, 0, 1, 0, 0},
187 {0, 0, 0, 0, 0, 0},
188 {0, 1, 0, 1, 0, 0},
189 {0, 0, 0, 0, 0, 0},
190 {0, 0, 0, 0, 0, 0},
191 {0, 0, 0, 0, 0, 0},
192 {0, 0, 0, 0, 0, 0},
193 }
194};
195
196phys_size_t initdram (int board_type)
197{
198 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
199 volatile memctl8260_t *memctl = &immap->im_memctl;
200 volatile uchar *base;
201 ulong maxsize;
202 int i;
203
204 memctl->memc_psrt = CONFIG_SYS_PSRT;
205 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
206
207#ifndef CONFIG_SYS_RAMBOOT
208 immap->im_siu_conf.sc_ppc_acr = 0x00000026;
209 immap->im_siu_conf.sc_ppc_alrh = 0x01276345;
210 immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF;
211 immap->im_siu_conf.sc_lcl_acr = 0x00000000;
212 immap->im_siu_conf.sc_lcl_alrh = 0x01234567;
213 immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF;
214 immap->im_siu_conf.sc_tescr1 = 0x00004000;
215 immap->im_siu_conf.sc_ltescr1 = 0x00004000;
216
217
218#define OP_VALUE 0x404A241A
219#define OP_VALUE_M (OP_VALUE & 0x87FFFFFF);
220 base = (uchar *) CONFIG_SYS_SDRAM_BASE;
221 memctl->memc_psdmr = 0x28000000 | OP_VALUE_M;
222 *base = 0xFF;
223 memctl->memc_psdmr = 0x08000000 | OP_VALUE_M;
224 for (i = 0; i < 8; i++)
225 *base = 0xFF;
226 memctl->memc_psdmr = 0x18000000 | OP_VALUE_M;
227 *(base + 0x110) = 0xFF;
228 memctl->memc_psdmr = OP_VALUE;
229 memctl->memc_lsdmr = 0x4086A522;
230 *base = 0xFF;
231
232
233
234
235
236
237 maxsize = (1 + (~memctl->memc_or1 | 0x7fff)) / 2;
238
239 maxsize = get_ram_size((long *)base, maxsize);
240
241 memctl->memc_or1 |= ~(maxsize - 1);
242
243 if (maxsize != hwc_main_sdram_size ())
244 printf ("Oops: memory test has not found all memory!\n");
245#endif
246
247 icache_enable ();
248
249 return (maxsize);
250}
251
252int checkboard (void)
253{
254 char string[32];
255
256 hwc_manufact_date (string);
257
258 printf ("Board: Interphase 4539 (#%d %s)\n",
259 hwc_serial_number (),
260 string);
261
262#ifdef DEBUG
263 printf ("Manufacturing date: %s\n", string);
264 printf ("Serial number : %d\n", hwc_serial_number ());
265 printf ("FLASH size : %d MB\n", hwc_flash_size () >> 20);
266 printf ("Main SDRAM size : %d MB\n", hwc_main_sdram_size () >> 20);
267 printf ("Local SDRAM size : %d MB\n", hwc_local_sdram_size () >> 20);
268 hwc_mac_address (string);
269 printf ("MAC address : %s\n", string);
270#endif
271
272 return 0;
273}
274
275int misc_init_r (void)
276{
277 char *s, str[32];
278 int num;
279
280 if ((s = getenv ("serial#")) == NULL &&
281 (num = hwc_serial_number ()) != -1) {
282 sprintf (str, "%06d", num);
283 setenv ("serial#", str);
284 }
285 if ((s = getenv ("ethaddr")) == NULL && hwc_mac_address (str) == 0) {
286 setenv ("ethaddr", str);
287 }
288 return (0);
289}
290
291
292
293
294
295
296int hwc_flash_size (void)
297{
298 uchar byte;
299
300 if (!seeprom_read (0x40, &byte, sizeof (byte))) {
301 switch ((byte >> 2) & 0x3) {
302 case 0x1:
303 return 0x0400000;
304 break;
305 case 0x2:
306 return 0x0800000;
307 break;
308 case 0x3:
309 return 0x1000000;
310 default:
311 return 0x0100000;
312 }
313 }
314 return -1;
315}
316int hwc_local_sdram_size (void)
317{
318 uchar byte;
319
320 if (!seeprom_read (0x40, &byte, sizeof (byte))) {
321 switch ((byte & 0x03)) {
322 case 0x1:
323 return 0x0800000;
324 case 0x2:
325 return 0x1000000;
326 default:
327 return 0;
328 }
329 }
330 return -1;
331}
332int hwc_main_sdram_size (void)
333{
334 uchar byte;
335
336 if (!seeprom_read (0x41, &byte, sizeof (byte))) {
337 return 0x1000000 << ((byte >> 5) & 0x7);
338 }
339 return -1;
340}
341int hwc_serial_number (void)
342{
343 int sn = -1;
344
345 if (!seeprom_read (0xa0, (uchar *) &sn, sizeof (sn))) {
346 sn = cpu_to_le32 (sn);
347 }
348 return sn;
349}
350int hwc_mac_address (char *str)
351{
352 char mac[6];
353
354 if (!seeprom_read (0xb0, (uchar *)mac, sizeof (mac))) {
355 sprintf (str, "%02x:%02x:%02x:%02x:%02x:%02x\n",
356 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
357 } else {
358 strcpy (str, "ERROR");
359 return -1;
360 }
361 return 0;
362}
363int hwc_manufact_date (char *str)
364{
365 uchar byte;
366 int value;
367
368 if (seeprom_read (0x92, &byte, sizeof (byte)))
369 goto out;
370 value = byte;
371 if (seeprom_read (0x93, &byte, sizeof (byte)))
372 goto out;
373 value += byte << 8;
374 sprintf (str, "%02d/%02d/%04d",
375 value & 0x1F, (value >> 5) & 0xF,
376 1980 + ((value >> 9) & 0x1FF));
377 return 0;
378
379 out:
380 strcpy (str, "ERROR");
381 return -1;
382}
383
384#define PSPAN_ADDR 0xF0020000
385#define EEPROM_REG 0x408
386#define EEPROM_READ_CMD 0xA000
387#define PSPAN_WRITE(a,v) \
388 *((volatile unsigned long *)(PSPAN_ADDR+(a))) = v; eieio()
389#define PSPAN_READ(a) \
390 *((volatile unsigned long *)(PSPAN_ADDR+(a)))
391
392int seeprom_read (int addr, uchar * data, int size)
393{
394 ulong val, cmd;
395 int i;
396
397 for (i = 0; i < size; i++) {
398
399 cmd = EEPROM_READ_CMD;
400 cmd |= ((addr + i) << 24) & 0xff000000;
401
402
403 while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
404 eieio ();
405
406
407 PSPAN_WRITE (EEPROM_REG, cmd);
408
409
410 while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
411 eieio ();
412
413 while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
414 eieio ();
415
416
417 if (val & 0x00000040) {
418 return -1;
419 } else {
420 data[i] = (val >> 16) & 0xff;
421 }
422 }
423 return 0;
424}
425