1/* 2 * Most of this taken from Redboot hal_platform_setup.h with cleanup 3 * 4 * NOTE: I haven't clean this up considerably, just enough to get it 5 * running. See hal_platform_setup.h for the source. See 6 * board/cradle/lowlevel_init.S for another PXA250 setup that is 7 * much cleaner. 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28#include <config.h> 29#include <version.h> 30#include <asm/arch/pxa-regs.h> 31 32DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE 33 34/* wait for coprocessor write complete */ 35 .macro CPWAIT reg 36 mrc p15,0,\reg,c2,c0,0 37 mov \reg,\reg 38 sub pc,pc,#4 39 .endm 40 41 42/* 43 * Memory setup 44 */ 45 46.globl lowlevel_init 47lowlevel_init: 48 49 mov r10, lr 50 51 /* Set up GPIO pins first ----------------------------------------- */ 52 53 ldr r0, =GPSR0 54 ldr r1, =CONFIG_SYS_GPSR0_VAL 55 str r1, [r0] 56 57 ldr r0, =GPSR1 58 ldr r1, =CONFIG_SYS_GPSR1_VAL 59 str r1, [r0] 60 61 ldr r0, =GPSR2 62 ldr r1, =CONFIG_SYS_GPSR2_VAL 63 str r1, [r0] 64 65 ldr r0, =GPCR0 66 ldr r1, =CONFIG_SYS_GPCR0_VAL 67 str r1, [r0] 68 69 ldr r0, =GPCR1 70 ldr r1, =CONFIG_SYS_GPCR1_VAL 71 str r1, [r0] 72 73 ldr r0, =GPCR2 74 ldr r1, =CONFIG_SYS_GPCR2_VAL 75 str r1, [r0] 76 77 ldr r0, =GPDR0 78 ldr r1, =CONFIG_SYS_GPDR0_VAL 79 str r1, [r0] 80 81 ldr r0, =GPDR1 82 ldr r1, =CONFIG_SYS_GPDR1_VAL 83 str r1, [r0] 84 85 ldr r0, =GPDR2 86 ldr r1, =CONFIG_SYS_GPDR2_VAL 87 str r1, [r0] 88 89 ldr r0, =GAFR0_L 90 ldr r1, =CONFIG_SYS_GAFR0_L_VAL 91 str r1, [r0] 92 93 ldr r0, =GAFR0_U 94 ldr r1, =CONFIG_SYS_GAFR0_U_VAL 95 str r1, [r0] 96 97 ldr r0, =GAFR1_L 98 ldr r1, =CONFIG_SYS_GAFR1_L_VAL 99 str r1, [r0] 100 101 ldr r0, =GAFR1_U 102 ldr r1, =CONFIG_SYS_GAFR1_U_VAL 103 str r1, [r0] 104 105 ldr r0, =GAFR2_L 106 ldr r1, =CONFIG_SYS_GAFR2_L_VAL 107 str r1, [r0] 108 109 ldr r0, =GAFR2_U 110 ldr r1, =CONFIG_SYS_GAFR2_U_VAL 111 str r1, [r0] 112 113 ldr r0, =PSSR /* enable GPIO pins */ 114 ldr r1, =CONFIG_SYS_PSSR_VAL 115 str r1, [r0] 116 117 /* ---------------------------------------------------------------- */ 118 /* Enable memory interface */ 119 /* */ 120 /* The sequence below is based on the recommended init steps */ 121 /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ 122 /* Chapter 10. */ 123 /* ---------------------------------------------------------------- */ 124 125 /* ---------------------------------------------------------------- */ 126 /* Step 1: Wait for at least 200 microsedonds to allow internal */ 127 /* clocks to settle. Only necessary after hard reset... */ 128 /* FIXME: can be optimized later */ 129 /* ---------------------------------------------------------------- */ 130 131 ldr r3, =OSCR /* reset the OS Timer Count to zero */ 132 mov r2, #0 133 str r2, [r3] 134 ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ 135 /* so 0x300 should be plenty */ 1361: 137 ldr r2, [r3] 138 cmp r4, r2 139 bgt 1b 140 141mem_init: 142 143 ldr r1, =MEMC_BASE /* get memory controller base addr. */ 144 145 /* ---------------------------------------------------------------- */ 146 /* Step 2a: Initialize Asynchronous static memory controller */ 147 /* ---------------------------------------------------------------- */ 148 149 /* MSC registers: timing, bus width, mem type */ 150 151 /* MSC0: nCS(0,1) */ 152 ldr r2, =CONFIG_SYS_MSC0_VAL 153 str r2, [r1, #MSC0_OFFSET] 154 ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ 155 /* that data latches */ 156 /* MSC1: nCS(2,3) */ 157 ldr r2, =CONFIG_SYS_MSC1_VAL 158 str r2, [r1, #MSC1_OFFSET] 159 ldr r2, [r1, #MSC1_OFFSET] 160 161 /* MSC2: nCS(4,5) */ 162 ldr r2, =CONFIG_SYS_MSC2_VAL 163 str r2, [r1, #MSC2_OFFSET] 164 ldr r2, [r1, #MSC2_OFFSET] 165 166 /* ---------------------------------------------------------------- */ 167 /* Step 2b: Initialize Card Interface */ 168 /* ---------------------------------------------------------------- */ 169 170 /* MECR: Memory Expansion Card Register */ 171 ldr r2, =CONFIG_SYS_MECR_VAL 172 str r2, [r1, #MECR_OFFSET] 173 ldr r2, [r1, #MECR_OFFSET] 174 175 /* MCMEM0: Card Interface slot 0 timing */ 176 ldr r2, =CONFIG_SYS_MCMEM0_VAL 177 str r2, [r1, #MCMEM0_OFFSET] 178 ldr r2, [r1, #MCMEM0_OFFSET] 179 180 /* MCMEM1: Card Interface slot 1 timing */ 181 ldr r2, =CONFIG_SYS_MCMEM1_VAL 182 str r2, [r1, #MCMEM1_OFFSET] 183 ldr r2, [r1, #MCMEM1_OFFSET] 184 185 /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ 186 ldr r2, =CONFIG_SYS_MCATT0_VAL 187 str r2, [r1, #MCATT0_OFFSET] 188 ldr r2, [r1, #MCATT0_OFFSET] 189 190 /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ 191 ldr r2, =CONFIG_SYS_MCATT1_VAL 192 str r2, [r1, #MCATT1_OFFSET] 193 ldr r2, [r1, #MCATT1_OFFSET] 194 195 /* MCIO0: Card Interface I/O Space Timing, slot 0 */ 196 ldr r2, =CONFIG_SYS_MCIO0_VAL 197 str r2, [r1, #MCIO0_OFFSET] 198 ldr r2, [r1, #MCIO0_OFFSET] 199 200 /* MCIO1: Card Interface I/O Space Timing, slot 1 */ 201 ldr r2, =CONFIG_SYS_MCIO1_VAL 202 str r2, [r1, #MCIO1_OFFSET] 203 ldr r2, [r1, #MCIO1_OFFSET] 204 205 /* ---------------------------------------------------------------- */ 206 /* Step 2c: Write FLYCNFG FIXME: what's that??? */ 207 /* ---------------------------------------------------------------- */ 208 209 210 /* ---------------------------------------------------------------- */ 211 /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ 212 /* ---------------------------------------------------------------- */ 213 214 /* Before accessing MDREFR we need a valid DRI field, so we set */ 215 /* this to power on defaults + DRI field. */ 216 217 ldr r3, =CONFIG_SYS_MDREFR_VAL 218 ldr r2, =0xFFF 219 and r3, r3, r2 220 ldr r4, =0x03ca4000 221 orr r4, r4, r3 222 str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ 223 ldr r4, [r1, #MDREFR_OFFSET] 224 225 /* Note: preserve the mdrefr value in r4 */ 226 227 228 /* ---------------------------------------------------------------- */ 229 /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ 230 /* ---------------------------------------------------------------- */ 231 232 /* Initialize SXCNFG register. Assert the enable bits */ 233 234 /* Write SXMRS to cause an MRS command to all enabled banks of */ 235 /* synchronous static memory. Note that SXLCR need not be written */ 236 /* at this time. */ 237 238 /* FIXME: we use async mode for now */ 239 240 241 /* ---------------------------------------------------------------- */ 242 /* Step 4: Initialize SDRAM */ 243 /* ---------------------------------------------------------------- */ 244 245 /* set MDREFR according to user define with exception of a few bits */ 246 247 ldr r4, =CONFIG_SYS_MDREFR_VAL 248 orr r4, r4, #(MDREFR_SLFRSH) 249 bic r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN) 250 str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ 251 ldr r4, [r1, #MDREFR_OFFSET] 252 253 /* Step 4b: de-assert MDREFR:SLFRSH. */ 254 255 bic r4, r4, #(MDREFR_SLFRSH) 256 str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ 257 ldr r4, [r1, #MDREFR_OFFSET] 258 259 260 /* Step 4c: assert MDREFR:E1PIN and E0PIO as desired */ 261 262 ldr r4, =CONFIG_SYS_MDREFR_VAL 263 str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ 264 ldr r4, [r1, #MDREFR_OFFSET] 265 266 267 /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ 268 /* configure but not enable each SDRAM partition pair. */ 269 270 ldr r4, =CONFIG_SYS_MDCNFG_VAL 271 bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) 272 273 str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ 274 ldr r4, [r1, #MDCNFG_OFFSET] 275 276 277 /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ 278 /* 100..200 µsec. */ 279 280 ldr r3, =OSCR /* reset the OS Timer Count to zero */ 281 mov r2, #0 282 str r2, [r3] 283 ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ 284 /* so 0x300 should be plenty */ 2851: 286 ldr r2, [r3] 287 cmp r4, r2 288 bgt 1b 289 290 291 /* Step 4f: Trigger a number (usually 8) refresh cycles by */ 292 /* attempting non-burst read or write accesses to disabled */ 293 /* SDRAM, as commonly specified in the power up sequence */ 294 /* documented in SDRAM data sheets. The address(es) used */ 295 /* for this purpose must not be cacheable. */ 296 297 ldr r3, =CONFIG_SYS_DRAM_BASE 298 str r2, [r3] 299 str r2, [r3] 300 str r2, [r3] 301 str r2, [r3] 302 str r2, [r3] 303 str r2, [r3] 304 str r2, [r3] 305 str r2, [r3] 306 307 308 /* Step 4g: Write MDCNFG with enable bits asserted */ 309 /* (MDCNFG:DEx set to 1). */ 310 311 ldr r3, [r1, #MDCNFG_OFFSET] 312 orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1) 313 str r3, [r1, #MDCNFG_OFFSET] 314 315 /* Step 4h: Write MDMRS. */ 316 317 ldr r2, =CONFIG_SYS_MDMRS_VAL 318 str r2, [r1, #MDMRS_OFFSET] 319 320 321 /* We are finished with Intel's memory controller initialisation */ 322 323 324 /* ---------------------------------------------------------------- */ 325 /* Disable (mask) all interrupts at interrupt controller */ 326 /* ---------------------------------------------------------------- */ 327 328initirqs: 329 330 mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ 331 ldr r2, =ICLR 332 str r1, [r2] 333 334 ldr r2, =ICMR /* mask all interrupts at the controller */ 335 str r1, [r2] 336 337 338 /* ---------------------------------------------------------------- */ 339 /* Clock initialisation */ 340 /* ---------------------------------------------------------------- */ 341 342initclks: 343 344 /* Disable the peripheral clocks, and set the core clock frequency */ 345 /* (hard-coding at 398.12MHz for now). */ 346 347 /* Turn Off ALL on-chip peripheral clocks for re-configuration */ 348 /* Note: See label 'ENABLECLKS' for the re-enabling */ 349 ldr r1, =CKEN 350 mov r2, #0 351 str r2, [r1] 352 353 354 /* default value in case no valid rotary switch setting is found */ 355 ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */ 356 357 /* ... and write the core clock config register */ 358 ldr r1, =CCCR 359 str r2, [r1] 360 361#ifdef RTC 362 /* enable the 32Khz oscillator for RTC and PowerManager */ 363 364 ldr r1, =OSCC 365 mov r2, #OSCC_OON 366 str r2, [r1] 367 368 /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ 369 /* has settled. */ 37060: 371 ldr r2, [r1] 372 ands r2, r2, #1 373 beq 60b 374#endif 375 376 /* ---------------------------------------------------------------- */ 377 /* */ 378 /* ---------------------------------------------------------------- */ 379 380 /* Save SDRAM size */ 381 ldr r1, =DRAM_SIZE 382 str r8, [r1] 383 384 /* Interrupt init: Mask all interrupts */ 385 ldr r0, =ICMR /* enable no sources */ 386 mov r1, #0 387 str r1, [r0] 388 389 /* FIXME */ 390 391#define NODEBUG 392#ifdef NODEBUG 393 /*Disable software and data breakpoints */ 394 mov r0,#0 395 mcr p15,0,r0,c14,c8,0 /* ibcr0 */ 396 mcr p15,0,r0,c14,c9,0 /* ibcr1 */ 397 mcr p15,0,r0,c14,c4,0 /* dbcon */ 398 399 /*Enable all debug functionality */ 400 mov r0,#0x80000000 401 mcr p14,0,r0,c10,c0,0 /* dcsr */ 402 403#endif 404 405 /* ---------------------------------------------------------------- */ 406 /* End lowlevel_init */ 407 /* ---------------------------------------------------------------- */ 408 409endlowlevel_init: 410 411 mov pc, lr 412