LXR uboot/board/t3corp/init.S

   1/*
   2 * (C) Copyright 2010
   3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#include <ppc_asm.tmpl>
  25#include <config.h>
  26#include <asm/mmu.h>
  27
  28/*
  29 * TLB TABLE
  30 *
  31 * This table is used by the cpu boot code to setup the initial tlb
  32 * entries. Rather than make broad assumptions in the cpu source tree,
  33 * this table lets each board set things up however they like.
  34 *
  35 *  Pointer to the table is returned in r1
  36 *
  37 */
  38        .section .bootpg,"ax"
  39        .globl tlbtab
  40
  41tlbtab:
  42        tlbtab_start
  43
  44        /*
  45         * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
  46         * use the speed up boot process. It is patched after relocation to
  47         * enable SA_I
  48         */
  49        tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M,
  50                 CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G)
  51
  52        /*
  53         * TLB entries for SDRAM are not needed on this platform.
  54         * They are dynamically generated in the DDR(2) detection
  55         * routine.
  56         */
  57
  58#ifdef CONFIG_SYS_INIT_RAM_DCACHE
  59        /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
  60        tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0,
  61                 AC_RWX | SA_G)
  62#endif
  63
  64        tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xc,
  65                 AC_RW | SA_IG)
  66        tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xc,
  67                 AC_RW | SA_IG)
  68        tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xd,
  69                 AC_RW | SA_IG)
  70
  71        tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xd,
  72                 AC_RW | SA_IG)
  73        tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xd,
  74                 AC_RW | SA_IG)
  75        tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xd,
  76                 AC_RW | SA_IG)
  77        tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xd,
  78                 AC_RW | SA_IG)
  79
  80        /* PCIe UTL register */
  81        tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xc, AC_RW | SA_IG)
  82
  83        /* TLB-entry for FPGA(s) */
  84        tlbentry(CONFIG_SYS_FPGA1_BASE, SZ_16M, CONFIG_SYS_FPGA1_BASE, 4,
  85                 AC_RW | SA_IG)
  86        tlbentry(CONFIG_SYS_FPGA1_BASE + (16 << 20), SZ_16M,
  87                 CONFIG_SYS_FPGA1_BASE + (16 << 20), 4, AC_RW | SA_IG)
  88        tlbentry(CONFIG_SYS_FPGA2_BASE, SZ_16M, CONFIG_SYS_FPGA2_BASE, 4,
  89                 AC_RW | SA_IG)
  90        tlbentry(CONFIG_SYS_FPGA3_BASE, SZ_16M, CONFIG_SYS_FPGA3_BASE, 4,
  91                 AC_RW | SA_IG)
  92
  93        /* TLB-entry for OCM */
  94        tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4,
  95                 AC_RWX | SA_I)
  96
  97        /* TLB-entry for Local Configuration registers => peripherals */
  98        tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M,
  99                 CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_RWX | SA_IG)
 100
 101        tlbtab_end
 102