1/* 2 * MPC8xx Communication Processor Module. 3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 4 * 5 * (C) Copyright 2000-2006 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7 * 8 * This file contains structures and information for the communication 9 * processor channels. Some CPM control and status is available 10 * throught the MPC8xx internal memory map. See immap.h for details. 11 * This file only contains what I need for the moment, not the total 12 * CPM capabilities. I (or someone else) will add definitions as they 13 * are needed. -- Dan 14 * 15 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512 16 * bytes of the DP RAM and relocates the I2C parameter area to the 17 * IDMA1 space. The remaining DP RAM is available for buffer descriptors 18 * or other use. 19 */ 20#ifndef __CPM_8XX__ 21#define __CPM_8XX__ 22 23#include <linux/config.h> 24#include <asm/8xx_immap.h> 25 26/* CPM Command register. 27*/ 28#define CPM_CR_RST ((ushort)0x8000) 29#define CPM_CR_OPCODE ((ushort)0x0f00) 30#define CPM_CR_CHAN ((ushort)0x00f0) 31#define CPM_CR_FLG ((ushort)0x0001) 32 33/* Some commands (there are more...later) 34*/ 35#define CPM_CR_INIT_TRX ((ushort)0x0000) 36#define CPM_CR_INIT_RX ((ushort)0x0001) 37#define CPM_CR_INIT_TX ((ushort)0x0002) 38#define CPM_CR_HUNT_MODE ((ushort)0x0003) 39#define CPM_CR_STOP_TX ((ushort)0x0004) 40#define CPM_CR_RESTART_TX ((ushort)0x0006) 41#define CPM_CR_SET_GADDR ((ushort)0x0008) 42 43/* Channel numbers. 44*/ 45#define CPM_CR_CH_SCC1 ((ushort)0x0000) 46#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */ 47#define CPM_CR_CH_SCC2 ((ushort)0x0004) 48#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI/IDMA2/Timers */ 49#define CPM_CR_CH_SCC3 ((ushort)0x0008) 50#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */ 51#define CPM_CR_CH_SCC4 ((ushort)0x000c) 52#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */ 53 54#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) 55 56/* 57 * DPRAM defines and allocation functions 58 */ 59 60/* The dual ported RAM is multi-functional. Some areas can be (and are 61 * being) used for microcode. There is an area that can only be used 62 * as data ram for buffer descriptors, which is all we use right now. 63 * Currently the first 512 and last 256 bytes are used for microcode. 64 */ 65#ifdef CONFIG_SYS_ALLOC_DPRAM 66 67#define CPM_DATAONLY_BASE ((uint)0x0800) 68#define CPM_DATAONLY_SIZE ((uint)0x0700) 69#define CPM_DP_NOSPACE ((uint)0x7fffffff) 70 71#else 72 73#define CPM_SERIAL_BASE 0x0800 74#define CPM_I2C_BASE 0x0820 75#define CPM_SPI_BASE 0x0840 76#define CPM_FEC_BASE 0x0860 77#define CPM_SERIAL2_BASE 0x08E0 78#define CPM_SCC_BASE 0x0900 79#define CPM_POST_BASE 0x0980 80#define CPM_WLKBD_BASE 0x0a00 81 82#endif 83 84#ifndef CONFIG_SYS_CPM_POST_WORD_ADDR 85#define CPM_POST_WORD_ADDR 0x07FC 86#else 87#define CPM_POST_WORD_ADDR CONFIG_SYS_CPM_POST_WORD_ADDR 88#endif 89 90#ifndef CONFIG_SYS_CPM_BOOTCOUNT_ADDR 91#define CPM_BOOTCOUNT_ADDR (CPM_POST_WORD_ADDR - 2*sizeof(ulong)) 92#else 93#define CPM_BOOTCOUNT_ADDR CONFIG_SYS_CPM_BOOTCOUNT_ADDR 94#endif 95 96#define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */ 97 98/* Export the base address of the communication processor registers 99 * and dual port ram. 100 */ 101extern cpm8xx_t *cpmp; /* Pointer to comm processor */ 102 103/* Buffer descriptors used by many of the CPM protocols. 104*/ 105typedef struct cpm_buf_desc { 106 ushort cbd_sc; /* Status and Control */ 107 ushort cbd_datlen; /* Data length in buffer */ 108 uint cbd_bufaddr; /* Buffer address in host memory */ 109} cbd_t; 110 111#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ 112#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ 113#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ 114#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ 115#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */ 116#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ 117#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ 118#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ 119#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ 120#define BD_SC_BR ((ushort)0x0020) /* Break received */ 121#define BD_SC_FR ((ushort)0x0010) /* Framing error */ 122#define BD_SC_PR ((ushort)0x0008) /* Parity error */ 123#define BD_SC_OV ((ushort)0x0002) /* Overrun */ 124#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */ 125 126/* Parameter RAM offsets. 127*/ 128#define PROFF_SCC1 ((uint)0x0000) 129#define PROFF_IIC ((uint)0x0080) 130#define PROFF_SCC2 ((uint)0x0100) 131#define PROFF_SPI ((uint)0x0180) 132#define PROFF_SCC3 ((uint)0x0200) 133#define PROFF_SMC1 ((uint)0x0280) 134#define PROFF_SCC4 ((uint)0x0300) 135#define PROFF_SMC2 ((uint)0x0380) 136 137/* Define enough so I can at least use the serial port as a UART. 138 * The MBX uses SMC1 as the host serial port. 139 */ 140typedef struct smc_uart { 141 ushort smc_rbase; /* Rx Buffer descriptor base address */ 142 ushort smc_tbase; /* Tx Buffer descriptor base address */ 143 u_char smc_rfcr; /* Rx function code */ 144 u_char smc_tfcr; /* Tx function code */ 145 ushort smc_mrblr; /* Max receive buffer length */ 146 uint smc_rstate; /* Internal */ 147 uint smc_idp; /* Internal */ 148 ushort smc_rbptr; /* Internal */ 149 ushort smc_ibc; /* Internal */ 150 uint smc_rxtmp; /* Internal */ 151 uint smc_tstate; /* Internal */ 152 uint smc_tdp; /* Internal */ 153 ushort smc_tbptr; /* Internal */ 154 ushort smc_tbc; /* Internal */ 155 uint smc_txtmp; /* Internal */ 156 ushort smc_maxidl; /* Maximum idle characters */ 157 ushort smc_tmpidl; /* Temporary idle counter */ 158 ushort smc_brklen; /* Last received break length */ 159 ushort smc_brkec; /* rcv'd break condition counter */ 160 ushort smc_brkcr; /* xmt break count register */ 161 ushort smc_rmask; /* Temporary bit mask */ 162 u_char res1[8]; 163 ushort smc_rpbase; /* Relocation pointer */ 164} smc_uart_t; 165 166/* Function code bits. 167*/ 168#define SMC_EB ((u_char)0x10) /* Set big endian byte order */ 169 170/* SMC uart mode register. 171*/ 172#define SMCMR_REN ((ushort)0x0001) 173#define SMCMR_TEN ((ushort)0x0002) 174#define SMCMR_DM ((ushort)0x000c) 175#define SMCMR_SM_GCI ((ushort)0x0000) 176#define SMCMR_SM_UART ((ushort)0x0020) 177#define SMCMR_SM_TRANS ((ushort)0x0030) 178#define SMCMR_SM_MASK ((ushort)0x0030) 179#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ 180#define SMCMR_REVD SMCMR_PM_EVEN 181#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ 182#define SMCMR_BS SMCMR_PEN 183#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ 184#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ 185#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) 186 187/* SMC2 as Centronics parallel printer. It is half duplex, in that 188 * it can only receive or transmit. The parameter ram values for 189 * each direction are either unique or properly overlap, so we can 190 * include them in one structure. 191 */ 192typedef struct smc_centronics { 193 ushort scent_rbase; 194 ushort scent_tbase; 195 u_char scent_cfcr; 196 u_char scent_smask; 197 ushort scent_mrblr; 198 uint scent_rstate; 199 uint scent_r_ptr; 200 ushort scent_rbptr; 201 ushort scent_r_cnt; 202 uint scent_rtemp; 203 uint scent_tstate; 204 uint scent_t_ptr; 205 ushort scent_tbptr; 206 ushort scent_t_cnt; 207 uint scent_ttemp; 208 ushort scent_max_sl; 209 ushort scent_sl_cnt; 210 ushort scent_character1; 211 ushort scent_character2; 212 ushort scent_character3; 213 ushort scent_character4; 214 ushort scent_character5; 215 ushort scent_character6; 216 ushort scent_character7; 217 ushort scent_character8; 218 ushort scent_rccm; 219 ushort scent_rccr; 220} smc_cent_t; 221 222/* Centronics Status Mask Register. 223*/ 224#define SMC_CENT_F ((u_char)0x08) 225#define SMC_CENT_PE ((u_char)0x04) 226#define SMC_CENT_S ((u_char)0x02) 227 228/* SMC Event and Mask register. 229*/ 230#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ 231#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ 232#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */ 233#define SMCM_BSY ((unsigned char)0x04) 234#define SMCM_TX ((unsigned char)0x02) 235#define SMCM_RX ((unsigned char)0x01) 236 237/* Baud rate generators. 238*/ 239#define CPM_BRG_RST ((uint)0x00020000) 240#define CPM_BRG_EN ((uint)0x00010000) 241#define CPM_BRG_EXTC_INT ((uint)0x00000000) 242#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000) 243#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000) 244#define CPM_BRG_ATB ((uint)0x00002000) 245#define CPM_BRG_CD_MASK ((uint)0x00001ffe) 246#define CPM_BRG_DIV16 ((uint)0x00000001) 247 248/* SI Clock Route Register 249*/ 250#define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000) 251#define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000) 252#define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800) 253#define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100) 254#define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000) 255#define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000) 256#define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000) 257#define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000) 258 259/* SCCs. 260*/ 261#define SCC_GSMRH_IRP ((uint)0x00040000) 262#define SCC_GSMRH_GDE ((uint)0x00010000) 263#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) 264#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) 265#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) 266#define SCC_GSMRH_REVD ((uint)0x00002000) 267#define SCC_GSMRH_TRX ((uint)0x00001000) 268#define SCC_GSMRH_TTX ((uint)0x00000800) 269#define SCC_GSMRH_CDP ((uint)0x00000400) 270#define SCC_GSMRH_CTSP ((uint)0x00000200) 271#define SCC_GSMRH_CDS ((uint)0x00000100) 272#define SCC_GSMRH_CTSS ((uint)0x00000080) 273#define SCC_GSMRH_TFL ((uint)0x00000040) 274#define SCC_GSMRH_RFW ((uint)0x00000020) 275#define SCC_GSMRH_TXSY ((uint)0x00000010) 276#define SCC_GSMRH_SYNL16 ((uint)0x0000000c) 277#define SCC_GSMRH_SYNL8 ((uint)0x00000008) 278#define SCC_GSMRH_SYNL4 ((uint)0x00000004) 279#define SCC_GSMRH_RTSM ((uint)0x00000002) 280#define SCC_GSMRH_RSYN ((uint)0x00000001) 281 282#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ 283#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) 284#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) 285#define SCC_GSMRL_EDGE_POS ((uint)0x20000000) 286#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) 287#define SCC_GSMRL_TCI ((uint)0x10000000) 288#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) 289#define SCC_GSMRL_TSNC_4 ((uint)0x08000000) 290#define SCC_GSMRL_TSNC_14 ((uint)0x04000000) 291#define SCC_GSMRL_TSNC_INF ((uint)0x00000000) 292#define SCC_GSMRL_RINV ((uint)0x02000000) 293#define SCC_GSMRL_TINV ((uint)0x01000000) 294#define SCC_GSMRL_TPL_128 ((uint)0x00c00000) 295#define SCC_GSMRL_TPL_64 ((uint)0x00a00000) 296#define SCC_GSMRL_TPL_48 ((uint)0x00800000) 297#define SCC_GSMRL_TPL_32 ((uint)0x00600000) 298#define SCC_GSMRL_TPL_16 ((uint)0x00400000) 299#define SCC_GSMRL_TPL_8 ((uint)0x00200000) 300#define SCC_GSMRL_TPL_NONE ((uint)0x00000000) 301#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) 302#define SCC_GSMRL_TPP_01 ((uint)0x00100000) 303#define SCC_GSMRL_TPP_10 ((uint)0x00080000) 304#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) 305#define SCC_GSMRL_TEND ((uint)0x00040000) 306#define SCC_GSMRL_TDCR_32 ((uint)0x00030000) 307#define SCC_GSMRL_TDCR_16 ((uint)0x00020000) 308#define SCC_GSMRL_TDCR_8 ((uint)0x00010000) 309#define SCC_GSMRL_TDCR_1 ((uint)0x00000000) 310#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) 311#define SCC_GSMRL_RDCR_16 ((uint)0x00008000) 312#define SCC_GSMRL_RDCR_8 ((uint)0x00004000) 313#define SCC_GSMRL_RDCR_1 ((uint)0x00000000) 314#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) 315#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) 316#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) 317#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) 318#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) 319#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) 320#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) 321#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) 322#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) 323#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) 324#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ 325#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) 326#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) 327#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) 328#define SCC_GSMRL_ENR ((uint)0x00000020) 329#define SCC_GSMRL_ENT ((uint)0x00000010) 330#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) 331#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) 332#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) 333#define SCC_GSMRL_MODE_V14 ((uint)0x00000007) 334#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) 335#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) 336#define SCC_GSMRL_MODE_UART ((uint)0x00000004) 337#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) 338#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) 339#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) 340 341#define SCC_TODR_TOD ((ushort)0x8000) 342 343/* SCC Event and Mask register. 344*/ 345#define SCCM_TXE ((unsigned char)0x10) 346#define SCCM_BSY ((unsigned char)0x04) 347#define SCCM_TX ((unsigned char)0x02) 348#define SCCM_RX ((unsigned char)0x01) 349 350typedef struct scc_param { 351 ushort scc_rbase; /* Rx Buffer descriptor base address */ 352 ushort scc_tbase; /* Tx Buffer descriptor base address */ 353 u_char scc_rfcr; /* Rx function code */ 354 u_char scc_tfcr; /* Tx function code */ 355 ushort scc_mrblr; /* Max receive buffer length */ 356 uint scc_rstate; /* Internal */ 357 uint scc_idp; /* Internal */ 358 ushort scc_rbptr; /* Internal */ 359 ushort scc_ibc; /* Internal */ 360 uint scc_rxtmp; /* Internal */ 361 uint scc_tstate; /* Internal */ 362 uint scc_tdp; /* Internal */ 363 ushort scc_tbptr; /* Internal */ 364 ushort scc_tbc; /* Internal */ 365 uint scc_txtmp; /* Internal */ 366 uint scc_rcrc; /* Internal */ 367 uint scc_tcrc; /* Internal */ 368} sccp_t; 369 370/* Function code bits. 371*/ 372#define SCC_EB ((u_char)0x10) /* Set big endian byte order */ 373 374/* CPM Ethernet through SCCx. 375 */ 376typedef struct scc_enet { 377 sccp_t sen_genscc; 378 uint sen_cpres; /* Preset CRC */ 379 uint sen_cmask; /* Constant mask for CRC */ 380 uint sen_crcec; /* CRC Error counter */ 381 uint sen_alec; /* alignment error counter */ 382 uint sen_disfc; /* discard frame counter */ 383 ushort sen_pads; /* Tx short frame pad character */ 384 ushort sen_retlim; /* Retry limit threshold */ 385 ushort sen_retcnt; /* Retry limit counter */ 386 ushort sen_maxflr; /* maximum frame length register */ 387 ushort sen_minflr; /* minimum frame length register */ 388 ushort sen_maxd1; /* maximum DMA1 length */ 389 ushort sen_maxd2; /* maximum DMA2 length */ 390 ushort sen_maxd; /* Rx max DMA */ 391 ushort sen_dmacnt; /* Rx DMA counter */ 392 ushort sen_maxb; /* Max BD byte count */ 393 ushort sen_gaddr1; /* Group address filter */ 394 ushort sen_gaddr2; 395 ushort sen_gaddr3; 396 ushort sen_gaddr4; 397 uint sen_tbuf0data0; /* Save area 0 - current frame */ 398 uint sen_tbuf0data1; /* Save area 1 - current frame */ 399 uint sen_tbuf0rba; /* Internal */ 400 uint sen_tbuf0crc; /* Internal */ 401 ushort sen_tbuf0bcnt; /* Internal */ 402 ushort sen_paddrh; /* physical address (MSB) */ 403 ushort sen_paddrm; 404 ushort sen_paddrl; /* physical address (LSB) */ 405 ushort sen_pper; /* persistence */ 406 ushort sen_rfbdptr; /* Rx first BD pointer */ 407 ushort sen_tfbdptr; /* Tx first BD pointer */ 408 ushort sen_tlbdptr; /* Tx last BD pointer */ 409 uint sen_tbuf1data0; /* Save area 0 - current frame */ 410 uint sen_tbuf1data1; /* Save area 1 - current frame */ 411 uint sen_tbuf1rba; /* Internal */ 412 uint sen_tbuf1crc; /* Internal */ 413 ushort sen_tbuf1bcnt; /* Internal */ 414 ushort sen_txlen; /* Tx Frame length counter */ 415 ushort sen_iaddr1; /* Individual address filter */ 416 ushort sen_iaddr2; 417 ushort sen_iaddr3; 418 ushort sen_iaddr4; 419 ushort sen_boffcnt; /* Backoff counter */ 420 421 /* NOTE: Some versions of the manual have the following items 422 * incorrectly documented. Below is the proper order. 423 */ 424 ushort sen_taddrh; /* temp address (MSB) */ 425 ushort sen_taddrm; 426 ushort sen_taddrl; /* temp address (LSB) */ 427} scc_enet_t; 428 429/********************************************************************** 430 * 431 * Board specific configuration settings. 432 * 433 * Please note that we use the presence of a #define SCC_ENET and/or 434 * #define FEC_ENET to enable the SCC resp. FEC ethernet drivers. 435 **********************************************************************/ 436 437 438/*** ADS *************************************************************/ 439 440#if defined(CONFIG_MPC860) && defined(CONFIG_ADS) 441/* This ENET stuff is for the MPC860ADS with ethernet on SCC1. 442 */ 443 444#define PROFF_ENET PROFF_SCC1 445#define CPM_CR_ENET CPM_CR_CH_SCC1 446#define SCC_ENET 0 447 448#define PA_ENET_RXD ((ushort)0x0001) 449#define PA_ENET_TXD ((ushort)0x0002) 450#define PA_ENET_TCLK ((ushort)0x0100) 451#define PA_ENET_RCLK ((ushort)0x0200) 452 453#define PB_ENET_TENA ((uint)0x00001000) 454 455#define PC_ENET_CLSN ((ushort)0x0010) 456#define PC_ENET_RENA ((ushort)0x0020) 457 458#define SICR_ENET_MASK ((uint)0x000000ff) 459#define SICR_ENET_CLKRT ((uint)0x0000002c) 460 461/* 68160 PHY control */ 462 463#define PC_ENET_ETHLOOP ((ushort)0x0800) 464#define PC_ENET_TPFLDL ((ushort)0x0400) 465#define PC_ENET_TPSQEL ((ushort)0x0200) 466 467#endif /* MPC860ADS */ 468 469/*** AMX860 **********************************************/ 470 471#if defined(CONFIG_AMX860) 472 473/* This ENET stuff is for the AMX860 with ethernet on SCC1. 474 */ 475 476#define PROFF_ENET PROFF_SCC1 477#define CPM_CR_ENET CPM_CR_CH_SCC1 478#define SCC_ENET 0 479 480#define PA_ENET_RXD ((ushort)0x0001) 481#define PA_ENET_TXD ((ushort)0x0002) 482#define PA_ENET_TCLK ((ushort)0x0400) 483#define PA_ENET_RCLK ((ushort)0x0800) 484 485#define PB_ENET_TENA ((uint)0x00001000) 486 487#define PC_ENET_CLSN ((ushort)0x0010) 488#define PC_ENET_RENA ((ushort)0x0020) 489 490#define SICR_ENET_MASK ((uint)0x000000ff) 491#define SICR_ENET_CLKRT ((uint)0x0000003e) 492 493/* 68160 PHY control */ 494 495#define PB_ENET_ETHLOOP ((uint)0x00020000) 496#define PB_ENET_TPFLDL ((uint)0x00010000) 497#define PB_ENET_TPSQEL ((uint)0x00008000) 498#define PD_ENET_ETH_EN ((ushort)0x0004) 499 500#endif /* CONFIG_AMX860 */ 501 502/*** BSEIP **********************************************************/ 503 504#ifdef CONFIG_BSEIP 505/* This ENET stuff is for the MPC823 with ethernet on SCC2. 506 * This is unique to the BSE ip-Engine board. 507 */ 508#define PROFF_ENET PROFF_SCC2 509#define CPM_CR_ENET CPM_CR_CH_SCC2 510#define SCC_ENET 1 511#define PA_ENET_RXD ((ushort)0x0004) 512#define PA_ENET_TXD ((ushort)0x0008) 513#define PA_ENET_TCLK ((ushort)0x0100) 514#define PA_ENET_RCLK ((ushort)0x0200) 515#define PB_ENET_TENA ((uint)0x00002000) 516#define PC_ENET_CLSN ((ushort)0x0040) 517#define PC_ENET_RENA ((ushort)0x0080) 518 519/* BSE uses port B and C bits for PHY control also. 520*/ 521#define PB_BSE_POWERUP ((uint)0x00000004) 522#define PB_BSE_FDXDIS ((uint)0x00008000) 523#define PC_BSE_LOOPBACK ((ushort)0x0800) 524 525#define SICR_ENET_MASK ((uint)0x0000ff00) 526#define SICR_ENET_CLKRT ((uint)0x00002c00) 527#endif /* CONFIG_BSEIP */ 528 529/*** BSEIP **********************************************************/ 530 531#ifdef CONFIG_FLAGADM 532/* Enet configuration for the FLAGADM */ 533/* Enet on SCC2 */ 534 535#define PROFF_ENET PROFF_SCC2 536#define CPM_CR_ENET CPM_CR_CH_SCC2 537#define SCC_ENET 1 538#define PA_ENET_RXD ((ushort)0x0004) 539#define PA_ENET_TXD ((ushort)0x0008) 540#define PA_ENET_TCLK ((ushort)0x0100) 541#define PA_ENET_RCLK ((ushort)0x0400) 542#define PB_ENET_TENA ((uint)0x00002000) 543#define PC_ENET_CLSN ((ushort)0x0040) 544#define PC_ENET_RENA ((ushort)0x0080) 545 546#define SICR_ENET_MASK ((uint)0x0000ff00) 547#define SICR_ENET_CLKRT ((uint)0x00003400) 548#endif /* CONFIG_FLAGADM */ 549 550/*** C2MON **********************************************************/ 551 552#ifdef CONFIG_C2MON 553 554# ifndef CONFIG_FEC_ENET /* use SCC for 10Mbps Ethernet */ 555# error "Ethernet on SCC not supported on C2MON Board!" 556# else /* Use FEC for Fast Ethernet */ 557 558#undef SCC_ENET 559#define FEC_ENET 560 561#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ 562#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ 563#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ 564#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ 565#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ 566#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ 567#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ 568#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ 569#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ 570#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ 571#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ 572#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ 573#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ 574 575#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ 576 577# endif /* CONFIG_FEC_ENET */ 578#endif /* CONFIG_C2MON */ 579 580/*********************************************************************/ 581 582 583/*** CCM and PCU E ***********************************************/ 584 585/* The PCU E and CCM use the FEC on a MPC860T for Ethernet */ 586 587#if defined (CONFIG_PCU_E) || defined(CONFIG_CCM) 588 589#define FEC_ENET /* use FEC for EThernet */ 590#undef SCC_ENET 591 592#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ 593#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ 594#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ 595#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ 596#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ 597#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ 598#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ 599#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ 600#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ 601#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ 602#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ 603#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ 604#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ 605 606#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ 607 608#endif /* CONFIG_PCU_E, CONFIG_CCM */ 609 610/*** ELPT860 *********************************************************/ 611 612#ifdef CONFIG_ELPT860 613/* Bits in parallel I/O port registers that have to be set/cleared 614 * to configure the pins for SCC1 use. 615 */ 616# define PROFF_ENET PROFF_SCC1 617# define CPM_CR_ENET CPM_CR_CH_SCC1 618# define SCC_ENET 0 619 620# define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ 621# define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ 622# define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ 623# define PA_ENET_TCLK ((ushort)0x0200) /* PA 6 */ 624 625# define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ 626# define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ 627# define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ 628 629/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK1) to 630 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. 631 */ 632# define SICR_ENET_MASK ((uint)0x000000FF) 633# define SICR_ENET_CLKRT ((uint)0x00000025) 634#endif /* CONFIG_ELPT860 */ 635 636/*** ESTEEM 192E **************************************************/ 637#ifdef CONFIG_ESTEEM192E 638/* ESTEEM192E 639 * This ENET stuff is for the MPC850 with ethernet on SCC2. This 640 * is very similar to the RPX-Lite configuration. 641 * Note TENA , LOOPBACK , FDPLEX_DIS on Port B. 642 */ 643 644#define PROFF_ENET PROFF_SCC2 645#define CPM_CR_ENET CPM_CR_CH_SCC2 646#define SCC_ENET 1 647 648#define PA_ENET_RXD ((ushort)0x0004) 649#define PA_ENET_TXD ((ushort)0x0008) 650#define PA_ENET_TCLK ((ushort)0x0200) 651#define PA_ENET_RCLK ((ushort)0x0800) 652#define PB_ENET_TENA ((uint)0x00002000) 653#define PC_ENET_CLSN ((ushort)0x0040) 654#define PC_ENET_RENA ((ushort)0x0080) 655 656#define SICR_ENET_MASK ((uint)0x0000ff00) 657#define SICR_ENET_CLKRT ((uint)0x00003d00) 658 659#define PB_ENET_LOOPBACK ((uint)0x00004000) 660#define PB_ENET_FDPLEX_DIS ((uint)0x00008000) 661 662#endif 663 664/*** FADS823 ********************************************************/ 665 666#if defined(CONFIG_MPC823FADS) && defined(CONFIG_FADS) 667/* This ENET stuff is for the MPC823FADS with ethernet on SCC2. 668 */ 669#ifdef CONFIG_SCC2_ENET 670#define PROFF_ENET PROFF_SCC2 671#define CPM_CR_ENET CPM_CR_CH_SCC2 672#define SCC_ENET 1 673#define CPMVEC_ENET CPMVEC_SCC2 674#endif 675 676#ifdef CONFIG_SCC1_ENET 677#define PROFF_ENET PROFF_SCC1 678#define CPM_CR_ENET CPM_CR_CH_SCC1 679#define SCC_ENET 0 680#define CPMVEC_ENET CPMVEC_SCC1 681#endif 682 683#define PA_ENET_RXD ((ushort)0x0004) 684#define PA_ENET_TXD ((ushort)0x0008) 685#define PA_ENET_TCLK ((ushort)0x0400) 686#define PA_ENET_RCLK ((ushort)0x0200) 687 688#define PB_ENET_TENA ((uint)0x00002000) 689 690#define PC_ENET_CLSN ((ushort)0x0040) 691#define PC_ENET_RENA ((ushort)0x0080) 692 693#define SICR_ENET_MASK ((uint)0x0000ff00) 694#define SICR_ENET_CLKRT ((uint)0x00002e00) 695 696#endif /* CONFIG_FADS823FADS */ 697 698/*** FADS850SAR ********************************************************/ 699 700#if defined(CONFIG_MPC850SAR) && defined(CONFIG_FADS) 701/* This ENET stuff is for the MPC850SAR with ethernet on SCC2. Some of 702 * this may be unique to the FADS850SAR configuration. 703 * Note TENA is on Port B. 704 */ 705#define PROFF_ENET PROFF_SCC2 706#define CPM_CR_ENET CPM_CR_CH_SCC2 707#define SCC_ENET 1 708#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 709#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 710#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ 711#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ 712#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ 713#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 714#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 715 716#define SICR_ENET_MASK ((uint)0x0000ff00) 717#define SICR_ENET_CLKRT ((uint)0x00002f00) /* RCLK-CLK2, TCLK-CLK4 */ 718#endif /* CONFIG_FADS850SAR */ 719 720/*** FADS860T********************************************************/ 721 722#if defined(CONFIG_FADS) && defined(CONFIG_MPC86x) 723/* 724 * This ENET stuff is for the MPC86xFADS/MPC8xxADS with ethernet on SCC1. 725 */ 726#ifdef CONFIG_SCC1_ENET 727 728#define SCC_ENET 0 729 730#define PROFF_ENET PROFF_SCC1 731#define CPM_CR_ENET CPM_CR_CH_SCC1 732 733#define PA_ENET_RXD ((ushort)0x0001) 734#define PA_ENET_TXD ((ushort)0x0002) 735#define PA_ENET_TCLK ((ushort)0x0100) 736#define PA_ENET_RCLK ((ushort)0x0200) 737 738#define PB_ENET_TENA ((uint)0x00001000) 739 740#define PC_ENET_CLSN ((ushort)0x0010) 741#define PC_ENET_RENA ((ushort)0x0020) 742 743#define SICR_ENET_MASK ((uint)0x000000ff) 744#define SICR_ENET_CLKRT ((uint)0x0000002c) 745 746#endif /* CONFIG_SCC1_ETHERNET */ 747 748/* 749 * This ENET stuff is for the MPC860TFADS/MPC86xADS/MPC885ADS 750 * with ethernet on FEC. 751 */ 752 753#ifdef CONFIG_FEC_ENET 754#define FEC_ENET /* Use FEC for Ethernet */ 755#endif /* CONFIG_FEC_ENET */ 756 757#endif /* CONFIG_FADS && CONFIG_MPC86x */ 758 759/*** FPS850L, FPS860L ************************************************/ 760 761#if defined(CONFIG_FPS850L) || defined(CONFIG_FPS860L) 762/* Bits in parallel I/O port registers that have to be set/cleared 763 * to configure the pins for SCC2 use. 764 */ 765#define PROFF_ENET PROFF_SCC2 766#define CPM_CR_ENET CPM_CR_CH_SCC2 767#define SCC_ENET 1 768#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 769#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 770#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ 771#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ 772 773#define PC_ENET_TENA ((ushort)0x0002) /* PC 14 */ 774#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 775#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 776 777/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to 778 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. 779 */ 780#define SICR_ENET_MASK ((uint)0x0000ff00) 781#define SICR_ENET_CLKRT ((uint)0x00002600) 782#endif /* CONFIG_FPS850L, CONFIG_FPS860L */ 783 784/*** GEN860T **********************************************************/ 785#if defined(CONFIG_GEN860T) 786#undef SCC_ENET 787#define FEC_ENET 788 789#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ 790#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ 791#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ 792#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ 793#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ 794#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ 795#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ 796#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ 797#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ 798#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ 799#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ 800#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ 801#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ 802#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3-15 */ 803#endif /* CONFIG_GEN860T */ 804 805/*** GENIETV ********************************************************/ 806 807#if defined(CONFIG_GENIETV) 808/* Ethernet is only on SCC2 */ 809 810#define CONFIG_SCC2_ENET 811#define PROFF_ENET PROFF_SCC2 812#define CPM_CR_ENET CPM_CR_CH_SCC2 813#define SCC_ENET 1 814#define CPMVEC_ENET CPMVEC_SCC2 815 816#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 817#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 818#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ 819#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ 820 821#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ 822 823#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 824#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 825 826#define SICR_ENET_MASK ((uint)0x0000ff00) 827#define SICR_ENET_CLKRT ((uint)0x00002e00) 828 829#endif /* CONFIG_GENIETV */ 830 831/*** HERMES-PRO ******************************************************/ 832 833/* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */ 834 835#ifdef CONFIG_HERMES 836 837#define FEC_ENET /* use FEC for EThernet */ 838#undef SCC_ENET 839 840 841#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ 842#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ 843#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ 844#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ 845#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ 846#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ 847#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ 848#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ 849#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ 850#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ 851#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ 852#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ 853#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ 854 855#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ 856 857#endif /* CONFIG_HERMES */ 858 859/*** IAD210 **********************************************************/ 860 861/* The IAD210 uses the FEC on a MPC860P for Ethernet */ 862 863#if defined(CONFIG_IAD210) 864 865# define FEC_ENET /* use FEC for Ethernet */ 866# undef SCC_ENET 867 868# define PD_MII_TXD1 ((ushort) 0x1000 ) /* PD 3 */ 869# define PD_MII_TXD2 ((ushort) 0x0800 ) /* PD 4 */ 870# define PD_MII_TXD3 ((ushort) 0x0400 ) /* PD 5 */ 871# define PD_MII_RX_DV ((ushort) 0x0200 ) /* PD 6 */ 872# define PD_MII_RX_ERR ((ushort) 0x0100 ) /* PD 7 */ 873# define PD_MII_RX_CLK ((ushort) 0x0080 ) /* PD 8 */ 874# define PD_MII_TXD0 ((ushort) 0x0040 ) /* PD 9 */ 875# define PD_MII_RXD0 ((ushort) 0x0020 ) /* PD 10 */ 876# define PD_MII_TX_ERR ((ushort) 0x0010 ) /* PD 11 */ 877# define PD_MII_MDC ((ushort) 0x0008 ) /* PD 12 */ 878# define PD_MII_RXD1 ((ushort) 0x0004 ) /* PD 13 */ 879# define PD_MII_RXD2 ((ushort) 0x0002 ) /* PD 14 */ 880# define PD_MII_RXD3 ((ushort) 0x0001 ) /* PD 15 */ 881 882# define PD_MII_MASK ((ushort) 0x1FFF ) /* PD 3...15 */ 883 884#endif /* CONFIG_IAD210 */ 885 886/*** ICU862 **********************************************************/ 887 888#if defined(CONFIG_ICU862) 889 890#ifdef CONFIG_FEC_ENET 891#define FEC_ENET /* use FEC for EThernet */ 892#endif /* CONFIG_FEC_ETHERNET */ 893 894#endif /* CONFIG_ICU862 */ 895 896/*** IP860 **********************************************************/ 897 898#if defined(CONFIG_IP860) 899/* Bits in parallel I/O port registers that have to be set/cleared 900 * to configure the pins for SCC1 use. 901 */ 902#define PROFF_ENET PROFF_SCC1 903#define CPM_CR_ENET CPM_CR_CH_SCC1 904#define SCC_ENET 0 905#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ 906#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ 907#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ 908#define PA_ENET_TCLK ((ushort)0x0100) /* PA 7 */ 909 910#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ 911#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ 912#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ 913 914#define PB_ENET_RESET (uint)0x00000008 /* PB 28 */ 915#define PB_ENET_JABD (uint)0x00000004 /* PB 29 */ 916 917/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to 918 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. 919 */ 920#define SICR_ENET_MASK ((uint)0x000000ff) 921#define SICR_ENET_CLKRT ((uint)0x0000002C) 922#endif /* CONFIG_IP860 */ 923 924/*** IVMS8 **********************************************************/ 925 926/* The IVMS8 uses the FEC on a MPC860T for Ethernet */ 927 928#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) 929 930#define FEC_ENET /* use FEC for EThernet */ 931#undef SCC_ENET 932 933#define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */ 934 935#define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */ 936 937#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ 938#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ 939#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ 940#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ 941#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ 942#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ 943#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ 944#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ 945#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ 946#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ 947#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ 948#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ 949#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ 950 951#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ 952 953#endif /* CONFIG_IVMS8, CONFIG_IVML24 */ 954 955/*** KUP4K, KUP4X ****************************************************/ 956/* The KUP4 boards uses the FEC on a MPC8xx for Ethernet */ 957 958#if defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) 959 960#define FEC_ENET /* use FEC for EThernet */ 961#undef SCC_ENET 962 963#define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */ 964 965#define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */ 966 967#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ 968#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ 969#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ 970#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ 971#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ 972#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ 973#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ 974#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ 975#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ 976#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ 977#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ 978#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ 979#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ 980 981#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ 982 983#endif /* CONFIG_KUP4K */ 984 985 986/*** LANTEC *********************************************************/ 987 988#if defined(CONFIG_LANTEC) && CONFIG_LANTEC >= 2 989/* Bits in parallel I/O port registers that have to be set/cleared 990 * to configure the pins for SCC2 use. 991 */ 992#define PROFF_ENET PROFF_SCC2 993#define CPM_CR_ENET CPM_CR_CH_SCC2 994#define SCC_ENET 1 995#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 996#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 997#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ 998#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ 999 1000#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
1001 1002#define PC_ENET_LBK ((ushort)0x0010) /* PC 11 */ 1003#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 1004#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 1005 1006/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to 1007 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. 1008 */ 1009#define SICR_ENET_MASK ((uint)0x0000FF00) 1010#define SICR_ENET_CLKRT ((uint)0x00002E00) 1011#endif /* CONFIG_LANTEC v2 */ 1012 1013/*** LWMON **********************************************************/ 1014 1015#if defined(CONFIG_LWMON) 1016/* Bits in parallel I/O port registers that have to be set/cleared 1017 * to configure the pins for SCC2 use. 1018 */ 1019#define PROFF_ENET PROFF_SCC2 1020#define CPM_CR_ENET CPM_CR_CH_SCC2 1021#define SCC_ENET 1 1022#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 1023#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 1024#define PA_ENET_RCLK ((ushort)0x0800) /* PA 4 */ 1025#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ 1026 1027#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ 1028 1029#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 1030#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 1031 1032/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK4) to 1033 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. 1034 */ 1035#define SICR_ENET_MASK ((uint)0x0000ff00) 1036#define SICR_ENET_CLKRT ((uint)0x00003E00) 1037#endif /* CONFIG_LWMON */ 1038 1039/*** NX823 ***********************************************/ 1040 1041#if defined(CONFIG_NX823) 1042/* Bits in parallel I/O port registers that have to be set/cleared 1043 * to configure the pins for SCC1 use. 1044 */ 1045#define PROFF_ENET PROFF_SCC2 1046#define CPM_CR_ENET CPM_CR_CH_SCC2 1047#define SCC_ENET 1 1048#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 1049#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 1050#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ 1051#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ 1052 1053#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ 1054 1055#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 1056#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 1057 1058/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to 1059 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. 1060 */ 1061#define SICR_ENET_MASK ((uint)0x0000ff00) 1062#define SICR_ENET_CLKRT ((uint)0x00002f00) 1063 1064#endif /* CONFIG_NX823 */ 1065 1066/*** MBX ************************************************************/ 1067 1068#ifdef CONFIG_MBX 1069/* Bits in parallel I/O port registers that have to be set/cleared 1070 * to configure the pins for SCC1 use. The TCLK and RCLK seem unique 1071 * to the MBX860 board. Any two of the four available clocks could be 1072 * used, and the MPC860 cookbook manual has an example using different 1073 * clock pins. 1074 */ 1075#define PROFF_ENET PROFF_SCC1 1076#define CPM_CR_ENET CPM_CR_CH_SCC1 1077#define SCC_ENET 0 1078#define PA_ENET_RXD ((ushort)0x0001) 1079#define PA_ENET_TXD ((ushort)0x0002) 1080#define PA_ENET_TCLK ((ushort)0x0200) 1081#define PA_ENET_RCLK ((ushort)0x0800) 1082#define PC_ENET_TENA ((ushort)0x0001) 1083#define PC_ENET_CLSN ((ushort)0x0010) 1084#define PC_ENET_RENA ((ushort)0x0020) 1085 1086/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to 1087 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. 1088 */ 1089#define SICR_ENET_MASK ((uint)0x000000ff) 1090#define SICR_ENET_CLKRT ((uint)0x0000003d) 1091#endif /* CONFIG_MBX */ 1092 1093/*** KM8XX *********************************************************/ 1094 1095/* The KM8XX Service Module uses SCC3 for Ethernet */ 1096 1097#ifdef CONFIG_KM8XX 1098#define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */ 1099#define CPM_CR_ENET CPM_CR_CH_SCC3 1100#define SCC_ENET 2 1101#define PA_ENET_RXD ((ushort)0x0010) /* PA 11 */ 1102#define PA_ENET_TXD ((ushort)0x0020) /* PA 10 */ 1103#define PA_ENET_RCLK ((ushort)0x1000) /* PA 3 CLK 5 */ 1104#define PA_ENET_TCLK ((ushort)0x2000) /* PA 2 CLK 6 */ 1105 1106#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */ 1107 1108#define PC_ENET_RENA ((ushort)0x0200) /* PC 6 */ 1109#define PC_ENET_CLSN ((ushort)0x0100) /* PC 7 */ 1110 1111/* Control bits in the SICR to route TCLK (CLK6) and RCLK (CLK5) to 1112 * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero. 1113 */ 1114#define SICR_ENET_MASK ((uint)0x00FF0000) 1115#define SICR_ENET_CLKRT ((uint)0x00250000) 1116#endif /* CONFIG_KM8XX */ 1117 1118 1119/*** MHPC ********************************************************/ 1120 1121#if defined(CONFIG_MHPC) 1122/* This ENET stuff is for the MHPC with ethernet on SCC2. 1123 * Note TENA is on Port B. 1124 */ 1125#define PROFF_ENET PROFF_SCC2 1126#define CPM_CR_ENET CPM_CR_CH_SCC2 1127#define SCC_ENET 1 1128#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 1129#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 1130#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ 1131#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ 1132#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ 1133#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 1134#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 1135 1136#define SICR_ENET_MASK ((uint)0x0000ff00) 1137#define SICR_ENET_CLKRT ((uint)0x00002e00) /* RCLK-CLK2, TCLK-CLK3 */ 1138#endif /* CONFIG_MHPC */ 1139 1140/*** NETVIA *******************************************************/ 1141 1142/* SinoVee Microsystems SC8xx series FEL8xx-AT,SC823,SC850,SC855T,SC860T */ 1143#if ( defined CONFIG_SVM_SC8xx ) 1144# ifndef CONFIG_FEC_ENET 1145 1146#define PROFF_ENET PROFF_SCC2 1147#define CPM_CR_ENET CPM_CR_CH_SCC2 1148#define SCC_ENET 1 1149 1150 /* Bits in parallel I/O port registers that have to be set/cleared 1151 * * * * to configure the pins for SCC2 use. 1152 * * * */ 1153#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 1154#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 1155#define PA_ENET_RCLK ((ushort)0x0400) /* PA 5 */ 1156#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ 1157 1158#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ 1159 1160#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 1161#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 1162/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to 1163 * * * * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. 1164 * * * */ 1165#define SICR_ENET_MASK ((uint)0x0000ff00) 1166#define SICR_ENET_CLKRT ((uint)0x00003700) 1167 1168# else /* Use FEC for Fast Ethernet */ 1169 1170#undef SCC_ENET 1171#define FEC_ENET 1172 1173#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ 1174#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ 1175#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ 1176#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ 1177#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ 1178#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ 1179#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ 1180#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ 1181#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ 1182#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ 1183#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ 1184#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ 1185#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ 1186 1187#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ 1188 1189# endif /* CONFIG_FEC_ENET */ 1190#endif /* CONFIG_SVM_SC8xx */ 1191 1192 1193#if defined(CONFIG_NETVIA) 1194/* Bits in parallel I/O port registers that have to be set/cleared 1195 * to configure the pins for SCC2 use. 1196 */ 1197#define PROFF_ENET PROFF_SCC2 1198#define CPM_CR_ENET CPM_CR_CH_SCC2 1199#define SCC_ENET 1 1200#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 1201#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 1202#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ 1203#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ 1204 1205#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1 1206# define PB_ENET_PDN ((ushort)0x4000) /* PB 17 */ 1207#elif CONFIG_NETVIA_VERSION >= 2 1208# define PC_ENET_PDN ((ushort)0x0008) /* PC 12 */ 1209#endif 1210 1211#define PB_ENET_TENA ((ushort)0x2000) /* PB 18 */ 1212 1213#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 1214#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 1215 1216/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to 1217 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. 1218 */ 1219#define SICR_ENET_MASK ((uint)0x0000ff00) 1220#define SICR_ENET_CLKRT ((uint)0x00002f00) 1221 1222#endif /* CONFIG_NETVIA */ 1223 1224/*** QS850/QS823 ***************************************************/ 1225 1226#if defined(CONFIG_QS850) || defined(CONFIG_QS823) 1227#undef FEC_ENET /* Don't use FEC for EThernet */ 1228 1229#define PROFF_ENET PROFF_SCC2 1230#define CPM_CR_ENET CPM_CR_CH_SCC2 1231#define SCC_ENET 1 1232 1233#define PA_ENET_RXD ((ushort)0x0004) /* RXD on PA13 (Pin D9) */ 1234#define PA_ENET_TXD ((ushort)0x0008) /* TXD on PA12 (Pin D7) */ 1235#define PC_ENET_RENA ((ushort)0x0080) /* RENA on PC8 (Pin D12) */ 1236#define PC_ENET_CLSN ((ushort)0x0040) /* CLSN on PC9 (Pin C12) */ 1237#define PA_ENET_TCLK ((ushort)0x0200) /* TCLK on PA6 (Pin D8) */ 1238#define PA_ENET_RCLK ((ushort)0x0800) /* RCLK on PA4 (Pin D10) */ 1239#define PB_ENET_TENA ((uint)0x00002000) /* TENA on PB18 (Pin D11) */ 1240#define PC_ENET_LBK ((ushort)0x0010) /* Loopback control on PC11 (Pin B14) */ 1241#define PC_ENET_LI ((ushort)0x0020) /* Link Integrity control PC10 (A15) */ 1242#define PC_ENET_SQE ((ushort)0x0100) /* SQE Disable control PC7 (B15) */ 1243 1244/* SCC2 TXCLK from CLK2 1245 * SCC2 RXCLK from CLK4 1246 * SCC2 Connected to NMSI */ 1247#define SICR_ENET_MASK ((uint)0x00007F00) 1248#define SICR_ENET_CLKRT ((uint)0x00003D00) 1249 1250#endif /* CONFIG_QS850/QS823 */ 1251 1252/*** QS860T ***************************************************/ 1253 1254#ifdef CONFIG_QS860T 1255#ifdef CONFIG_FEC_ENET 1256#define FEC_ENET /* use FEC for EThernet */ 1257#endif /* CONFIG_FEC_ETHERNET */ 1258 1259/* This ENET stuff is for GTH 10 Mbit ( SCC ) */ 1260#define PROFF_ENET PROFF_SCC1 1261#define CPM_CR_ENET CPM_CR_CH_SCC1 1262#define SCC_ENET 0 1263 1264#define PA_ENET_RXD ((ushort)0x0001) /* PA15 */ 1265#define PA_ENET_TXD ((ushort)0x0002) /* PA14 */ 1266#define PA_ENET_TCLK ((ushort)0x0800) /* PA4 */ 1267#define PA_ENET_RCLK ((ushort)0x0200) /* PA6 */ 1268#define PB_ENET_TENA ((uint)0x00001000) /* PB19 */ 1269#define PC_ENET_CLSN ((ushort)0x0010) /* PC11 */ 1270#define PC_ENET_RENA ((ushort)0x0020) /* PC10 */ 1271 1272#define SICR_ENET_MASK ((uint)0x000000ff) 1273/* RCLK PA4 -->CLK4, TCLK PA6 -->CLK2 */ 1274#define SICR_ENET_CLKRT ((uint)0x0000003D) 1275 1276#endif /* CONFIG_QS860T */ 1277 1278/*** RPXCLASSIC *****************************************************/ 1279 1280#ifdef CONFIG_RPXCLASSIC 1281 1282#ifdef CONFIG_FEC_ENET 1283 1284# define FEC_ENET /* use FEC for EThernet */ 1285# undef SCC_ENET 1286 1287#else /* ! CONFIG_FEC_ENET */ 1288 1289/* Bits in parallel I/O port registers that have to be set/cleared 1290 * to configure the pins for SCC1 use. 1291 */ 1292#define PROFF_ENET PROFF_SCC1 1293#define CPM_CR_ENET CPM_CR_CH_SCC1 1294#define SCC_ENET 0 1295#define PA_ENET_RXD ((ushort)0x0001) 1296#define PA_ENET_TXD ((ushort)0x0002) 1297#define PA_ENET_TCLK ((ushort)0x0200) 1298#define PA_ENET_RCLK ((ushort)0x0800) 1299#define PB_ENET_TENA ((uint)0x00001000) 1300#define PC_ENET_CLSN ((ushort)0x0010) 1301#define PC_ENET_RENA ((ushort)0x0020) 1302 1303/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to 1304 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. 1305 */ 1306#define SICR_ENET_MASK ((uint)0x000000ff) 1307#define SICR_ENET_CLKRT ((uint)0x0000003d) 1308 1309#endif /* CONFIG_FEC_ENET */ 1310 1311#endif /* CONFIG_RPXCLASSIC */ 1312 1313/*** RPXLITE ********************************************************/ 1314 1315#ifdef CONFIG_RPXLITE 1316/* This ENET stuff is for the MPC850 with ethernet on SCC2. Some of 1317 * this may be unique to the RPX-Lite configuration. 1318 * Note TENA is on Port B. 1319 */ 1320#define PROFF_ENET PROFF_SCC2 1321#define CPM_CR_ENET CPM_CR_CH_SCC2 1322#define SCC_ENET 1 1323#define PA_ENET_RXD ((ushort)0x0004) 1324#define PA_ENET_TXD ((ushort)0x0008) 1325#define PA_ENET_TCLK ((ushort)0x0200) 1326#define PA_ENET_RCLK ((ushort)0x0800) 1327#if defined(CONFIG_RMU) 1328#define PC_ENET_TENA ((uint)0x00000002) /* PC14 */ 1329#else 1330#define PB_ENET_TENA ((uint)0x00002000) 1331#endif 1332#define PC_ENET_CLSN ((ushort)0x0040) 1333#define PC_ENET_RENA ((ushort)0x0080) 1334 1335#define SICR_ENET_MASK ((uint)0x0000ff00) 1336#define SICR_ENET_CLKRT ((uint)0x00003d00) 1337#endif /* CONFIG_RPXLITE */ 1338 1339/*** SM850 *********************************************************/ 1340 1341/* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */ 1342 1343#ifdef CONFIG_SM850 1344#define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */ 1345#define CPM_CR_ENET CPM_CR_CH_SCC3 1346#define SCC_ENET 2 1347#define PB_ENET_RXD ((uint)0x00000004) /* PB 29 */ 1348#define PB_ENET_TXD ((uint)0x00000002) /* PB 30 */ 1349#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ 1350#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ 1351 1352#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */ 1353#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */ 1354 1355#define PC_ENET_RENA ((ushort)0x0800) /* PC 4 */ 1356#define PC_ENET_CLSN ((ushort)0x0400) /* PC 5 */ 1357 1358/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to 1359 * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero. 1360 */ 1361#define SICR_ENET_MASK ((uint)0x00FF0000) 1362#define SICR_ENET_CLKRT ((uint)0x00260000) 1363#endif /* CONFIG_SM850 */ 1364 1365/*** SPD823TS ******************************************************/ 1366 1367#ifdef CONFIG_SPD823TS 1368/* Bits in parallel I/O port registers that have to be set/cleared 1369 * to configure the pins for SCC2 use. 1370 */ 1371#define PROFF_ENET PROFF_SCC2 /* Ethernet on SCC2 */ 1372#define CPM_CR_ENET CPM_CR_CH_SCC2 1373#define SCC_ENET 1 1374#define PA_ENET_MDC ((ushort)0x0001) /* PA 15 !!! */ 1375#define PA_ENET_MDIO ((ushort)0x0002) /* PA 14 !!! */ 1376#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 1377#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 1378#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ 1379#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ 1380 1381#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ 1382 1383#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 1384#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 1385#define PC_ENET_RESET ((ushort)0x0100) /* PC 7 !!! */ 1386 1387/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to 1388 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. 1389 */ 1390#define SICR_ENET_MASK ((uint)0x0000ff00) 1391#define SICR_ENET_CLKRT ((uint)0x00002E00) 1392#endif /* CONFIG_SPD823TS */ 1393 1394/*** SXNI855T ******************************************************/ 1395 1396#if defined(CONFIG_SXNI855T) 1397 1398#ifdef CONFIG_FEC_ENET 1399#define FEC_ENET /* use FEC for Ethernet */ 1400#endif /* CONFIG_FEC_ETHERNET */ 1401 1402#endif /* CONFIG_SXNI855T */ 1403 1404/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, ETX094, R360MPI **********/ 1405 1406#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \ 1407 defined(CONFIG_R360MPI) || defined(CONFIG_RBC823) || \ 1408 defined(CONFIG_TQM823L) || defined(CONFIG_TQM823M) || \ 1409 defined(CONFIG_TQM850L) || defined(CONFIG_TQM850M) || \ 1410 defined(CONFIG_TQM885D) || defined(CONFIG_ETX094) || \ 1411 defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2)|| \ 1412 (defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2) 1413 1414/* Bits in parallel I/O port registers that have to be set/cleared 1415 * to configure the pins for SCC2 use. 1416 */ 1417#define PROFF_ENET PROFF_SCC2 1418#define CPM_CR_ENET CPM_CR_CH_SCC2 1419#if (!defined(CONFIG_TK885D)) /* TK885D does not use SCC Ethernet */ 1420#define SCC_ENET 1 1421#endif 1422#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ 1423#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ 1424#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ 1425#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ 1426 1427#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ 1428 1429#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ 1430#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ 1431#if defined(CONFIG_R360MPI) 1432#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */ 1433#endif /* CONFIG_R360MPI */ 1434 1435/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to 1436 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. 1437 */ 1438#define SICR_ENET_MASK ((uint)0x0000ff00) 1439#define SICR_ENET_CLKRT ((uint)0x00002600) 1440 1441# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */ 1442#define FEC_ENET 1443# endif /* CONFIG_FEC_ENET */ 1444 1445#endif /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */ 1446 1447/*** TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M *********************/ 1448 1449#if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \ 1450 defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \ 1451 defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M) || \ 1452 defined(CONFIG_TQM866L) || defined(CONFIG_TQM866M) 1453 1454# ifdef CONFIG_SCC1_ENET /* use SCC for 10Mbps Ethernet */ 1455 1456/* Bits in parallel I/O port registers that have to be set/cleared 1457 * to configure the pins for SCC1 use. 1458 */ 1459#define PROFF_ENET PROFF_SCC1 1460#define CPM_CR_ENET CPM_CR_CH_SCC1 1461#define SCC_ENET 0 1462#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ 1463#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ 1464#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ 1465#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ 1466 1467#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ 1468#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ 1469#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ 1470 1471/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to 1472 * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. 1473 */ 1474#define SICR_ENET_MASK ((uint)0x000000ff) 1475#define SICR_ENET_CLKRT ((uint)0x00000026) 1476 1477# endif /* CONFIG_SCC1_ENET */ 1478 1479# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */ 1480 1481#define FEC_ENET 1482 1483#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ 1484#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ 1485#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ 1486#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ 1487#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ 1488#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ 1489#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ 1490#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ 1491#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ 1492#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ 1493#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ 1494#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ 1495#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ 1496 1497#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ 1498 1499# endif /* CONFIG_FEC_ENET */ 1500#endif /* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */ 1501 1502/*** V37 **********************************************************/ 1503 1504#ifdef CONFIG_V37 1505/* This ENET stuff is for the MPC823 with ethernet on SCC2. Some of 1506 * this may be unique to the Marel V37 configuration. 1507 * Note TENA is on Port B. 1508 */ 1509#define PROFF_ENET PROFF_SCC2 1510#define CPM_CR_ENET CPM_CR_CH_SCC2 1511#define SCC_ENET 1 1512#define PA_ENET_RXD ((ushort)0x0004) 1513#define PA_ENET_TXD ((ushort)0x0008) 1514#define PA_ENET_TCLK ((ushort)0x0400) 1515#define PA_ENET_RCLK ((ushort)0x0200) 1516#define PB_ENET_TENA ((uint)0x00002000) 1517#define PC_ENET_CLSN ((ushort)0x0040) 1518#define PC_ENET_RENA ((ushort)0x0080) 1519 1520#define SICR_ENET_MASK ((uint)0x0000ff00) 1521#define SICR_ENET_CLKRT ((uint)0x00002e00) 1522#endif /* CONFIG_V37 */ 1523 1524 1525/*********************************************************************/ 1526 1527/* SCC Event register as used by Ethernet. 1528*/ 1529#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ 1530#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ 1531#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ 1532#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ 1533#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ 1534#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ 1535 1536/* SCC Mode Register (PSMR) as used by Ethernet. 1537*/ 1538#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */ 1539#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */ 1540#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */ 1541#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */ 1542#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ 1543#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */ 1544#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ 1545#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */ 1546#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */ 1547#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */ 1548#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */ 1549#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */ 1550#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */ 1551 1552/* Buffer descriptor control/status used by Ethernet receive. 1553*/ 1554#define BD_ENET_RX_EMPTY ((ushort)0x8000) 1555#define BD_ENET_RX_WRAP ((ushort)0x2000) 1556#define BD_ENET_RX_INTR ((ushort)0x1000) 1557#define BD_ENET_RX_LAST ((ushort)0x0800) 1558#define BD_ENET_RX_FIRST ((ushort)0x0400) 1559#define BD_ENET_RX_MISS ((ushort)0x0100) 1560#define BD_ENET_RX_LG ((ushort)0x0020) 1561#define BD_ENET_RX_NO ((ushort)0x0010) 1562#define BD_ENET_RX_SH ((ushort)0x0008) 1563#define BD_ENET_RX_CR ((ushort)0x0004) 1564#define BD_ENET_RX_OV ((ushort)0x0002) 1565#define BD_ENET_RX_CL ((ushort)0x0001) 1566#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ 1567 1568/* Buffer descriptor control/status used by Ethernet transmit. 1569*/ 1570#define BD_ENET_TX_READY ((ushort)0x8000) 1571#define BD_ENET_TX_PAD ((ushort)0x4000) 1572#define BD_ENET_TX_WRAP ((ushort)0x2000) 1573#define BD_ENET_TX_INTR ((ushort)0x1000) 1574#define BD_ENET_TX_LAST ((ushort)0x0800) 1575#define BD_ENET_TX_TC ((ushort)0x0400) 1576#define BD_ENET_TX_DEF ((ushort)0x0200) 1577#define BD_ENET_TX_HB ((ushort)0x0100) 1578#define BD_ENET_TX_LC ((ushort)0x0080) 1579#define BD_ENET_TX_RL ((ushort)0x0040) 1580#define BD_ENET_TX_RCMASK ((ushort)0x003c) 1581#define BD_ENET_TX_UN ((ushort)0x0002) 1582#define BD_ENET_TX_CSL ((ushort)0x0001) 1583#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ 1584 1585/* SCC as UART 1586*/ 1587typedef struct scc_uart { 1588 sccp_t scc_genscc; 1589 uint scc_res1; /* Reserved */ 1590 uint scc_res2; /* Reserved */ 1591 ushort scc_maxidl; /* Maximum idle chars */ 1592 ushort scc_idlc; /* temp idle counter */ 1593 ushort scc_brkcr; /* Break count register */ 1594 ushort scc_parec; /* receive parity error counter */ 1595 ushort scc_frmec; /* receive framing error counter */ 1596 ushort scc_nosec; /* receive noise counter */ 1597 ushort scc_brkec; /* receive break condition counter */ 1598 ushort scc_brkln; /* last received break length */ 1599 ushort scc_uaddr1; /* UART address character 1 */ 1600 ushort scc_uaddr2; /* UART address character 2 */ 1601 ushort scc_rtemp; /* Temp storage */ 1602 ushort scc_toseq; /* Transmit out of sequence char */ 1603 ushort scc_char1; /* control character 1 */ 1604 ushort scc_char2; /* control character 2 */ 1605 ushort scc_char3; /* control character 3 */ 1606 ushort scc_char4; /* control character 4 */ 1607 ushort scc_char5; /* control character 5 */ 1608 ushort scc_char6; /* control character 6 */ 1609 ushort scc_char7; /* control character 7 */ 1610 ushort scc_char8; /* control character 8 */ 1611 ushort scc_rccm; /* receive control character mask */ 1612 ushort scc_rccr; /* receive control character register */ 1613 ushort scc_rlbc; /* receive last break character */ 1614} scc_uart_t; 1615 1616/* SCC Event and Mask registers when it is used as a UART. 1617*/ 1618#define UART_SCCM_GLR ((ushort)0x1000) 1619#define UART_SCCM_GLT ((ushort)0x0800) 1620#define UART_SCCM_AB ((ushort)0x0200) 1621#define UART_SCCM_IDL ((ushort)0x0100) 1622#define UART_SCCM_GRA ((ushort)0x0080) 1623#define UART_SCCM_BRKE ((ushort)0x0040) 1624#define UART_SCCM_BRKS ((ushort)0x0020) 1625#define UART_SCCM_CCR ((ushort)0x0008) 1626#define UART_SCCM_BSY ((ushort)0x0004) 1627#define UART_SCCM_TX ((ushort)0x0002) 1628#define UART_SCCM_RX ((ushort)0x0001) 1629 1630/* The SCC PSMR when used as a UART. 1631*/ 1632#define SCU_PSMR_FLC ((ushort)0x8000) 1633#define SCU_PSMR_SL ((ushort)0x4000) 1634#define SCU_PSMR_CL ((ushort)0x3000) 1635#define SCU_PSMR_UM ((ushort)0x0c00) 1636#define SCU_PSMR_FRZ ((ushort)0x0200) 1637#define SCU_PSMR_RZS ((ushort)0x0100) 1638#define SCU_PSMR_SYN ((ushort)0x0080) 1639#define SCU_PSMR_DRT ((ushort)0x0040) 1640#define SCU_PSMR_PEN ((ushort)0x0010) 1641#define SCU_PSMR_RPM ((ushort)0x000c) 1642#define SCU_PSMR_REVP ((ushort)0x0008) 1643#define SCU_PSMR_TPM ((ushort)0x0003) 1644#define SCU_PSMR_TEVP ((ushort)0x0003) 1645 1646/* CPM Transparent mode SCC. 1647 */ 1648typedef struct scc_trans { 1649 sccp_t st_genscc; 1650 uint st_cpres; /* Preset CRC */ 1651 uint st_cmask; /* Constant mask for CRC */ 1652} scc_trans_t; 1653 1654#define BD_SCC_TX_LAST ((ushort)0x0800) 1655 1656/* IIC parameter RAM. 1657*/ 1658typedef struct iic { 1659 ushort iic_rbase; /* Rx Buffer descriptor base address */ 1660 ushort iic_tbase; /* Tx Buffer descriptor base address */ 1661 u_char iic_rfcr; /* Rx function code */ 1662 u_char iic_tfcr; /* Tx function code */ 1663 ushort iic_mrblr; /* Max receive buffer length */ 1664 uint iic_rstate; /* Internal */ 1665 uint iic_rdp; /* Internal */ 1666 ushort iic_rbptr; /* Internal */ 1667 ushort iic_rbc; /* Internal */ 1668 uint iic_rxtmp; /* Internal */ 1669 uint iic_tstate; /* Internal */ 1670 uint iic_tdp; /* Internal */ 1671 ushort iic_tbptr; /* Internal */ 1672 ushort iic_tbc; /* Internal */ 1673 uint iic_txtmp; /* Internal */ 1674 uint iic_res; /* reserved */ 1675 ushort iic_rpbase; /* Relocation pointer */ 1676 ushort iic_res2; /* reserved */ 1677} iic_t; 1678 1679/* SPI parameter RAM. 1680*/ 1681typedef struct spi { 1682 ushort spi_rbase; /* Rx Buffer descriptor base address */ 1683 ushort spi_tbase; /* Tx Buffer descriptor base address */ 1684 u_char spi_rfcr; /* Rx function code */ 1685 u_char spi_tfcr; /* Tx function code */ 1686 ushort spi_mrblr; /* Max receive buffer length */ 1687 uint spi_rstate; /* Internal */ 1688 uint spi_rdp; /* Internal */ 1689 ushort spi_rbptr; /* Internal */ 1690 ushort spi_rbc; /* Internal */ 1691 uint spi_rxtmp; /* Internal */ 1692 uint spi_tstate; /* Internal */ 1693 uint spi_tdp; /* Internal */ 1694 ushort spi_tbptr; /* Internal */ 1695 ushort spi_tbc; /* Internal */ 1696 uint spi_txtmp; /* Internal */ 1697 uint spi_res; 1698 ushort spi_rpbase; /* Relocation pointer */ 1699 ushort spi_res2; 1700} spi_t; 1701 1702/* SPI Mode register. 1703*/ 1704#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */ 1705#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */ 1706#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */ 1707#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */ 1708#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */ 1709#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */ 1710#define SPMODE_EN ((ushort)0x0100) /* Enable */ 1711#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */ 1712#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */ 1713 1714#define SPMODE_LEN(x) ((((x)-1)&0xF)<<4) 1715#define SPMODE_PM(x) ((x) &0xF) 1716 1717/* HDLC parameter RAM. 1718*/ 1719 1720typedef struct hdlc_pram_s { 1721 /* 1722 * SCC parameter RAM 1723 */ 1724 ushort rbase; /* Rx Buffer descriptor base address */ 1725 ushort tbase; /* Tx Buffer descriptor base address */ 1726 uchar rfcr; /* Rx function code */ 1727 uchar tfcr; /* Tx function code */ 1728 ushort mrblr; /* Rx buffer length */ 1729 ulong rstate; /* Rx internal state */ 1730 ulong rptr; /* Rx internal data pointer */ 1731 ushort rbptr; /* rb BD Pointer */ 1732 ushort rcount; /* Rx internal byte count */ 1733 ulong rtemp; /* Rx temp */ 1734 ulong tstate; /* Tx internal state */ 1735 ulong tptr; /* Tx internal data pointer */ 1736 ushort tbptr; /* Tx BD pointer */ 1737 ushort tcount; /* Tx byte count */ 1738 ulong ttemp; /* Tx temp */ 1739 ulong rcrc; /* temp receive CRC */ 1740 ulong tcrc; /* temp transmit CRC */ 1741 /* 1742 * HDLC specific parameter RAM 1743 */ 1744 uchar res[4]; /* reserved */ 1745 ulong c_mask; /* CRC constant */ 1746 ulong c_pres; /* CRC preset */ 1747 ushort disfc; /* discarded frame counter */ 1748 ushort crcec; /* CRC error counter */ 1749 ushort abtsc; /* abort sequence counter */ 1750 ushort nmarc; /* nonmatching address rx cnt */ 1751 ushort retrc; /* frame retransmission cnt */ 1752 ushort mflr; /* maximum frame length reg */ 1753 ushort max_cnt; /* maximum length counter */ 1754 ushort rfthr; /* received frames threshold */ 1755 ushort rfcnt; /* received frames count */ 1756 ushort hmask; /* user defined frm addr mask */ 1757 ushort haddr1; /* user defined frm address 1 */ 1758 ushort haddr2; /* user defined frm address 2 */ 1759 ushort haddr3; /* user defined frm address 3 */ 1760 ushort haddr4; /* user defined frm address 4 */ 1761 ushort tmp; /* temp */ 1762 ushort tmp_mb; /* temp */ 1763} hdlc_pram_t; 1764 1765/* CPM interrupts. There are nearly 32 interrupts generated by CPM 1766 * channels or devices. All of these are presented to the PPC core 1767 * as a single interrupt. The CPM interrupt handler dispatches its 1768 * own handlers, in a similar fashion to the PPC core handler. We 1769 * use the table as defined in the manuals (i.e. no special high 1770 * priority and SCC1 == SCCa, etc...). 1771 */ 1772#define CPMVEC_NR 32 1773#define CPMVEC_OFFSET 0x00010000 1774#define CPMVEC_PIO_PC15 ((ushort)0x1f | CPMVEC_OFFSET) 1775#define CPMVEC_SCC1 ((ushort)0x1e | CPMVEC_OFFSET) 1776#define CPMVEC_SCC2 ((ushort)0x1d | CPMVEC_OFFSET) 1777#define CPMVEC_SCC3 ((ushort)0x1c | CPMVEC_OFFSET) 1778#define CPMVEC_SCC4 ((ushort)0x1b | CPMVEC_OFFSET) 1779#define CPMVEC_PIO_PC14 ((ushort)0x1a | CPMVEC_OFFSET) 1780#define CPMVEC_TIMER1 ((ushort)0x19 | CPMVEC_OFFSET) 1781#define CPMVEC_PIO_PC13 ((ushort)0x18 | CPMVEC_OFFSET) 1782#define CPMVEC_PIO_PC12 ((ushort)0x17 | CPMVEC_OFFSET) 1783#define CPMVEC_SDMA_CB_ERR ((ushort)0x16 | CPMVEC_OFFSET) 1784#define CPMVEC_IDMA1 ((ushort)0x15 | CPMVEC_OFFSET) 1785#define CPMVEC_IDMA2 ((ushort)0x14 | CPMVEC_OFFSET) 1786#define CPMVEC_TIMER2 ((ushort)0x12 | CPMVEC_OFFSET) 1787#define CPMVEC_RISCTIMER ((ushort)0x11 | CPMVEC_OFFSET) 1788#define CPMVEC_I2C ((ushort)0x10 | CPMVEC_OFFSET) 1789#define CPMVEC_PIO_PC11 ((ushort)0x0f | CPMVEC_OFFSET) 1790#define CPMVEC_PIO_PC10 ((ushort)0x0e | CPMVEC_OFFSET) 1791#define CPMVEC_TIMER3 ((ushort)0x0c | CPMVEC_OFFSET) 1792#define CPMVEC_PIO_PC9 ((ushort)0x0b | CPMVEC_OFFSET) 1793#define CPMVEC_PIO_PC8 ((ushort)0x0a | CPMVEC_OFFSET) 1794#define CPMVEC_PIO_PC7 ((ushort)0x09 | CPMVEC_OFFSET) 1795#define CPMVEC_TIMER4 ((ushort)0x07 | CPMVEC_OFFSET) 1796#define CPMVEC_PIO_PC6 ((ushort)0x06 | CPMVEC_OFFSET) 1797#define CPMVEC_SPI ((ushort)0x05 | CPMVEC_OFFSET) 1798#define CPMVEC_SMC1 ((ushort)0x04 | CPMVEC_OFFSET) 1799#define CPMVEC_SMC2 ((ushort)0x03 | CPMVEC_OFFSET) 1800#define CPMVEC_PIO_PC5 ((ushort)0x02 | CPMVEC_OFFSET) 1801#define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET) 1802#define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET) 1803 1804extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id); 1805 1806/* CPM interrupt configuration vector. 1807*/ 1808#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ 1809#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ 1810#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ 1811#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ 1812#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */ 1813#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ 1814#define CICR_IEN ((uint)0x00000080) /* Int. enable */ 1815#define CICR_SPS ((uint)0x00000001) /* SCC Spread */ 1816#endif /* __CPM_8XX__ */ 1817