LXR uboot/include/configs/G2000.h

   1/*
   2 * (C) Copyright 2004
   3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24/*
  25 * board/config.h - configuration options, board specific
  26 */
  27
  28#ifndef __CONFIG_H
  29#define __CONFIG_H
  30
  31/*
  32 * High Level Configuration Options
  33 * (easy to change)
  34 */
  35
  36#define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  37#define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  38#define CONFIG_G2000            1       /* ...on a PLU405 board         */
  39
  40#define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  41#define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  42
  43#define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
  44
  45#if 0 /* test-only */
  46#define CONFIG_BAUDRATE         115200
  47#else
  48#define CONFIG_BAUDRATE         9600
  49#endif
  50
  51#define CONFIG_PREBOOT
  52
  53#undef  CONFIG_BOOTARGS
  54
  55#define CONFIG_EXTRA_ENV_SETTINGS                                       \
  56        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  57                "nfsroot=${serverip}:${rootpath}\0"                     \
  58        "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  59        "addip=setenv bootargs ${bootargs} "                            \
  60                "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  61                ":${hostname}:${netdev}:off\0"                          \
  62        "addmisc=setenv bootargs ${bootargs} "                          \
  63                "console=ttyS0,${baudrate} "                            \
  64                "panic=1\0"                                             \
  65        "flash_nfs=run nfsargs addip addmisc;"                          \
  66                "bootm ${kernel_addr}\0"                                \
  67        "flash_self=run ramargs addip addmisc;"                         \
  68                "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  69        "net_nfs=tftp 200000 ${bootfile};"                              \
  70                "run nfsargs addip addmisc;bootm\0"                     \
  71        "rootpath=/opt/eldk/ppc_4xx\0"                                  \
  72        "bootfile=/tftpboot/g2000/pImage\0"                             \
  73        "kernel_addr=ff800000\0"                                        \
  74        "ramdisk_addr=ff900000\0"                                       \
  75        "pciconfighost=yes\0"                                           \
  76        ""
  77#define CONFIG_BOOTCOMMAND      "run net_nfs"
  78
  79#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  80
  81#define CONFIG_NET_MULTI        1
  82
  83#define CONFIG_PPC4xx_EMAC
  84#define CONFIG_MII              1       /* MII PHY management           */
  85#define CONFIG_PHY_ADDR         0       /* PHY address                  */
  86#define CONFIG_PHY1_ADDR        1       /* PHY address                  */
  87
  88#if 0 /* test-only */
  89#define CONFIG_PHY_CLK_FREQ     EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
  90#endif
  91
  92
  93/*
  94 * BOOTP options
  95 */
  96#define CONFIG_BOOTP_BOOTFILESIZE
  97#define CONFIG_BOOTP_BOOTPATH
  98#define CONFIG_BOOTP_GATEWAY
  99#define CONFIG_BOOTP_HOSTNAME
 100
 101
 102/*
 103 * Command line configuration.
 104 */
 105#include <config_cmd_default.h>
 106
 107#define CONFIG_CMD_DHCP
 108#define CONFIG_CMD_PCI
 109#define CONFIG_CMD_IRQ
 110#define CONFIG_CMD_ELF
 111#define CONFIG_CMD_DATE
 112#define CONFIG_CMD_I2C
 113#define CONFIG_CMD_MII
 114#define CONFIG_CMD_PING
 115#define CONFIG_CMD_BSP
 116#define CONFIG_CMD_EEPROM
 117
 118
 119#undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 120
 121#if 0 /* test-only */
 122#define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
 123#endif
 124
 125/*
 126 * Miscellaneous configurable options
 127 */
 128#define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 129#define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 130
 131#undef  CONFIG_SYS_HUSH_PARSER                  /* use "hush" command parser    */
 132#ifdef  CONFIG_SYS_HUSH_PARSER
 133#define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 134#endif
 135
 136#if defined(CONFIG_CMD_KGDB)
 137#define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 138#else
 139#define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 140#endif
 141#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 142#define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 143#define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 144
 145#define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
 146
 147#define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
 148
 149#define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
 150
 151#define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 152#define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 153
 154#undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
 155#define CONFIG_SYS_BASE_BAUD        691200
 156#undef  CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
 157
 158/* The following table includes the supported baudrates */
 159#define CONFIG_SYS_BAUDRATE_TABLE       \
 160        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 161         57600, 115200, 230400, 460800, 921600 }
 162
 163#define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 164#define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 165
 166#define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 167
 168#define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 169#define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
 170
 171#define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 172
 173#define CONFIG_SYS_RX_ETH_BUFFER        16      /* use 16 rx buffer on 405 emac */
 174
 175/*----------------------------------------------------------------------------*/
 176/* adding Ethernet setting:  FTS OUI 00:11:0B */
 177/*----------------------------------------------------------------------------*/
 178#define CONFIG_ETHADDR          00:11:0B:00:00:01
 179#define CONFIG_HAS_ETH1
 180#define CONFIG_ETH1ADDR         00:11:0B:00:00:02
 181#define CONFIG_IPADDR           10.48.8.178
 182#define CONFIG_IP1ADDR          10.48.8.188
 183#define CONFIG_NETMASK          255.255.255.128
 184#define CONFIG_SERVERIP         10.48.8.138
 185
 186/*-----------------------------------------------------------------------
 187 * RTC stuff
 188 *-----------------------------------------------------------------------
 189 */
 190#define CONFIG_RTC_DS1337
 191#define CONFIG_SYS_I2C_RTC_ADDR 0x68
 192
 193#if 0 /* test-only */
 194/*-----------------------------------------------------------------------
 195 * NAND-FLASH stuff
 196 *-----------------------------------------------------------------------
 197 */
 198#define CONFIG_SYS_MAX_NAND_DEVICE      1       /* Max number of NAND devices           */
 199
 200#define CONFIG_SYS_NAND_CE  (0x80000000 >> 1)   /* our CE is GPIO1 */
 201#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2)   /* our CLE is GPIO2 */
 202#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3)   /* our ALE is GPIO3 */
 203#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4)   /* our RDY is GPIO4 */
 204
 205#endif
 206
 207/*-----------------------------------------------------------------------
 208 * PCI stuff
 209 *-----------------------------------------------------------------------
 210 */
 211#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 212#define PCI_HOST_FORCE  1               /* configure as pci host        */
 213#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 214
 215#define CONFIG_PCI                      /* include pci support          */
 216#define CONFIG_PCI_HOST PCI_HOST_HOST   /* select pci host function     */
 217#define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 218                                        /* resource configuration       */
 219
 220#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 221
 222#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 223
 224#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 225#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
 226#define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
 227#define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
 228#define CONFIG_SYS_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
 229#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 230#define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
 231#define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
 232#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 233
 234/*
 235 * For booting Linux, the board info and command line data
 236 * have to be in the first 8 MB of memory, since this is
 237 * the maximum mapped by the Linux kernel during initialization.
 238 */
 239#define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 240
 241/*-----------------------------------------------------------------------
 242 * FLASH organization
 243 */
 244#if 0 /* APC405 */
 245#define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant              */
 246#define CONFIG_SYS_MAX_FLASH_SECT       128     /* max number of sectors on one chip    */
 247#define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks           */
 248#undef CONFIG_SYS_FLASH_PROTECTION              /* don't use hardware protection        */
 249#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 250#define CONFIG_SYS_FLASH_BASE           0xFE000000 /* test-only...*/
 251#define CONFIG_SYS_FLASH_INCREMENT      0x01000000 /* test-only */
 252#else /* G2000 */
 253#define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant              */
 254#define CONFIG_SYS_MAX_FLASH_SECT       128     /* max number of sectors on one chip    */
 255#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 256#undef CONFIG_SYS_FLASH_PROTECTION              /* don't use hardware protection        */
 257#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 258#define CONFIG_SYS_FLASH_BASE           0xFF800000 /* test-only...*/
 259#define CONFIG_SYS_FLASH_INCREMENT      0x01000000 /* test-only */
 260#endif
 261
 262#define CONFIG_SYS_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 263
 264#define CONFIG_SYS_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
 265#define CONFIG_SYS_JFFS2_NUM_BANKS     1           /* ! second bank contains u-boot    */
 266
 267/*-----------------------------------------------------------------------
 268 * Start addresses for the final memory configuration
 269 * (Set up by the startup code)
 270 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 271 */
 272#define CONFIG_SYS_SDRAM_BASE           0x00000000
 273#define CONFIG_SYS_MONITOR_BASE 0xFFFC0000
 274#define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Monitor   */
 275#define CONFIG_SYS_MALLOC_LEN           (256 * 1024)    /* Reserve 256 kB for malloc()  */
 276
 277/*-----------------------------------------------------------------------
 278 * Environment Variable setup
 279 */
 280#if 1 /* test-only */
 281#define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 282#define CONFIG_ENV_OFFSET               0x100   /* environment starts at the beginning of the EEPROM */
 283#define CONFIG_ENV_SIZE         0x700   /* 2048 bytes may be used for env vars*/
 284                                   /* total size of a CAT24WC16 is 2048 bytes */
 285
 286#else   /* DEFAULT: environment in flash, using redundand flash sectors */
 287
 288#define CONFIG_ENV_IS_IN_FLASH  1       /* use FLASH for environment vars */
 289#define CONFIG_ENV_ADDR         0xFFFA0000 /* environment starts before u-boot */
 290#define CONFIG_ENV_SECT_SIZE    0x20000 /* 128k bytes may be used for env vars*/
 291
 292#endif
 293
 294/*-----------------------------------------------------------------------
 295 * I2C EEPROM (CAT24WC16) for environment
 296 */
 297#define CONFIG_HARD_I2C                 /* I2c with hardware support */
 298#define CONFIG_PPC4XX_I2C               /* use PPC4xx driver            */
 299#define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 300#define CONFIG_SYS_I2C_SLAVE            0x7F
 301
 302#define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT24WC08             */
 303/* CAT24WC08/16... */
 304#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 305/* mask of address bits that overflow into the "EEPROM chip address"    */
 306#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 307#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has   */
 308                                        /* 16 byte page write mode using*/
 309                                        /* last 4 bits of the address   */
 310#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 311
 312/*-----------------------------------------------------------------------
 313 * External Bus Controller (EBC) Setup
 314 */
 315
 316/* Memory Bank 0 (Intel Strata Flash) initialization                            */
 317#define CONFIG_SYS_EBC_PB0AP   0x92015480
 318#define CONFIG_SYS_EBC_PB0CR   0xFF87A000          /* BAS=0xFF8,BS=08MB,BU=R/W,BW=16bit*/
 319
 320/* Memory Bank 1 ( Power TAU) initialization               */
 321/* #define CONFIG_SYS_EBC_PB1AP           0x04041000 */
 322/* #define CONFIG_SYS_EBC_PB1CR           0xF0018000   */  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 323#define CONFIG_SYS_EBC_PB1AP           0x00000000
 324#define CONFIG_SYS_EBC_PB1CR           0x00000000
 325
 326/* Memory Bank 2 (Intel Flash) initialization                 */
 327#define CONFIG_SYS_EBC_PB2AP           0x00000000
 328#define CONFIG_SYS_EBC_PB2CR           0x00000000
 329
 330/* Memory Bank 3 (NAND) initialization                        */
 331#define CONFIG_SYS_EBC_PB3AP           0x92015480
 332#define CONFIG_SYS_EBC_PB3CR           0xF40B8000  /*addr 0xF40, BS=32M,BU=R/W, BW=8bit */
 333
 334/* Memory Bank 4 (FPGA regs) initialization                                     */
 335#define CONFIG_SYS_EBC_PB4AP           0x00000000
 336#define CONFIG_SYS_EBC_PB4CR           0x00000000  /* leave it blank  */
 337
 338#define CONFIG_SYS_NAND_BASE   0xF4000000
 339
 340/*-----------------------------------------------------------------------
 341 * Definitions for initial stack pointer and data area (in data cache)
 342 */
 343/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 344#define CONFIG_SYS_TEMP_STACK_OCM         1
 345
 346/* On Chip Memory location */
 347#define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 348#define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 349#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 350#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM     */
 351
 352#define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 353#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 354#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 355
 356/*-----------------------------------------------------------------------
 357 * Definitions for GPIO setup (PPC405EP specific)
 358 *
 359 * GPIO0[0]     - External Bus Controller BLAST output
 360 * GPIO0[1-9]   - Instruction trace outputs
 361 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 362 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
 363 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 364 * GPIO0[24-27] - UART0 control signal inputs/outputs
 365 * GPIO0[28-29] - UART1 data signal input/output
 366 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 367 *
 368 * following GPIO setting changed for G20000, 080304
 369 */
 370#define CONFIG_SYS_GPIO0_OSRH          0x40005555
 371#define CONFIG_SYS_GPIO0_OSRL          0x40000110
 372#define CONFIG_SYS_GPIO0_ISR1H         0x00000000
 373#define CONFIG_SYS_GPIO0_ISR1L         0x15555445
 374#define CONFIG_SYS_GPIO0_TSRH          0x00000000
 375#define CONFIG_SYS_GPIO0_TSRL          0x00000000
 376#define CONFIG_SYS_GPIO0_TCR           0xF7FF8014
 377
 378/*
 379 * Internal Definitions
 380 *
 381 * Boot Flags
 382 */
 383#define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 384#define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 385
 386/*
 387 * Default speed selection (cpu_plb_opb_ebc) in mhz.
 388 * This value will be set if iic boot eprom is disabled.
 389 */
 390#if 1
 391#define PLLMR0_DEFAULT   PLLMR0_266_66_33_33
 392#define PLLMR1_DEFAULT   PLLMR1_266_66_33_33
 393#endif
 394#if 0
 395#define PLLMR0_DEFAULT   PLLMR0_266_133_66_33
 396#define PLLMR1_DEFAULT   PLLMR1_266_133_66_33
 397#endif
 398#if 0
 399#define PLLMR0_DEFAULT   PLLMR0_200_100_50_33
 400#define PLLMR1_DEFAULT   PLLMR1_200_100_50_33
 401#endif
 402#if 0
 403#define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
 404#define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
 405#endif
 406
 407#endif  /* __CONFIG_H */
 408