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25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29
30#define CONFIG_BOOKE 1
31#define CONFIG_E500 1
32#define CONFIG_MPC85xx 1
33#define CONFIG_MPC8569 1
34#define CONFIG_MPC8569MDS 1
35
36#define CONFIG_FSL_ELBC 1
37
38#define CONFIG_PCI 1
39#define CONFIG_PCIE1 1
40#define CONFIG_FSL_PCI_INIT 1
41#define CONFIG_FSL_PCIE_RESET 1
42#define CONFIG_SYS_PCI_64BIT 1
43#define CONFIG_QE
44#define CONFIG_ENV_OVERWRITE
45#define CONFIG_FSL_LAW 1
46
47#ifndef __ASSEMBLY__
48extern unsigned long get_clock_freq(void);
49#endif
50
51#define CONFIG_SYS_CLK_FREQ 66666666
52#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ
53
54#ifdef CONFIG_MK_ATM
55#define CONFIG_PQ_MDS_PIB
56#define CONFIG_PQ_MDS_PIB_ATM
57#endif
58
59
60
61
62#define CONFIG_L2_CACHE
63#define CONFIG_BTB
64
65#ifdef CONFIG_MK_NAND
66#define CONFIG_NAND_U_BOOT 1
67#define CONFIG_RAMBOOT_NAND 1
68#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000
69#endif
70
71
72
73
74#define CONFIG_ENABLE_36BIT_PHYS 1
75
76#define CONFIG_BOARD_EARLY_INIT_F 1
77#define CONFIG_HWCONFIG
78
79#define CONFIG_SYS_MEMTEST_START 0x00200000
80#define CONFIG_SYS_MEMTEST_END 0x00400000
81
82
83
84
85#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
86#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
87#define CONFIG_SYS_L2_SIZE (512 << 10)
88#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
89
90
91
92
93
94#define CONFIG_SYS_CCSRBAR 0xe0000000
95#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
96
97#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
98
99
100#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
101#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
102#else
103#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
104#endif
105
106
107#define CONFIG_FSL_DDR3
108#undef CONFIG_FSL_DDR_INTERACTIVE
109#define CONFIG_SPD_EEPROM
110#define CONFIG_DDR_SPD
111#define CONFIG_DDR_DLL
112#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
113
114#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
115
116#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
117
118#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
119
120#define CONFIG_NUM_DDR_CONTROLLERS 1
121#define CONFIG_DIMM_SLOTS_PER_CTLR 1
122#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
123
124
125#define SPD_EEPROM_ADDRESS1 0x51
126#define SPD_EEPROM_ADDRESS2 0x52
127
128
129#define CONFIG_SYS_SDRAM_SIZE 1024
130#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
131#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
132#define CONFIG_SYS_DDR_TIMING_3 0x00020000
133#define CONFIG_SYS_DDR_TIMING_0 0x00330004
134#define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644
135#define CONFIG_SYS_DDR_TIMING_2 0x002888D0
136#define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000
137#define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040
138#define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521
139#define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000
140#define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000
141#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
142#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000
143#define CONFIG_SYS_DDR_TIMING_4 0x00220001
144#define CONFIG_SYS_DDR_TIMING_5 0x03402400
145#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600
146#define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604
147#define CONFIG_SYS_DDR_CDR_1 0x80040000
148#define CONFIG_SYS_DDR_CDR_2 0x00000000
149#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
150#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
151#define CONFIG_SYS_DDR_CONTROL 0xc7000000
152#define CONFIG_SYS_DDR_CONTROL2 0x24400000
153
154#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
155#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
156#define CONFIG_SYS_DDR_SBE 0x00010000
157
158#undef CONFIG_CLOCKS_IN_MHZ
159
160
161
162
163
164#define CONFIG_SYS_FLASH_BASE 0xfe000000
165#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
166
167#define CONFIG_SYS_BCSR_BASE 0xf8000000
168#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
169
170
171#define CONFIG_FLASH_BR_PRELIM 0xfe000801
172#define CONFIG_FLASH_OR_PRELIM 0xfe000ff7
173
174
175#define CONFIG_SYS_BR1_PRELIM 0xf8000801
176#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
177
178
179#define CONFIG_SYS_BR4_PRELIM 0xf8008801
180#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
181
182
183#define CONFIG_SYS_BR5_PRELIM 0xf8010801
184#define CONFIG_SYS_OR5_PRELIM 0xffffe9f7
185
186#define CONFIG_SYS_MAX_FLASH_BANKS 1
187#define CONFIG_SYS_MAX_FLASH_SECT 512
188#undef CONFIG_SYS_FLASH_CHECKSUM
189#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
190#define CONFIG_SYS_FLASH_WRITE_TOUT 500
191
192#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
193
194#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
195#define CONFIG_SYS_RAMBOOT
196#else
197#undef CONFIG_SYS_RAMBOOT
198#endif
199
200#define CONFIG_FLASH_CFI_DRIVER
201#define CONFIG_SYS_FLASH_CFI
202#define CONFIG_SYS_FLASH_EMPTY_INFO
203
204
205#ifndef CONFIG_NAND_SPL
206#define CONFIG_SYS_NAND_BASE 0xFC000000
207#else
208#define CONFIG_SYS_NAND_BASE 0xFFF00000
209#endif
210
211
212#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
213#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
214#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
215#define CONFIG_SYS_NAND_U_BOOT_START \
216 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
217#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
218#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
219#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
220
221#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
222#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
223#define CONFIG_SYS_MAX_NAND_DEVICE 1
224#define CONFIG_MTD_NAND_VERIFY_WRITE 1
225#define CONFIG_CMD_NAND 1
226#define CONFIG_NAND_FSL_ELBC 1
227#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
228#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
229 | (2<<BR_DECC_SHIFT) \
230 | BR_PS_8 \
231 | BR_MS_FCM \
232 | BR_V)
233#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 \
234 | OR_FCM_CSCT \
235 | OR_FCM_CST \
236 | OR_FCM_CHT \
237 | OR_FCM_SCY_1 \
238 | OR_FCM_TRLX \
239 | OR_FCM_EHTR)
240
241#ifdef CONFIG_RAMBOOT_NAND
242#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM
243#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM
244#define CONFIG_SYS_BR3_PRELIM CONFIG_FLASH_BR_PRELIM
245#define CONFIG_SYS_OR3_PRELIM CONFIG_FLASH_OR_PRELIM
246#else
247#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM
248#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM
249#define CONFIG_SYS_BR3_PRELIM CONFIG_NAND_BR_PRELIM
250#define CONFIG_SYS_OR3_PRELIM CONFIG_NAND_OR_PRELIM
251#endif
252
253
254
255
256#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000
257#define CONFIG_SYS_LBC_SDRAM_SIZE 64
258
259#define CONFIG_SYS_LBC_LCRR 0x00000004
260#define CONFIG_SYS_LBC_LBCR 0x00040000
261#define CONFIG_SYS_LBC_LSRT 0x20000000
262#define CONFIG_SYS_LBC_MRTPR 0x00000000
263
264#define CONFIG_SYS_INIT_RAM_LOCK 1
265#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000
266#define CONFIG_SYS_INIT_RAM_END 0x4000
267
268#define CONFIG_SYS_GBL_DATA_SIZE 128
269#define CONFIG_SYS_GBL_DATA_OFFSET \
270 (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
271#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
272
273#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
274#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
275
276
277#define CONFIG_CONS_INDEX 1
278#define CONFIG_SERIAL_MULTI 1
279#undef CONFIG_SERIAL_SOFTWARE_FIFO
280#define CONFIG_SYS_NS16550
281#define CONFIG_SYS_NS16550_SERIAL
282#define CONFIG_SYS_NS16550_REG_SIZE 1
283#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
284#ifdef CONFIG_NAND_SPL
285#define CONFIG_NS16550_MIN_FUNCTIONS
286#endif
287
288#define CONFIG_SYS_BAUDRATE_TABLE \
289 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
290
291#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
292#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
293
294
295#define CONFIG_SYS_HUSH_PARSER
296#ifdef CONFIG_SYS_HUSH_PARSER
297#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
298#endif
299
300
301#define CONFIG_OF_LIBFDT 1
302#define CONFIG_OF_BOARD_SETUP 1
303#define CONFIG_OF_STDOUT_VIA_ALIAS 1
304
305
306
307
308#define CONFIG_FSL_I2C
309#define CONFIG_HARD_I2C
310#undef CONFIG_SOFT_I2C
311#define CONFIG_I2C_MULTI_BUS
312#define CONFIG_SYS_I2C_SPEED 400000
313#define CONFIG_SYS_I2C_SLAVE 0x7F
314#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}}
315#define CONFIG_SYS_I2C_OFFSET 0x3000
316#define CONFIG_SYS_I2C2_OFFSET 0x3100
317
318
319
320
321#define CONFIG_ID_EEPROM
322#ifdef CONFIG_ID_EEPROM
323#define CONFIG_SYS_I2C_EEPROM_NXID
324#endif
325#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
326#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
327#define CONFIG_SYS_EEPROM_BUS_NUM 1
328
329#define PLPPAR1_I2C_BIT_MASK 0x0000000F
330#define PLPPAR1_I2C2_VAL 0x00000000
331#define PLPPAR1_ESDHC_VAL 0x0000000A
332#define PLPDIR1_I2C_BIT_MASK 0x0000000F
333#define PLPDIR1_I2C2_VAL 0x0000000F
334#define PLPDIR1_ESDHC_VAL 0x00000006
335#define PLPPAR1_UART0_BIT_MASK 0x00000fc0
336#define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80
337#define PLPDIR1_UART0_BIT_MASK 0x00000fc0
338#define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80
339
340
341
342
343
344#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
345#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
346#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
347#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
348#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
349#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
350#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
351#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
352
353#define CONFIG_SYS_SRIO_MEM_VIRT 0xc0000000
354#define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000
355#define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000
356
357#ifdef CONFIG_QE
358
359
360
361#define CONFIG_SYS_UCC_RGMII_MODE
362#undef CONFIG_SYS_UCC_RMII_MODE
363
364#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
365#define CONFIG_UEC_ETH
366#define CONFIG_ETHPRIME "UEC0"
367#define CONFIG_PHY_MODE_NEED_CHANGE
368
369#define CONFIG_UEC_ETH1
370#define CONFIG_HAS_ETH0
371
372#ifdef CONFIG_UEC_ETH1
373#define CONFIG_SYS_UEC1_UCC_NUM 0
374#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
375#if defined(CONFIG_SYS_UCC_RGMII_MODE)
376#define CONFIG_SYS_UEC1_TX_CLK QE_CLK12
377#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
378#define CONFIG_SYS_UEC1_PHY_ADDR 7
379#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID
380#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
381#elif defined(CONFIG_SYS_UCC_RMII_MODE)
382#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16
383#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
384#define CONFIG_SYS_UEC1_PHY_ADDR 8
385#define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII
386#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
387#endif
388#endif
389
390#define CONFIG_UEC_ETH2
391#define CONFIG_HAS_ETH1
392
393#ifdef CONFIG_UEC_ETH2
394#define CONFIG_SYS_UEC2_UCC_NUM 1
395#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
396#if defined(CONFIG_SYS_UCC_RGMII_MODE)
397#define CONFIG_SYS_UEC2_TX_CLK QE_CLK17
398#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
399#define CONFIG_SYS_UEC2_PHY_ADDR 1
400#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID
401#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
402#elif defined(CONFIG_SYS_UCC_RMII_MODE)
403#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16
404#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
405#define CONFIG_SYS_UEC2_PHY_ADDR 0x9
406#define CONFIG_SYS_UEC2_INTERFACE_TYPE RMII
407#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
408#endif
409#endif
410
411#define CONFIG_UEC_ETH3
412#define CONFIG_HAS_ETH2
413
414#ifdef CONFIG_UEC_ETH3
415#define CONFIG_SYS_UEC3_UCC_NUM 2
416#define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE
417#if defined(CONFIG_SYS_UCC_RGMII_MODE)
418#define CONFIG_SYS_UEC3_TX_CLK QE_CLK12
419#define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH
420#define CONFIG_SYS_UEC3_PHY_ADDR 2
421#define CONFIG_SYS_UEC3_INTERFACE_TYPE RGMII_ID
422#define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000
423#elif defined(CONFIG_SYS_UCC_RMII_MODE)
424#define CONFIG_SYS_UEC3_TX_CLK QE_CLK16
425#define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH
426#define CONFIG_SYS_UEC3_PHY_ADDR 0xA
427#define CONFIG_SYS_UEC3_INTERFACE_TYPE RMII
428#define CONFIG_SYS_UEC3_INTERFACE_SPEED 100
429#endif
430#endif
431
432#define CONFIG_UEC_ETH4
433#define CONFIG_HAS_ETH3
434
435#ifdef CONFIG_UEC_ETH4
436#define CONFIG_SYS_UEC4_UCC_NUM 3
437#define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE
438#if defined(CONFIG_SYS_UCC_RGMII_MODE)
439#define CONFIG_SYS_UEC4_TX_CLK QE_CLK17
440#define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH
441#define CONFIG_SYS_UEC4_PHY_ADDR 3
442#define CONFIG_SYS_UEC4_INTERFACE_TYPE RGMII_ID
443#define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000
444#elif defined(CONFIG_SYS_UCC_RMII_MODE)
445#define CONFIG_SYS_UEC4_TX_CLK QE_CLK16
446#define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH
447#define CONFIG_SYS_UEC4_PHY_ADDR 0xB
448#define CONFIG_SYS_UEC4_INTERFACE_TYPE RMII
449#define CONFIG_SYS_UEC4_INTERFACE_SPEED 100
450#endif
451#endif
452
453#undef CONFIG_UEC_ETH6
454#define CONFIG_HAS_ETH5
455
456#ifdef CONFIG_UEC_ETH6
457#define CONFIG_SYS_UEC6_UCC_NUM 5
458#define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE
459#define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE
460#define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH
461#define CONFIG_SYS_UEC6_PHY_ADDR 4
462#define CONFIG_SYS_UEC6_INTERFACE_TYPE SGMII
463#define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000
464#endif
465
466#undef CONFIG_UEC_ETH8
467#define CONFIG_HAS_ETH7
468
469#ifdef CONFIG_UEC_ETH8
470#define CONFIG_SYS_UEC8_UCC_NUM 7
471#define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE
472#define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE
473#define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH
474#define CONFIG_SYS_UEC8_PHY_ADDR 6
475#define CONFIG_SYS_UEC8_INTERFACE_TYPE SGMII
476#define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000
477#endif
478
479#endif
480
481#if defined(CONFIG_PCI)
482
483#define CONFIG_NET_MULTI
484#define CONFIG_PCI_PNP
485
486#undef CONFIG_EEPRO100
487#undef CONFIG_TULIP
488
489#undef CONFIG_PCI_SCAN_SHOW
490
491#endif
492
493#ifndef CONFIG_NET_MULTI
494#define CONFIG_NET_MULTI 1
495#endif
496
497
498
499
500#if defined(CONFIG_SYS_RAMBOOT)
501#if defined(CONFIG_RAMBOOT_NAND)
502#define CONFIG_ENV_IS_IN_NAND 1
503#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
504#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
505#endif
506#else
507#define CONFIG_ENV_IS_IN_FLASH 1
508#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
509#define CONFIG_ENV_SECT_SIZE 0x20000
510#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
511#endif
512
513#define CONFIG_LOADS_ECHO 1
514#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
515
516
517#define CONFIG_SYS_QE_FW_ADDR 0xfff00000
518
519
520
521
522#define CONFIG_BOOTP_BOOTFILESIZE
523#define CONFIG_BOOTP_BOOTPATH
524#define CONFIG_BOOTP_GATEWAY
525#define CONFIG_BOOTP_HOSTNAME
526
527
528
529
530
531#include <config_cmd_default.h>
532
533#define CONFIG_CMD_PING
534#define CONFIG_CMD_I2C
535#define CONFIG_CMD_MII
536#define CONFIG_CMD_ELF
537#define CONFIG_CMD_IRQ
538#define CONFIG_CMD_SETEXPR
539#define CONFIG_CMD_REGINFO
540
541#if defined(CONFIG_PCI)
542 #define CONFIG_CMD_PCI
543#endif
544
545
546#undef CONFIG_WATCHDOG
547
548#define CONFIG_MMC 1
549
550#ifdef CONFIG_MMC
551#define CONFIG_FSL_ESDHC
552#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
553#define CONFIG_CMD_MMC
554#define CONFIG_GENERIC_MMC
555#define CONFIG_CMD_EXT2
556#define CONFIG_CMD_FAT
557#define CONFIG_DOS_PARTITION
558#endif
559
560
561
562
563#define CONFIG_SYS_LONGHELP
564#define CONFIG_CMDLINE_EDITING
565#define CONFIG_AUTO_COMPLETE
566#define CONFIG_SYS_LOAD_ADDR 0x2000000
567#define CONFIG_SYS_PROMPT "=> "
568#if defined(CONFIG_CMD_KGDB)
569#define CONFIG_SYS_CBSIZE 2048
570#else
571#define CONFIG_SYS_CBSIZE 512
572#endif
573#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
574
575#define CONFIG_SYS_MAXARGS 32
576#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
577
578#define CONFIG_SYS_HZ 1000
579
580
581
582
583
584
585#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
586
587
588
589
590
591
592
593#define BOOTFLAG_COLD 0x01
594#define BOOTFLAG_WARM 0x02
595
596#if defined(CONFIG_CMD_KGDB)
597#define CONFIG_KGDB_BAUDRATE 230400
598#define CONFIG_KGDB_SER_INDEX 2
599#endif
600
601
602
603
604#define CONFIG_HOSTNAME mpc8569mds
605#define CONFIG_ROOTPATH /nfsroot
606#define CONFIG_BOOTFILE your.uImage
607
608#define CONFIG_SERVERIP 192.168.1.1
609#define CONFIG_GATEWAYIP 192.168.1.1
610#define CONFIG_NETMASK 255.255.255.0
611
612#define CONFIG_LOADADDR 200000
613
614#define CONFIG_BOOTDELAY 10
615#undef CONFIG_BOOTARGS
616
617#define CONFIG_BAUDRATE 115200
618
619#define CONFIG_EXTRA_ENV_SETTINGS \
620 "netdev=eth0\0" \
621 "consoledev=ttyS0\0" \
622 "ramdiskaddr=600000\0" \
623 "ramdiskfile=your.ramdisk.u-boot\0" \
624 "fdtaddr=400000\0" \
625 "fdtfile=your.fdt.dtb\0" \
626 "nfsargs=setenv bootargs root=/dev/nfs rw " \
627 "nfsroot=$serverip:$rootpath " \
628 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
629 "console=$consoledev,$baudrate $othbootargs\0" \
630 "ramargs=setenv bootargs root=/dev/ram rw " \
631 "console=$consoledev,$baudrate $othbootargs\0" \
632
633#define CONFIG_NFSBOOTCOMMAND \
634 "run nfsargs;" \
635 "tftp $loadaddr $bootfile;" \
636 "tftp $fdtaddr $fdtfile;" \
637 "bootm $loadaddr - $fdtaddr"
638
639#define CONFIG_RAMBOOTCOMMAND \
640 "run ramargs;" \
641 "tftp $ramdiskaddr $ramdiskfile;" \
642 "tftp $loadaddr $bootfile;" \
643 "bootm $loadaddr $ramdiskaddr"
644
645#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
646
647#endif
648