1/* 2 * (C) Copyright 2001-2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31/* 32 * Imported from global configuration: 33 * CONFIG_MPC8255 34 * CONFIG_MPC8265 35 * CONFIG_200MHz 36 * CONFIG_266MHz 37 * CONFIG_300MHz 38 * CONFIG_L2_CACHE 39 * CONFIG_BUSMODE_60x 40 */ 41 42/* 43 * High Level Configuration Options 44 * (easy to change) 45 */ 46 47#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ 48 49#if 0 50#define CONFIG_TQM8260 100 /* ...on a TQM8260 module Rev.100 */ 51#else 52#define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */ 53#endif 54 55#define CONFIG_CPM2 1 /* Has a CPM2 */ 56 57#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */ 58 59#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 60 61#define CONFIG_BOOTCOUNT_LIMIT 62 63#define CONFIG_BAUDRATE 115200 64 65#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" 66 67#undef CONFIG_BOOTARGS 68 69#define CONFIG_EXTRA_ENV_SETTINGS \ 70 "netdev=eth0\0" \ 71 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 72 "nfsroot=${serverip}:${rootpath}\0" \ 73 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 74 "addip=setenv bootargs ${bootargs} " \ 75 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 76 ":${hostname}:${netdev}:off panic=1\0" \ 77 "flash_nfs=run nfsargs addip;" \ 78 "bootm ${kernel_addr}\0" \ 79 "flash_self=run ramargs addip;" \ 80 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 81 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 82 "rootpath=/opt/eldk/ppc_6xx\0" \ 83 "bootfile=tqm8260/uImage\0" \ 84 "kernel_addr=400C0000\0" \ 85 "ramdisk_addr=40240000\0" \ 86 "" 87#define CONFIG_BOOTCOMMAND "run flash_self" 88 89/* enable I2C and select the hardware/software driver */ 90#undef CONFIG_HARD_I2C /* I2C with hardware support */ 91#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ 92#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 93#define CONFIG_SYS_I2C_SLAVE 0x7F 94 95/* 96 * Software (bit-bang) I2C driver configuration 97 */ 98 99/* TQM8260 Rev.100 has the clock and data pins swapped (!!!) on EEPROM */ 100#if (CONFIG_TQM8260 <= 100) 101 102#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ 103#define I2C_ACTIVE (iop->pdir |= 0x00020000) 104#define I2C_TRISTATE (iop->pdir &= ~0x00020000) 105#define I2C_READ ((iop->pdat & 0x00020000) != 0) 106#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00020000; \ 107 else iop->pdat &= ~0x00020000 108#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00010000; \ 109 else iop->pdat &= ~0x00010000 110#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ 111 112#else 113 114#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ 115#define I2C_ACTIVE (iop->pdir |= 0x00010000) 116#define I2C_TRISTATE (iop->pdir &= ~0x00010000) 117#define I2C_READ ((iop->pdat & 0x00010000) != 0) 118#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ 119 else iop->pdat &= ~0x00010000 120#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ 121 else iop->pdat &= ~0x00020000 122#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ 123#endif 124 125#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 126#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 127#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 128#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 129 130#define CONFIG_I2C_X 131 132/* 133 * select serial console configuration 134 * 135 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then 136 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 137 * for SCC). 138 * 139 * if CONFIG_CONS_NONE is defined, then the serial console routines must 140 * defined elsewhere (for example, on the cogent platform, there are serial 141 * ports on the motherboard which are used for the serial console - see 142 * cogent/cma101/serial.[ch]). 143 */ 144#define CONFIG_CONS_ON_SMC /* define if console on SMC */ 145#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ 146#undef CONFIG_CONS_NONE /* define if console on something else*/ 147#ifdef CONFIG_82xx_CONS_SMC1 148#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ 149#endif 150#ifdef CONFIG_82xx_CONS_SMC2 151#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ 152#endif 153 154#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ 155#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ 156#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */ 157 158/* 159 * select ethernet configuration 160 * 161 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then 162 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 163 * for FCC) 164 * 165 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be 166 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. 167 * 168 * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the 169 * X.29 connector, and FCC2 is hardwired to the X.1 connector) 170 */ 171#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ 172#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ 173#undef CONFIG_ETHER_NONE /* define if ether on something else */ 174#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ 175 176#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) 177 178/* 179 * - RX clk is CLK11 180 * - TX clk is CLK12 181 */ 182# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) 183 184#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) 185 186/* 187 * - Rx-CLK is CLK13 188 * - Tx-CLK is CLK14 189 * - RAM for BD/Buffers is on the 60x Bus (see 28-13) 190 * - Enable Full Duplex in FSMR 191 */ 192# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) 193# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) 194# define CONFIG_SYS_CPMFCR_RAMTYPE 0 195# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) 196 197#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ 198 199 200/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ 201#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265) 202# define CONFIG_8260_CLKIN 66666666 /* in Hz */ 203#else /* !CONFIG_MPC8255 && !CONFIG_MPC8265 */ 204# ifndef CONFIG_300MHz 205# define CONFIG_8260_CLKIN 66666666 /* in Hz */ 206# else 207# define CONFIG_8260_CLKIN 83333000 /* in Hz */ 208# endif 209#endif /* CONFIG_MPC8255 */ 210 211#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 212#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 213 214#undef CONFIG_WATCHDOG /* watchdog disabled */ 215 216#define CONFIG_TIMESTAMP /* Print image info with timestamp */ 217 218 219/* 220 * BOOTP options 221 */ 222#define CONFIG_BOOTP_SUBNETMASK 223#define CONFIG_BOOTP_GATEWAY 224#define CONFIG_BOOTP_HOSTNAME 225#define CONFIG_BOOTP_BOOTPATH 226#define CONFIG_BOOTP_BOOTFILESIZE 227 228 229/* 230 * Command line configuration. 231 */ 232#include <config_cmd_default.h> 233 234#define CONFIG_CMD_DHCP 235#define CONFIG_CMD_I2C 236#define CONFIG_CMD_EEPROM 237#define CONFIG_CMD_NFS 238#define CONFIG_CMD_SNTP 239 240 241/* 242 * Miscellaneous configurable options 243 */ 244#define CONFIG_SYS_LONGHELP /* undef to save memory */ 245#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 246 247#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 248#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 249#ifdef CONFIG_SYS_HUSH_PARSER 250#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 251#endif 252 253#if defined(CONFIG_CMD_KGDB) 254#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 255#else 256#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 257#endif 258#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 259#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 260#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 261 262#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 263#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 264 265#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 266 267#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 268 269#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 270 271#define CONFIG_SYS_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */ 272 273/* 274 * For booting Linux, the board info and command line data 275 * have to be in the first 8 MB of memory, since this is 276 * the maximum mapped by the Linux kernel during initialization. 277 */ 278#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 279 280 281/* What should the base address of the main FLASH be and how big is 282 * it (in MBytes)? This must contain TEXT_BASE from board/tqm8260/config.mk 283 * The main FLASH is whichever is connected to *CS0. 284 */ 285#define CONFIG_SYS_FLASH0_BASE 0x40000000 286#define CONFIG_SYS_FLASH1_BASE 0x60000000 287#define CONFIG_SYS_FLASH0_SIZE 32 288#define CONFIG_SYS_FLASH1_SIZE 32 289 290/* Flash bank size (for preliminary settings) 291 */ 292#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE 293 294/*----------------------------------------------------------------------- 295 * FLASH organization 296 */ 297#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ 298#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ 299 300#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ 301#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ 302 303/* use CFI flash driver */ 304#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 305#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 306#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 307#define CONFIG_SYS_FLASH_EMPTY_INFO 1 308#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 309 310#define CONFIG_ENV_IS_IN_FLASH 1 311#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 312#define CONFIG_ENV_SIZE 0x08000 313#define CONFIG_ENV_SECT_SIZE 0x40000 314#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 315#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE 316 317/*----------------------------------------------------------------------- 318 * Hardware Information Block 319 */ 320#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 321#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 322#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 323 324/*----------------------------------------------------------------------- 325 * Hard Reset Configuration Words 326 * 327 * if you change bits in the HRCW, you must also change the CONFIG_SYS_* 328 * defines for the various registers affected by the HRCW e.g. changing 329 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. 330 */ 331#define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) 332 333#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265) 334# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) 335#else /* ! MPC8255 && !MPC8265 */ 336# if defined(CONFIG_266MHz) 337# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) 338# elif defined(CONFIG_300MHz) 339# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0110) 340# else 341# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__) 342# endif 343#endif /* CONFIG_MPC8255 */ 344 345/* no slaves so just fill with zeros */ 346#define CONFIG_SYS_HRCW_SLAVE1 0 347#define CONFIG_SYS_HRCW_SLAVE2 0 348#define CONFIG_SYS_HRCW_SLAVE3 0 349#define CONFIG_SYS_HRCW_SLAVE4 0 350#define CONFIG_SYS_HRCW_SLAVE5 0 351#define CONFIG_SYS_HRCW_SLAVE6 0 352#define CONFIG_SYS_HRCW_SLAVE7 0 353 354/*----------------------------------------------------------------------- 355 * Internal Memory Mapped Register 356 */ 357#define CONFIG_SYS_IMMR 0xFFF00000 358 359/*----------------------------------------------------------------------- 360 * Definitions for initial stack pointer and data area (in DPRAM) 361 */ 362#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 363#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ 364#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ 365#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 366#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 367 368/*----------------------------------------------------------------------- 369 * Start addresses for the final memory configuration 370 * (Set up by the startup code) 371 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 372 * 373 * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM 374 * is mapped at SDRAM_BASE2_PRELIM. 375 */ 376#define CONFIG_SYS_SDRAM_BASE 0x00000000 377#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE 378#define CONFIG_SYS_MONITOR_BASE TEXT_BASE 379#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 380#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc()*/ 381 382/* 383 * Internal Definitions 384 * 385 * Boot Flags 386 */ 387#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ 388#define BOOTFLAG_WARM 0x02 /* Software reboot */ 389 390 391/*----------------------------------------------------------------------- 392 * Cache Configuration 393 */ 394#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ 395#if defined(CONFIG_CMD_KGDB) 396# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 397#endif 398 399/*----------------------------------------------------------------------- 400 * HIDx - Hardware Implementation-dependent Registers 2-11 401 *----------------------------------------------------------------------- 402 * HID0 also contains cache control - initially enable both caches and 403 * invalidate contents, then the final state leaves only the instruction 404 * cache enabled. Note that Power-On and Hard reset invalidate the caches, 405 * but Soft reset does not. 406 * 407 * HID1 has only read-only information - nothing to set. 408 */ 409#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ 410 HID0_IFEM|HID0_ABE) 411#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE) 412#define CONFIG_SYS_HID2 0 413 414/*----------------------------------------------------------------------- 415 * RMR - Reset Mode Register 5-5 416 *----------------------------------------------------------------------- 417 * turn on Checkstop Reset Enable 418 */ 419#define CONFIG_SYS_RMR RMR_CSRE 420 421/*----------------------------------------------------------------------- 422 * BCR - Bus Configuration 4-25 423 *----------------------------------------------------------------------- 424 */ 425#ifdef CONFIG_BUSMODE_60x 426#define CONFIG_SYS_BCR (BCR_EBM|BCR_L2C|BCR_LETM|\ 427 BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode */ 428#else 429#define BCR_APD01 0x10000000 430#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ 431#endif 432 433/*----------------------------------------------------------------------- 434 * SIUMCR - SIU Module Configuration 4-31 435 *----------------------------------------------------------------------- 436 */ 437#if 0 438#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) 439#else 440#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10) 441#endif 442 443 444/*----------------------------------------------------------------------- 445 * SYPCR - System Protection Control 4-35 446 * SYPCR can only be written once after reset! 447 *----------------------------------------------------------------------- 448 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable 449 */ 450#if defined(CONFIG_WATCHDOG) 451#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 452 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) 453#else 454#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 455 SYPCR_SWRI|SYPCR_SWP) 456#endif /* CONFIG_WATCHDOG */ 457 458/*----------------------------------------------------------------------- 459 * TMCNTSC - Time Counter Status and Control 4-40 460 *----------------------------------------------------------------------- 461 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, 462 * and enable Time Counter 463 */ 464#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) 465 466/*----------------------------------------------------------------------- 467 * PISCR - Periodic Interrupt Status and Control 4-42 468 *----------------------------------------------------------------------- 469 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable 470 * Periodic timer 471 */ 472#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) 473 474/*----------------------------------------------------------------------- 475 * SCCR - System Clock Control 9-8 476 *----------------------------------------------------------------------- 477 * Ensure DFBRG is Divide by 16 478 */ 479#define CONFIG_SYS_SCCR 0 480 481/*----------------------------------------------------------------------- 482 * RCCR - RISC Controller Configuration 13-7 483 *----------------------------------------------------------------------- 484 */ 485#define CONFIG_SYS_RCCR 0 486 487/* 488 * Init Memory Controller: 489 * 490 * Bank Bus Machine PortSz Device 491 * ---- --- ------- ------ ------ 492 * 0 60x GPCM 64 bit FLASH 493 * 1 60x SDRAM 64 bit SDRAM 494 * 2 Local SDRAM 32 bit SDRAM 495 * 496 */ 497 498 /* Initialize SDRAM on local bus 499 */ 500#define CONFIG_SYS_INIT_LOCAL_SDRAM 501 502#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ 503 504/* Minimum mask to separate preliminary 505 * address ranges for CS[0:2] 506 */ 507#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */ 508#define CONFIG_SYS_LOCAL_SDRAM_LIMIT (128<<20) /* less than 128 MB */ 509 510#define CONFIG_SYS_MPTPR 0x4000 511 512/*----------------------------------------------------------------------------- 513 * Address for Mode Register Set (MRS) command 514 *----------------------------------------------------------------------------- 515 * In fact, the address is rather configuration data presented to the SDRAM on 516 * its address lines. Because the address lines may be mux'ed externally either 517 * for 8 column or 9 column devices, some bits appear twice in the 8260's 518 * address: 519 * 520 * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length | 521 * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 | 522 * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 | 523 * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 | 524 * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 | 525 *----------------------------------------------------------------------------- 526 */ 527#define CONFIG_SYS_MRS_OFFS 0x00000110 528 529 530/* Bank 0 - FLASH 531 */ 532#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ 533 BRx_PS_64 |\ 534 BRx_MS_GPCM_P |\ 535 BRx_V) 536 537#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ 538 ORxG_CSNT |\ 539 ORxG_ACS_DIV1 |\ 540 ORxG_SCY_3_CLK |\ 541 ORxG_EHTR |\ 542 ORxG_TRLX) 543 544 /* SDRAM on TQM8260 can have either 8 or 9 columns. 545 * The number affects configuration values. 546 */ 547 548/* Bank 1 - 60x bus SDRAM 549 */ 550#define CONFIG_SYS_PSRT 0x20 551#define CONFIG_SYS_LSRT 0x20 552#ifndef CONFIG_SYS_RAMBOOT 553#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ 554 BRx_PS_64 |\ 555 BRx_MS_SDRAM_P |\ 556 BRx_V) 557 558#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_8COL 559 560 561 /* SDRAM initialization values for 8-column chips 562 */ 563#define CONFIG_SYS_OR1_8COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ 564 ORxS_BPD_4 |\ 565 ORxS_ROWST_PBI1_A7 |\ 566 ORxS_NUMR_12) 567 568#define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\ 569 PSDMR_SDAM_A15_IS_A5 |\ 570 PSDMR_BSMA_A12_A14 |\ 571 PSDMR_SDA10_PBI1_A8 |\ 572 PSDMR_RFRC_7_CLK |\ 573 PSDMR_PRETOACT_2W |\ 574 PSDMR_ACTTORW_2W |\ 575 PSDMR_LDOTOPRE_1C |\ 576 PSDMR_WRC_2C |\ 577 PSDMR_EAMUX |\ 578 PSDMR_CL_2) 579 580 /* SDRAM initialization values for 9-column chips 581 */ 582#define CONFIG_SYS_OR1_9COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ 583 ORxS_BPD_4 |\ 584 ORxS_ROWST_PBI1_A5 |\ 585 ORxS_NUMR_13) 586 587#define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\ 588 PSDMR_SDAM_A16_IS_A5 |\ 589 PSDMR_BSMA_A12_A14 |\ 590 PSDMR_SDA10_PBI1_A7 |\ 591 PSDMR_RFRC_7_CLK |\ 592 PSDMR_PRETOACT_2W |\ 593 PSDMR_ACTTORW_2W |\ 594 PSDMR_LDOTOPRE_1C |\ 595 PSDMR_WRC_2C |\ 596 PSDMR_EAMUX |\ 597 PSDMR_CL_2) 598 599/* Bank 2 - Local bus SDRAM 600 */ 601#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM 602#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\ 603 BRx_PS_32 |\ 604 BRx_MS_SDRAM_L |\ 605 BRx_V) 606 607#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL 608 609#define SDRAM_BASE2_PRELIM 0x80000000 610 611 /* SDRAM initialization values for 8-column chips 612 */ 613#define CONFIG_SYS_OR2_8COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ 614 ORxS_BPD_4 |\ 615 ORxS_ROWST_PBI1_A8 |\ 616 ORxS_NUMR_12) 617 618#define CONFIG_SYS_LSDMR_8COL (PSDMR_PBI |\ 619 PSDMR_SDAM_A15_IS_A5 |\ 620 PSDMR_BSMA_A13_A15 |\ 621 PSDMR_SDA10_PBI1_A9 |\ 622 PSDMR_RFRC_7_CLK |\ 623 PSDMR_PRETOACT_2W |\ 624 PSDMR_ACTTORW_2W |\ 625 PSDMR_BL |\ 626 PSDMR_LDOTOPRE_1C |\ 627 PSDMR_WRC_2C |\ 628 PSDMR_CL_2) 629 630 /* SDRAM initialization values for 9-column chips 631 */ 632#define CONFIG_SYS_OR2_9COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ 633 ORxS_BPD_4 |\ 634 ORxS_ROWST_PBI1_A6 |\ 635 ORxS_NUMR_13) 636 637#define CONFIG_SYS_LSDMR_9COL (PSDMR_PBI |\ 638 PSDMR_SDAM_A16_IS_A5 |\ 639 PSDMR_BSMA_A13_A15 |\ 640 PSDMR_SDA10_PBI1_A8 |\ 641 PSDMR_RFRC_7_CLK |\ 642 PSDMR_PRETOACT_2W |\ 643 PSDMR_ACTTORW_2W |\ 644 PSDMR_BL |\ 645 PSDMR_LDOTOPRE_1C |\ 646 PSDMR_WRC_2C |\ 647 PSDMR_CL_2) 648 649#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */ 650 651#endif /* CONFIG_SYS_RAMBOOT */ 652 653#endif /* __CONFIG_H */ 654