LXR uboot/include/configs/TQM8272.h

   1/*
   2 * (C) Copyright 2006
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24/*
  25 * board/config.h - configuration options, board specific
  26 */
  27
  28#ifndef __CONFIG_H
  29#define __CONFIG_H
  30
  31/*
  32 * High Level Configuration Options
  33 * (easy to change)
  34 */
  35
  36#define CONFIG_MPC8260          1       /* This is a MPC8260 CPU                */
  37#define CONFIG_MPC8272_FAMILY   1
  38#define CONFIG_TQM8272          1
  39
  40#define CONFIG_GET_CPU_STR_F    1       /* Get the CPU ID STR */
  41#define CONFIG_BOARD_GET_CPU_CLK_F      1 /* Get the CLKIN from board fct */
  42
  43#define STK82xx_150             1       /* on a STK82xx.150 */
  44
  45#define CONFIG_CPM2             1       /* Has a CPM2 */
  46
  47#define CONFIG_82xx_CONS_SMC1   1       /* console on SMC1              */
  48
  49#define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  50
  51#define CONFIG_BOARD_EARLY_INIT_R       1
  52
  53#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
  54#define CONFIG_BAUDRATE         230400
  55#else
  56#define CONFIG_BAUDRATE         115200
  57#endif
  58
  59#define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  60
  61#undef  CONFIG_BOOTARGS
  62
  63#define CONFIG_EXTRA_ENV_SETTINGS                                       \
  64        "netdev=eth0\0"                                                 \
  65        "consdev=ttyCPM0\0"                                             \
  66        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  67                "nfsroot=${serverip}:${rootpath}\0"                     \
  68        "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  69        "hostname=tqm8272\0"                                            \
  70        "addip=setenv bootargs ${bootargs} "                            \
  71                "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  72                ":${hostname}:${netdev}:off panic=1\0"                  \
  73        "addcons=setenv bootargs ${bootargs} "                          \
  74                "console=$(consdev),$(baudrate)\0"                      \
  75        "flash_nfs=run nfsargs addip addcons;"                          \
  76                "bootm ${kernel_addr}\0"                                \
  77        "flash_self=run ramargs addip addcons;"                         \
  78                "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  79        "net_nfs=tftp 300000 ${bootfile};"                              \
  80                "run nfsargs addip addcons;bootm\0"                     \
  81        "rootpath=/opt/eldk/ppc_82xx\0"                                 \
  82        "bootfile=/tftpboot/tqm8272/uImage\0"                           \
  83        "kernel_addr=40080000\0"                                        \
  84        "ramdisk_addr=40100000\0"                                       \
  85        "load=tftp 300000 /tftpboot/tqm8272/u-boot.bin\0"               \
  86        "update=protect off 40000000 4003ffff;era 40000000 4003ffff;"   \
  87                "cp.b 300000 40000000 40000;"                           \
  88                "setenv filesize;saveenv\0"                             \
  89        "cphwib=cp.b 4003fc00 33fc00 400\0"                             \
  90        "upd=run load cphwib update\0"                                  \
  91        ""
  92#define CONFIG_BOOTCOMMAND      "run flash_self"
  93
  94#define CONFIG_I2C      1
  95
  96#if CONFIG_I2C
  97/* enable I2C and select the hardware/software driver */
  98#undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
  99#define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
 100#define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address  */
 101#define CONFIG_SYS_I2C_SLAVE            0x7F
 102
 103/*
 104 * Software (bit-bang) I2C driver configuration
 105 */
 106#define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 107#define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 108#define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 109#define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 110#define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 111                        else    iop->pdat &= ~0x00010000
 112#define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 113                        else    iop->pdat &= ~0x00020000
 114#define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 115
 116#define CONFIG_I2C_X
 117
 118/* EEPROM */
 119#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 120#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 121#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 122#define CONFIG_SYS_I2C_MULTI_EEPROMS            1       /* more than one eeprom */
 123
 124/* I2C RTC */
 125#define CONFIG_RTC_DS1337               /* Use ds1337 rtc via i2c       */
 126#define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68              */
 127
 128/* I2C SYSMON (LM75) */
 129#define CONFIG_DTT_LM75         1               /* ON Semi's LM75       */
 130#define CONFIG_DTT_SENSORS      {0}             /* Sensor addresses     */
 131#define CONFIG_SYS_DTT_MAX_TEMP 70
 132#define CONFIG_SYS_DTT_LOW_TEMP -30
 133#define CONFIG_SYS_DTT_HYSTERESIS       3
 134
 135#else
 136#undef CONFIG_HARD_I2C
 137#undef CONFIG_SOFT_I2C
 138#endif
 139
 140/*
 141 * select serial console configuration
 142 *
 143 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 144 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 145 * for SCC).
 146 *
 147 * if CONFIG_CONS_NONE is defined, then the serial console routines must
 148 * defined elsewhere (for example, on the cogent platform, there are serial
 149 * ports on the motherboard which are used for the serial console - see
 150 * cogent/cma101/serial.[ch]).
 151 */
 152#define CONFIG_CONS_ON_SMC              /* define if console on SMC */
 153#undef  CONFIG_CONS_ON_SCC              /* define if console on SCC */
 154#undef  CONFIG_CONS_NONE                /* define if console on something else*/
 155#ifdef CONFIG_82xx_CONS_SMC1
 156#define CONFIG_CONS_INDEX       1       /* which serial channel for console */
 157#endif
 158#ifdef CONFIG_82xx_CONS_SMC2
 159#define CONFIG_CONS_INDEX       2       /* which serial channel for console */
 160#endif
 161
 162#undef  CONFIG_CONS_USE_EXTC            /* SMC/SCC use ext clock not brg_clk */
 163#define CONFIG_CONS_EXTC_RATE   3686400 /* SMC/SCC ext clk rate in Hz */
 164#define CONFIG_CONS_EXTC_PINSEL 0       /* pin select 0=CLK3/CLK9 */
 165
 166/*
 167 * select ethernet configuration
 168 *
 169 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 170 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 171 * for FCC)
 172 *
 173 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 174 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 175 *
 176 * (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
 177 * X.29 connector, and FCC2 is hardwired to the X.1 connector)
 178 */
 179#define CONFIG_SYS_FCC_ETHERNET
 180
 181#if defined(CONFIG_SYS_FCC_ETHERNET)
 182#undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
 183#define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
 184#undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 185#define CONFIG_ETHER_INDEX    2         /* which SCC/FCC channel for ethernet */
 186#else
 187#define CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
 188#undef  CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
 189#undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 190#define CONFIG_ETHER_INDEX    1         /* which SCC/FCC channel for ethernet */
 191#endif
 192
 193#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
 194
 195/*
 196 *  - RX clk is CLK11
 197 *  - TX clk is CLK12
 198 */
 199# define CONFIG_SYS_CMXSCR_VALUE        (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
 200
 201#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 202
 203/*
 204 * - Rx-CLK is CLK13
 205 * - Tx-CLK is CLK14
 206 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 207 * - Enable Full Duplex in FSMR
 208 */
 209# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
 210# define CONFIG_SYS_CMXFCR_VALUE        (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 211# define CONFIG_SYS_CPMFCR_RAMTYPE      0
 212# define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
 213
 214#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 215
 216#define CONFIG_MII                      /* MII PHY management           */
 217#define CONFIG_BITBANGMII               /* bit-bang MII PHY management  */
 218/*
 219 * GPIO pins used for bit-banged MII communications
 220 */
 221#define MDIO_PORT       2               /* Port C */
 222#define MDIO_DECLARE    volatile ioport_t *iop = ioport_addr ( \
 223                                (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
 224#define MDC_DECLARE     MDIO_DECLARE
 225
 226#if STK82xx_150
 227#define CONFIG_SYS_MDIO_PIN     0x00008000      /* PC16 */
 228#define CONFIG_SYS_MDC_PIN      0x00004000      /* PC17 */
 229#endif
 230
 231#if STK82xx_100
 232#define CONFIG_SYS_MDIO_PIN     0x00000002      /* PC30 */
 233#define CONFIG_SYS_MDC_PIN      0x00000001      /* PC31 */
 234#endif
 235
 236#if 1
 237#define MDIO_ACTIVE     (iop->pdir |=  CONFIG_SYS_MDIO_PIN)
 238#define MDIO_TRISTATE   (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
 239#define MDIO_READ       ((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
 240
 241#define MDIO(bit)       if(bit) iop->pdat |=  CONFIG_SYS_MDIO_PIN; \
 242                        else    iop->pdat &= ~CONFIG_SYS_MDIO_PIN
 243
 244#define MDC(bit)        if(bit) iop->pdat |=  CONFIG_SYS_MDC_PIN; \
 245                        else    iop->pdat &= ~CONFIG_SYS_MDC_PIN
 246#else
 247#define MDIO_ACTIVE     ({unsigned long tmp; tmp = iop->pdir; tmp |=  CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;})
 248#define MDIO_TRISTATE   ({unsigned long tmp; tmp = iop->pdir; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;})
 249#define MDIO_READ       ((iop->pdat &  CONFIG_SYS_MDIO_PIN) != 0)
 250
 251#define MDIO(bit)       if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |=  CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}\
 252                        else    {unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}
 253
 254#define MDC(bit)        if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |=  CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}\
 255                        else    {unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}
 256#endif
 257
 258#define MIIDELAY        udelay(1)
 259
 260
 261/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 262#define CONFIG_8260_CLKIN       66666666        /* in Hz */
 263
 264#define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 265#undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
 266
 267#undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 268
 269#define CONFIG_TIMESTAMP                /* Print image info with timestamp */
 270
 271/*
 272 * BOOTP options
 273 */
 274#define CONFIG_BOOTP_SUBNETMASK
 275#define CONFIG_BOOTP_GATEWAY
 276#define CONFIG_BOOTP_HOSTNAME
 277#define CONFIG_BOOTP_BOOTPATH
 278#define CONFIG_BOOTP_BOOTFILESIZE
 279
 280
 281/*
 282 * Command line configuration.
 283 */
 284#include <config_cmd_default.h>
 285
 286#define CONFIG_CMD_I2C
 287#define CONFIG_CMD_DHCP
 288#define CONFIG_CMD_MII
 289#define CONFIG_CMD_NAND
 290#define CONFIG_CMD_NFS
 291#define CONFIG_CMD_PCI
 292#define CONFIG_CMD_PING
 293#define CONFIG_CMD_SNTP
 294
 295#if CONFIG_I2C
 296    #define CONFIG_CMD_I2C
 297    #define CONFIG_CMD_DATE
 298    #define CONFIG_CMD_DTT
 299    #define CONFIG_CMD_EEPROM
 300#endif
 301
 302
 303/*
 304 * Miscellaneous configurable options
 305 */
 306#define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 307#define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 308
 309#if 0
 310#define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 311#define CONFIG_SYS_HUSH_PARSER          1       /* Use the HUSH parser          */
 312#ifdef  CONFIG_SYS_HUSH_PARSER
 313#define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 314#endif
 315#endif
 316
 317#if defined(CONFIG_CMD_KGDB)
 318#define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 319#else
 320#define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 321#endif
 322#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 323#define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 324#define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 325
 326#define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 327#define CONFIG_SYS_MEMTEST_END  0x0C00000       /* 4 ... 12 MB in DRAM  */
 328
 329#define CONFIG_SYS_LOAD_ADDR    0x300000        /* default load address */
 330
 331#define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 332
 333#define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 334
 335#define CONFIG_SYS_RESET_ADDRESS 0x40000104     /* "bad" address                */
 336
 337/*
 338 * For booting Linux, the board info and command line data
 339 * have to be in the first 8 MB of memory, since this is
 340 * the maximum mapped by the Linux kernel during initialization.
 341 */
 342#define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 343
 344/*-----------------------------------------------------------------------
 345 * CAN stuff
 346 *-----------------------------------------------------------------------
 347 */
 348#define CONFIG_SYS_CAN_BASE     0x51000000
 349#define CONFIG_SYS_CAN_SIZE     1
 350#define CONFIG_SYS_CAN_BR       ((CONFIG_SYS_CAN_BASE & BRx_BA_MSK)     |\
 351                         BRx_PS_8                       |\
 352                         BRx_MS_UPMC                    |\
 353                         BRx_V)
 354
 355#define CONFIG_SYS_CAN_OR       (MEG_TO_AM(CONFIG_SYS_CAN_SIZE) |\
 356                         ORxU_BI)
 357
 358
 359/* What should the base address of the main FLASH be and how big is
 360 * it (in MBytes)? This must contain TEXT_BASE from board/tqm8272/config.mk
 361 * The main FLASH is whichever is connected to *CS0.
 362 */
 363#define CONFIG_SYS_FLASH0_BASE 0x40000000
 364#define CONFIG_SYS_FLASH0_SIZE 32       /* 32 MB */
 365
 366/* Flash bank size (for preliminary settings)
 367 */
 368#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
 369
 370/*-----------------------------------------------------------------------
 371 * FLASH organization
 372 */
 373#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks      */
 374#define CONFIG_SYS_MAX_FLASH_SECT       128     /* max num of sects on one chip */
 375
 376#define CONFIG_SYS_FLASH_CFI                            /* flash is CFI compat. */
 377#define CONFIG_FLASH_CFI_DRIVER                 /* Use common CFI driver*/
 378#define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector   */
 379#define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash*/
 380
 381#define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 382#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 383
 384#define CONFIG_SYS_UPDATE_FLASH_SIZE
 385
 386#define CONFIG_ENV_IS_IN_FLASH  1
 387#define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x40000)
 388#define CONFIG_ENV_SIZE         0x20000
 389#define CONFIG_ENV_SECT_SIZE    0x20000
 390#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
 391#define CONFIG_ENV_SIZE_REDUND  0x20000
 392
 393/* Where is the Hardwareinformation Block (from Monitor Sources) */
 394#define MON_RES_LENGTH          (0x0003FC00)
 395#define HWIB_INFO_START_ADDR    (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH)
 396#define HWIB_INFO_LEN           512
 397#define CIB_INFO_START_ADDR     (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN)
 398#define CIB_INFO_LEN            512
 399
 400#define CONFIG_SYS_HWINFO_OFFSET        0x3fc00 /* offset of HW Info block */
 401#define CONFIG_SYS_HWINFO_SIZE          0x00000060      /* size   of HW Info block */
 402#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38      /* 'TQM8' */
 403
 404/*-----------------------------------------------------------------------
 405 * NAND-FLASH stuff
 406 *-----------------------------------------------------------------------
 407 */
 408#if defined(CONFIG_CMD_NAND)
 409
 410#define CONFIG_SYS_NAND_CS_DIST         0x80
 411#define CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS       0x20
 412#define CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS      0x40
 413
 414#define CONFIG_SYS_NAND_BR      ((CONFIG_SYS_NAND0_BASE & BRx_BA_MSK)   |\
 415                         BRx_PS_8                       |\
 416                         BRx_MS_UPMB                    |\
 417                         BRx_V)
 418
 419#define CONFIG_SYS_NAND_OR      (MEG_TO_AM(CONFIG_SYS_NAND_SIZE)        |\
 420                         ORxU_BI                        |\
 421                         ORxU_EHTR_8IDLE)
 422
 423#define CONFIG_SYS_NAND_SIZE    1
 424#define CONFIG_SYS_NAND0_BASE 0x50000000
 425#define CONFIG_SYS_NAND1_BASE (CONFIG_SYS_NAND0_BASE + CONFIG_SYS_NAND_CS_DIST)
 426#define CONFIG_SYS_NAND2_BASE (CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST)
 427#define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST)
 428
 429#define CONFIG_SYS_MAX_NAND_DEVICE     4       /* Max number of NAND devices           */
 430
 431#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
 432                             CONFIG_SYS_NAND1_BASE, \
 433                             CONFIG_SYS_NAND2_BASE, \
 434                             CONFIG_SYS_NAND3_BASE, \
 435                           }
 436
 437#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr)) = (__u8)d; } while(0)
 438#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr)))
 439#define WRITE_NAND_UPM(d, adr, off) do \
 440{ \
 441        volatile unsigned char *addr = (unsigned char *) (adr + off); \
 442        WRITE_NAND(d, addr); \
 443} while(0)
 444
 445#endif /* CONFIG_CMD_NAND */
 446
 447#define CONFIG_PCI
 448#ifdef CONFIG_PCI
 449#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
 450#define CONFIG_PCI_PNP
 451#define CONFIG_EEPRO100
 452#define CONFIG_SYS_RX_ETH_BUFFER        8               /* use 8 rx buffer on eepro100  */
 453#define CONFIG_PCI_SCAN_SHOW
 454#endif
 455
 456/*-----------------------------------------------------------------------
 457 * Hard Reset Configuration Words
 458 *
 459 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 460 * defines for the various registers affected by the HRCW e.g. changing
 461 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 462 */
 463#if 0
 464#define __HRCW__ALL__           (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
 465
 466#  define CONFIG_SYS_HRCW_MASTER        (__HRCW__ALL__ | HRCW_MODCK_H0111)
 467#else
 468#define CONFIG_SYS_HRCW_MASTER  (HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111)
 469#endif
 470
 471/* no slaves so just fill with zeros */
 472#define CONFIG_SYS_HRCW_SLAVE1          0
 473#define CONFIG_SYS_HRCW_SLAVE2          0
 474#define CONFIG_SYS_HRCW_SLAVE3          0
 475#define CONFIG_SYS_HRCW_SLAVE4          0
 476#define CONFIG_SYS_HRCW_SLAVE5          0
 477#define CONFIG_SYS_HRCW_SLAVE6          0
 478#define CONFIG_SYS_HRCW_SLAVE7          0
 479
 480/*-----------------------------------------------------------------------
 481 * Internal Memory Mapped Register
 482 */
 483#define CONFIG_SYS_IMMR         0xFFF00000
 484
 485/*-----------------------------------------------------------------------
 486 * Definitions for initial stack pointer and data area (in DPRAM)
 487 */
 488#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 489#define CONFIG_SYS_INIT_RAM_END 0x2000  /* End of used area in DPRAM    */
 490#define CONFIG_SYS_GBL_DATA_SIZE        128 /* size in bytes reserved for initial data*/
 491#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 492#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 493
 494/*-----------------------------------------------------------------------
 495 * Start addresses for the final memory configuration
 496 * (Set up by the startup code)
 497 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 498 */
 499#define CONFIG_SYS_SDRAM_BASE           0x00000000
 500#define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_FLASH0_BASE
 501#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
 502#define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor */
 503#define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()*/
 504
 505/*
 506 * Internal Definitions
 507 *
 508 * Boot Flags
 509 */
 510#define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH*/
 511#define BOOTFLAG_WARM           0x02    /* Software reboot                 */
 512
 513/*-----------------------------------------------------------------------
 514 * Cache Configuration
 515 */
 516#define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 517#if defined(CONFIG_CMD_KGDB)
 518# define CONFIG_SYS_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 519#endif
 520
 521/*-----------------------------------------------------------------------
 522 * HIDx - Hardware Implementation-dependent Registers                    2-11
 523 *-----------------------------------------------------------------------
 524 * HID0 also contains cache control - initially enable both caches and
 525 * invalidate contents, then the final state leaves only the instruction
 526 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 527 * but Soft reset does not.
 528 *
 529 * HID1 has only read-only information - nothing to set.
 530 */
 531#define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 532                                HID0_IFEM|HID0_ABE)
 533#define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
 534#define CONFIG_SYS_HID2        0
 535
 536/*-----------------------------------------------------------------------
 537 * RMR - Reset Mode Register                                     5-5
 538 *-----------------------------------------------------------------------
 539 * turn on Checkstop Reset Enable
 540 */
 541#define CONFIG_SYS_RMR         RMR_CSRE
 542
 543/*-----------------------------------------------------------------------
 544 * BCR - Bus Configuration                                       4-25
 545 *-----------------------------------------------------------------------
 546 */
 547#define CONFIG_SYS_BCR_60x         (BCR_EBM|BCR_NPQM0|BCR_NPQM2)        /* 60x mode  */
 548#define BCR_APD01       0x10000000
 549#define CONFIG_SYS_BCR_SINGLE           (BCR_APD01|BCR_ETM)     /* 8260 mode */
 550
 551/*-----------------------------------------------------------------------
 552 * SIUMCR - SIU Module Configuration                             4-31
 553 *-----------------------------------------------------------------------
 554 */
 555#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
 556#define CONFIG_SYS_SIUMCR_LOW           (SIUMCR_DPPC00)
 557#define CONFIG_SYS_SIUMCR_HIGH          (SIUMCR_DPPC00 | SIUMCR_ABE)
 558#else
 559#define CONFIG_SYS_SIUMCR               (SIUMCR_DPPC00)
 560#endif
 561
 562/*-----------------------------------------------------------------------
 563 * SYPCR - System Protection Control                             4-35
 564 * SYPCR can only be written once after reset!
 565 *-----------------------------------------------------------------------
 566 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 567 */
 568#if defined(CONFIG_WATCHDOG)
 569#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 570                         SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 571#else
 572#define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 573                         SYPCR_SWRI|SYPCR_SWP)
 574#endif /* CONFIG_WATCHDOG */
 575
 576/*-----------------------------------------------------------------------
 577 * TMCNTSC - Time Counter Status and Control                     4-40
 578 *-----------------------------------------------------------------------
 579 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 580 * and enable Time Counter
 581 */
 582#define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 583
 584/*-----------------------------------------------------------------------
 585 * PISCR - Periodic Interrupt Status and Control                 4-42
 586 *-----------------------------------------------------------------------
 587 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 588 * Periodic timer
 589 */
 590#define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 591
 592/*-----------------------------------------------------------------------
 593 * SCCR - System Clock Control                                   9-8
 594 *-----------------------------------------------------------------------
 595 * Ensure DFBRG is Divide by 16
 596 */
 597#define CONFIG_SYS_SCCR        SCCR_DFBRG01
 598
 599/*-----------------------------------------------------------------------
 600 * RCCR - RISC Controller Configuration                         13-7
 601 *-----------------------------------------------------------------------
 602 */
 603#define CONFIG_SYS_RCCR        0
 604
 605/*
 606 * Init Memory Controller:
 607 *
 608 * Bank Bus     Machine PortSz  Device
 609 * ---- ---     ------- ------  ------
 610 *  0   60x     GPCM    32 bit  FLASH
 611 *  1   60x     SDRAM   64 bit  SDRAM
 612 *  2   60x     UPMB     8 bit  NAND
 613 *  3   60x     UPMC     8 bit  CAN
 614 *
 615 */
 616
 617/* Initialize SDRAM
 618         */
 619#undef CONFIG_SYS_INIT_LOCAL_SDRAM              /* No SDRAM on Local Bus */
 620
 621#define SDRAM_MAX_SIZE  0x20000000      /* max. 512 MB          */
 622
 623/* Minimum mask to separate preliminary
 624 * address ranges for CS[0:2]
 625 */
 626#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT   (512<<20)       /* less than 512 MB */
 627
 628#define CONFIG_SYS_MPTPR       0x4000
 629
 630/*-----------------------------------------------------------------------------
 631 * Address for Mode Register Set (MRS) command
 632 *-----------------------------------------------------------------------------
 633 * In fact, the address is rather configuration data presented to the SDRAM on
 634 * its address lines. Because the address lines may be mux'ed externally either
 635 * for 8 column or 9 column devices, some bits appear twice in the 8260's
 636 * address:
 637 *
 638 * |   (RFU)   |   (RFU)   | WBL |    TM    |     CL    |  BT | Burst Length |
 639 * | BA1   BA0 | A12 : A10 |  A9 |  A8   A7 |  A6 : A4  |  A3 |   A2 :  A0   |
 640 *  8 columns mux'ing:     |  A9 | A10  A21 | A22 : A24 | A25 |  A26 : A28   |
 641 *  9 columns mux'ing:     |  A8 | A20  A21 | A22 : A24 | A25 |  A26 : A28   |
 642 *  Settings:              |  0  |  0    0  |  0  1  0  |  0  |   0  1  0    |
 643 *-----------------------------------------------------------------------------
 644 */
 645#define CONFIG_SYS_MRS_OFFS     0x00000110
 646
 647/* Bank 0 - FLASH
 648 */
 649#define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
 650                         BRx_PS_32                      |\
 651                         BRx_MS_GPCM_P                  |\
 652                         BRx_V)
 653
 654#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
 655                         ORxG_CSNT                      |\
 656                         ORxG_ACS_DIV4                  |\
 657                         ORxG_SCY_8_CLK                 |\
 658                         ORxG_TRLX)
 659
 660/* SDRAM on TQM8272 can have either 8 or 9 columns.
 661 * The number affects configuration values.
 662 */
 663
 664/* Bank 1 - 60x bus SDRAM
 665 */
 666#define CONFIG_SYS_PSRT        0x20     /* Low Value */
 667/* #define CONFIG_SYS_PSRT        0x10   Fast Value */
 668#define CONFIG_SYS_LSRT        0x20     /* Local Bus */
 669#ifndef CONFIG_SYS_RAMBOOT
 670#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
 671                         BRx_PS_64                      |\
 672                         BRx_MS_SDRAM_P                 |\
 673                         BRx_V)
 674
 675#define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR1_8COL
 676
 677/* SDRAM initialization values for 8-column chips
 678 */
 679#define CONFIG_SYS_OR1_8COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 680                         ORxS_BPD_4                     |\
 681                         ORxS_ROWST_PBI1_A7             |\
 682                         ORxS_NUMR_12)
 683
 684#define CONFIG_SYS_PSDMR_8COL  (PSDMR_PBI                      |\
 685                         PSDMR_SDAM_A15_IS_A5           |\
 686                         PSDMR_BSMA_A12_A14             |\
 687                         PSDMR_SDA10_PBI1_A8            |\
 688                         PSDMR_RFRC_7_CLK               |\
 689                         PSDMR_PRETOACT_2W              |\
 690                         PSDMR_ACTTORW_2W               |\
 691                         PSDMR_LDOTOPRE_1C              |\
 692                         PSDMR_WRC_2C                   |\
 693                         PSDMR_EAMUX                    |\
 694                         PSDMR_BUFCMD                   |\
 695                         PSDMR_CL_2)
 696
 697
 698/* SDRAM initialization values for 9-column chips
 699 */
 700#define CONFIG_SYS_OR1_9COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 701                         ORxS_BPD_4                     |\
 702                         ORxS_ROWST_PBI1_A5             |\
 703                         ORxS_NUMR_13)
 704
 705#define CONFIG_SYS_PSDMR_9COL  (PSDMR_PBI                      |\
 706                         PSDMR_SDAM_A16_IS_A5           |\
 707                         PSDMR_BSMA_A12_A14             |\
 708                         PSDMR_SDA10_PBI1_A7            |\
 709                         PSDMR_RFRC_7_CLK               |\
 710                         PSDMR_PRETOACT_2W              |\
 711                         PSDMR_ACTTORW_2W               |\
 712                         PSDMR_LDOTOPRE_1C              |\
 713                         PSDMR_WRC_2C                   |\
 714                         PSDMR_EAMUX                    |\
 715                         PSDMR_BUFCMD                   |\
 716                         PSDMR_CL_2)
 717
 718#define CONFIG_SYS_OR1_10COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 719                         ORxS_BPD_4                     |\
 720                         ORxS_ROWST_PBI1_A4             |\
 721                         ORxS_NUMR_13)
 722
 723#define CONFIG_SYS_PSDMR_10COL  (PSDMR_PBI                      |\
 724                         PSDMR_SDAM_A17_IS_A5           |\
 725                         PSDMR_BSMA_A12_A14             |\
 726                         PSDMR_SDA10_PBI1_A4            |\
 727                         PSDMR_RFRC_6_CLK               |\
 728                         PSDMR_PRETOACT_2W              |\
 729                         PSDMR_ACTTORW_2W               |\
 730                         PSDMR_LDOTOPRE_1C              |\
 731                         PSDMR_WRC_2C                   |\
 732                         PSDMR_EAMUX                    |\
 733                         PSDMR_BUFCMD                   |\
 734                         PSDMR_CL_2)
 735
 736#define PSDMR_RFRC_66MHZ_SINGLE         0x00028000  /* PSDMR[RFRC] at 66 MHz single mode */
 737#define PSDMR_RFRC_100MHZ_SINGLE        0x00030000  /* PSDMR[RFRC] at 100 MHz single mode */
 738#define PSDMR_RFRC_133MHZ_SINGLE        0x00030000  /* PSDMR[RFRC] at 133 MHz single mode */
 739#define PSDMR_RFRC_66MHZ_60X            0x00030000  /* PSDMR[RFRC] at 66 MHz 60x mode */
 740#define PSDMR_RFRC_100MHZ_60X           0x00028000  /* PSDMR[RFRC] at 100 MHz 60x mode */
 741#define PSDMR_RFRC_DEFAULT              PSDMR_RFRC_133MHZ_SINGLE  /* PSDMR[RFRC] default value */
 742
 743#define PSDMR_PRETOACT_66MHZ_SINGLE     0x00002000  /* PSDMR[PRETOACT] at 66 MHz single mode */
 744#define PSDMR_PRETOACT_100MHZ_SINGLE    0x00002000  /* PSDMR[PRETOACT] at 100 MHz single mode */
 745#define PSDMR_PRETOACT_133MHZ_SINGLE    0x00002000  /* PSDMR[PRETOACT] at 133 MHz single mode */
 746#define PSDMR_PRETOACT_66MHZ_60X        0x00001000  /* PSDMR[PRETOACT] at 66 MHz 60x mode */
 747#define PSDMR_PRETOACT_100MHZ_60X       0x00001000  /* PSDMR[PRETOACT] at 100 MHz 60x mode */
 748#define PSDMR_PRETOACT_DEFAULT          PSDMR_PRETOACT_133MHZ_SINGLE  /* PSDMR[PRETOACT] default value */
 749
 750#define PSDMR_WRC_66MHZ_SINGLE          0x00000020  /* PSDMR[WRC] at 66 MHz single mode */
 751#define PSDMR_WRC_100MHZ_SINGLE         0x00000020  /* PSDMR[WRC] at 100 MHz single mode */
 752#define PSDMR_WRC_133MHZ_SINGLE         0x00000010  /* PSDMR[WRC] at 133 MHz single mode */
 753#define PSDMR_WRC_66MHZ_60X             0x00000010  /* PSDMR[WRC] at 66 MHz 60x mode */
 754#define PSDMR_WRC_100MHZ_60X            0x00000010  /* PSDMR[WRC] at 100 MHz 60x mode */
 755#define PSDMR_WRC_DEFAULT               PSDMR_WRC_133MHZ_SINGLE  /* PSDMR[WRC] default value */
 756
 757#define PSDMR_BUFCMD_66MHZ_SINGLE       0x00000000  /* PSDMR[BUFCMD] at 66 MHz single mode */
 758#define PSDMR_BUFCMD_100MHZ_SINGLE      0x00000000  /* PSDMR[BUFCMD] at 100 MHz single mode */
 759#define PSDMR_BUFCMD_133MHZ_SINGLE      0x00000004  /* PSDMR[BUFCMD] at 133 MHz single mode */
 760#define PSDMR_BUFCMD_66MHZ_60X          0x00000000  /* PSDMR[BUFCMD] at 66 MHz 60x mode */
 761#define PSDMR_BUFCMD_100MHZ_60X         0x00000000  /* PSDMR[BUFCMD] at 100 MHz 60x mode */
 762#define PSDMR_BUFCMD_DEFAULT            PSDMR_BUFCMD_133MHZ_SINGLE  /* PSDMR[BUFCMD] default value */
 763
 764#endif /* CONFIG_SYS_RAMBOOT */
 765
 766#endif  /* __CONFIG_H */
 767