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27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31#define CONFIG_ARIA 1
32
33
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41
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44
45
46
47
48
49#define CONFIG_E300 1
50#define CONFIG_MPC512X 1
51#define CONFIG_FSL_DIU_FB 1
52#define CONFIG_FSL_DIU_LOGO_BMP 1
53
54
55#undef CONFIG_VIDEO
56
57#if defined(CONFIG_VIDEO)
58#define CONFIG_CFB_CONSOLE
59#define CONFIG_VGA_AS_SINGLE_DEVICE
60#endif
61
62
63
64#define CONFIG_SYS_MPC512X_CLKIN 33000000
65
66#define CONFIG_BOARD_EARLY_INIT_F
67#define CONFIG_MISC_INIT_R
68
69#define CONFIG_SYS_IMMR 0x80000000
70#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100)
71
72#define CONFIG_SYS_MEMTEST_START 0x00200000
73#define CONFIG_SYS_MEMTEST_END 0x00400000
74
75
76
77
78#define CONFIG_SYS_DDR_SIZE 256
79#define CONFIG_SYS_DDR_BASE 0x00000000
80#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
81#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
82
83#define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036
84
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127
128
129#define CONFIG_SYS_MDDRC_SYS_CFG ( (1 << 31) | \
130 (1 << 30) | \
131 (1 << 29) | \
132 (0 << 28) | \
133 (4 << 25) | \
134 (3 << 21) | \
135 (0 << 18) | \
136 (0 << 17) | \
137 (2 << 13) | \
138 (0 << 12) | \
139 (1 << 11) | \
140 (2 << 8) | \
141 (0 << 7) | \
142 (1 << 6) | \
143 (0 << 5) | \
144 (0 << 4) | \
145 (0 << 1) | \
146 (0 << 0) \
147 )
148
149#define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E
150#define CONFIG_SYS_MDDRC_TIME_CFG1 0x55D81189
151#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34790863
152
153#define CONFIG_SYS_DDRCMD_NOP 0x01380000
154#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
155#define CONFIG_SYS_MICRON_EMR ( (1 << 24) | \
156 (0 << 22) | \
157 (0 << 21) | \
158 (0 << 20) | \
159 (0 << 19) | \
160 (1 << 16) | \
161 (0 << 15) | \
162 (0 << 12) | \
163 (0 << 11) | \
164 (0 << 10) | \
165 (0 << 7) | \
166 (0 << 6) | \
167 (0 << 3) | \
168 (0 << 2) | \
169 (1 << 1) | \
170 (0 << 0) \
171 )
172#define CONFIG_SYS_MICRON_EMR2 0x01020000
173#define CONFIG_SYS_MICRON_EMR3 0x01030000
174#define CONFIG_SYS_DDRCMD_RFSH 0x01080000
175#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
176#define CONFIG_SYS_MICRON_EMR_OCD ( (1 << 24) | \
177 (0 << 22) | \
178 (0 << 21) | \
179 (0 << 20) | \
180 (0 << 19) | \
181 (1 << 16) | \
182 (0 << 15) | \
183 (0 << 12) | \
184 (0 << 11) | \
185 (1 << 10) | \
186 (7 << 7) | \
187 (0 << 6) | \
188 (0 << 3) | \
189 (1 << 2) | \
190 (0 << 1) | \
191 (0 << 0) \
192 )
193
194
195
196
197
198#define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2)
199#define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3)
200#define CONFIG_SYS_DDRCMD_EN_DLL (CONFIG_SYS_MICRON_EMR)
201#define CONFIG_SYS_DDRCMD_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD)
202
203
204#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
205#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000
206#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001
207#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC
208#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA
209#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666
210#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555
211#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444
212#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444
213#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555
214#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558
215#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111
216#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122
217#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa
218#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa
219#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666
220#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666
221#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111
222#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111
223#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111
224#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111
225#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111
226#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111
227
228
229
230
231#define CONFIG_SYS_FLASH_CFI
232#define CONFIG_FLASH_CFI_DRIVER
233#define CONFIG_SYS_FLASH_BASE 0xF8000000
234#define CONFIG_SYS_FLASH_SIZE 0x08000000
235
236#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
237#define CONFIG_SYS_MAX_FLASH_BANKS 1
238#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
239#define CONFIG_SYS_MAX_FLASH_SECT 1024
240
241#undef CONFIG_SYS_FLASH_CHECKSUM
242
243
244
245
246
247#define CONFIG_CMD_NAND
248#define CONFIG_JFFS2_NAND
249
250
251#define CONFIG_NAND_MPC5121_NFC
252#define CONFIG_SYS_NAND_BASE 0x40000000
253
254#define CONFIG_SYS_MAX_NAND_DEVICE 1
255#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
256
257
258
259
260#define CONFIG_FSL_NFC_WIDTH 1
261#define CONFIG_FSL_NFC_WRITE_SIZE 2048
262#define CONFIG_FSL_NFC_SPARE_SIZE 64
263#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
264
265#define CONFIG_SYS_SRAM_BASE 0x30000000
266#define CONFIG_SYS_SRAM_SIZE 0x00020000
267
268
269#define CONFIG_SYS_ARIA_SRAM_BASE (CONFIG_SYS_SRAM_BASE + \
270 CONFIG_SYS_SRAM_SIZE)
271#define CONFIG_SYS_ARIA_SRAM_SIZE 0x00100000
272
273#define CONFIG_SYS_ARIA_FPGA_BASE (CONFIG_SYS_ARIA_SRAM_BASE + \
274 CONFIG_SYS_ARIA_SRAM_SIZE)
275#define CONFIG_SYS_ARIA_FPGA_SIZE 0x20000
276
277#define CONFIG_SYS_CS0_CFG 0x05059150
278#define CONFIG_SYS_CS2_CFG ( (5 << 24) | \
279 (5 << 16) | \
280 (1 << 15) | \
281 (0 << 14) | \
282 (0 << 13) | \
283 (1 << 12) | \
284 (0 << 10) | \
285 (3 << 8) | \
286 (0 << 7) | \
287 (1 << 6) | \
288 (1 << 4) | \
289 (0 << 3) | \
290 (0 << 2) | \
291 (0 << 1) | \
292 (0 << 0) \
293 )
294#define CONFIG_SYS_CS6_CFG 0x05059150
295
296
297#define CONFIG_SYS_CS_ALETIMING 0x00000005
298
299
300#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE
301#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE
302
303#define CONFIG_SYS_GBL_DATA_SIZE 0x100
304#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
305 CONFIG_SYS_GBL_DATA_SIZE)
306#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
307
308#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
309#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
310
311#ifdef CONFIG_FSL_DIU_FB
312#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
313#else
314#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
315#endif
316
317
318#define CONFIG_ARIA_FPGA 1
319
320
321
322
323#define CONFIG_CONS_INDEX 1
324#undef CONFIG_SERIAL_SOFTWARE_FIFO
325
326
327
328
329#define CONFIG_PSC_CONSOLE 3
330#if CONFIG_PSC_CONSOLE != 3
331#error CONFIG_PSC_CONSOLE must be 3
332#endif
333
334#define CONFIG_BAUDRATE 115200
335#define CONFIG_SYS_BAUDRATE_TABLE \
336 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
337
338#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE
339#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR
340#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
341#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
342
343#define CONFIG_CMDLINE_EDITING 1
344
345#define CONFIG_SYS_HUSH_PARSER
346#ifdef CONFIG_SYS_HUSH_PARSER
347#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
348#endif
349
350
351
352
353#ifdef CONFIG_PCI
354
355#define CONFIG_SYS_PCI_MEM_BASE 0xA0000000
356#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
357#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
358#define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + \
359 CONFIG_SYS_PCI_MEM_SIZE)
360#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
361#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000
362#define CONFIG_SYS_PCI_IO_BASE 0x00000000
363#define CONFIG_SYS_PCI_IO_PHYS 0x84000000
364#define CONFIG_SYS_PCI_IO_SIZE 0x01000000
365
366#define CONFIG_PCI_PNP
367
368#define CONFIG_PCI_SCAN_SHOW
369
370#endif
371
372
373#define CONFIG_HARD_I2C
374#undef CONFIG_SOFT_I2C
375#define CONFIG_I2C_MULTI_BUS
376
377
378#define CONFIG_SYS_I2C_SPEED 100000
379#define CONFIG_SYS_I2C_SLAVE 0x7F
380#if 0
381#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}}
382#endif
383
384
385
386
387#undef CONFIG_IIM
388
389
390
391
392
393#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
394#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
395#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
396#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
397
398
399
400
401#define CONFIG_MPC512x_FEC 1
402#define CONFIG_NET_MULTI
403#define CONFIG_PHY_ADDR 0x17
404#define CONFIG_MII 1
405#define CONFIG_FEC_AN_TIMEOUT 1
406#define CONFIG_HAS_ETH0
407
408
409
410
411#define CONFIG_ENV_IS_IN_FLASH 1
412
413#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
414 CONFIG_SYS_MONITOR_LEN)
415#define CONFIG_ENV_SIZE 0x2000
416#define CONFIG_ENV_SECT_SIZE 0x20000
417
418
419#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
420 CONFIG_ENV_SECT_SIZE)
421#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
422
423#define CONFIG_LOADS_ECHO 1
424#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
425
426#include <config_cmd_default.h>
427
428#define CONFIG_CMD_ASKENV
429#define CONFIG_CMD_DHCP
430#define CONFIG_CMD_EEPROM
431#undef CONFIG_CMD_FUSE
432#define CONFIG_CMD_I2C
433#undef CONFIG_CMD_IDE
434#define CONFIG_CMD_JFFS2
435#define CONFIG_CMD_MII
436#define CONFIG_CMD_NFS
437#define CONFIG_CMD_PING
438#define CONFIG_CMD_REGINFO
439
440#if defined(CONFIG_PCI)
441#define CONFIG_CMD_PCI
442#endif
443
444#if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2)
445#define CONFIG_DOS_PARTITION
446#define CONFIG_MAC_PARTITION
447#define CONFIG_ISO_PARTITION
448#endif
449
450
451
452
453#define CONFIG_CMD_MTDPARTS
454#define CONFIG_MTD_DEVICE
455#define CONFIG_FLASH_CFI_MTD
456#define MTDIDS_DEFAULT "nor0=f8000000.flash,nand0=mpc5121.nand"
457
458
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466
467
468
469#define MTDPARTS_DEFAULT "mtdparts=f8000000.flash:107m(user)," \
470 "16m(rootfs)," \
471 "4m(kernel)," \
472 "768k(u-boot)," \
473 "256k(dtb);" \
474 "mpc5121.nand:-(data)"
475
476
477
478
479
480
481
482
483#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
484
485
486
487
488#define CONFIG_SYS_LONGHELP
489#define CONFIG_SYS_LOAD_ADDR 0x2000000
490#define CONFIG_SYS_PROMPT "=> "
491
492#ifdef CONFIG_CMD_KGDB
493# define CONFIG_SYS_CBSIZE 1024
494#else
495# define CONFIG_SYS_CBSIZE 256
496#endif
497
498
499#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
500 sizeof(CONFIG_SYS_PROMPT) + 16)
501
502#define CONFIG_SYS_MAXARGS 32
503
504#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
505
506#define CONFIG_SYS_HZ 1000
507
508
509
510
511
512
513#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
514
515
516#define CONFIG_SYS_DCACHE_SIZE 32768
517#define CONFIG_SYS_CACHELINE_SIZE 32
518#ifdef CONFIG_CMD_KGDB
519#define CONFIG_SYS_CACHELINE_SHIFT 5
520#endif
521
522#define CONFIG_SYS_HID0_INIT 0x000000000
523#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
524 HID0_ICE)
525#define CONFIG_SYS_HID2 HID2_HBE
526
527#define CONFIG_HIGH_BATS 1
528
529
530
531
532
533
534#define BOOTFLAG_COLD 0x01
535#define BOOTFLAG_WARM 0x02
536
537#ifdef CONFIG_CMD_KGDB
538#define CONFIG_KGDB_BAUDRATE 230400
539#define CONFIG_KGDB_SER_INDEX 2
540#endif
541
542
543
544
545#define CONFIG_ENV_OVERWRITE
546#define CONFIG_TIMESTAMP
547
548#define CONFIG_HOSTNAME aria
549#define CONFIG_BOOTFILE aria/uImage
550#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx
551
552#define CONFIG_LOADADDR 400000
553
554#define CONFIG_BOOTDELAY 5
555#undef CONFIG_BOOTARGS
556
557#define CONFIG_BAUDRATE 115200
558
559#define CONFIG_PREBOOT "echo;" \
560 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
561 "echo"
562
563#define CONFIG_EXTRA_ENV_SETTINGS \
564 "u-boot_addr_r=200000\0" \
565 "kernel_addr_r=600000\0" \
566 "fdt_addr_r=880000\0" \
567 "ramdisk_addr_r=900000\0" \
568 "u-boot_addr=FFF00000\0" \
569 "kernel_addr=FFB00000\0" \
570 "fdt_addr=FFFC0000\0" \
571 "ramdisk_addr=FEB00000\0" \
572 "ramdiskfile=aria/uRamdisk\0" \
573 "u-boot=aria/u-boot.bin\0" \
574 "fdtfile=aria/aria.dtb\0" \
575 "netdev=eth0\0" \
576 "consdev=ttyPSC0\0" \
577 "nfsargs=setenv bootargs root=/dev/nfs rw " \
578 "nfsroot=${serverip}:${rootpath}\0" \
579 "ramargs=setenv bootargs root=/dev/ram rw\0" \
580 "addip=setenv bootargs ${bootargs} " \
581 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
582 ":${hostname}:${netdev}:off panic=1\0" \
583 "addtty=setenv bootargs ${bootargs} " \
584 "console=${consdev},${baudrate}\0" \
585 "flash_nfs=run nfsargs addip addtty;" \
586 "bootm ${kernel_addr} - ${fdt_addr}\0" \
587 "flash_self=run ramargs addip addtty;" \
588 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
589 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
590 "tftp ${fdt_addr_r} ${fdtfile};" \
591 "run nfsargs addip addtty;" \
592 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
593 "net_self=tftp ${kernel_addr_r} ${bootfile};" \
594 "tftp ${ramdisk_addr_r} ${ramdiskfile};" \
595 "tftp ${fdt_addr_r} ${fdtfile};" \
596 "run ramargs addip addtty;" \
597 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
598 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
599 "update=protect off ${u-boot_addr} +${filesize};" \
600 "era ${u-boot_addr} +${filesize};" \
601 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \
602 "upd=run load update\0" \
603 ""
604
605#define CONFIG_BOOTCOMMAND "run flash_self"
606
607#define CONFIG_OF_LIBFDT 1
608#define CONFIG_OF_BOARD_SETUP 1
609#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1
610
611#define OF_CPU "PowerPC,5121@0"
612#define OF_SOC_COMPAT "fsl,mpc5121-immr"
613#define OF_TBCLK (bd->bi_busfreq / 4)
614#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
615
616
617
618
619
620
621#undef CONFIG_IDE_8xx_PCCARD
622#undef CONFIG_IDE_8xx_DIRECT
623#undef CONFIG_IDE_LED
624
625#define CONFIG_IDE_RESET
626#define CONFIG_IDE_PREINIT
627
628#define CONFIG_SYS_IDE_MAXBUS 1
629#define CONFIG_SYS_IDE_MAXDEVICE 2
630
631#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
632#define CONFIG_SYS_ATA_BASE_ADDR get_pata_base()
633
634
635#define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0)
636
637
638#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
639
640
641#define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8)
642
643
644#define CONFIG_SYS_ATA_STRIDE 4
645
646#define ATA_BASE_ADDR get_pata_base()
647
648
649
650
651#define FSL_ATA_CTRL_FIFO_RST_B 0x80000000
652#define FSL_ATA_CTRL_ATA_RST_B 0x40000000
653#define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000
654#define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000
655#define FSL_ATA_CTRL_DMA_PENDING 0x08000000
656#define FSL_ATA_CTRL_DMA_ULTRA 0x04000000
657#define FSL_ATA_CTRL_DMA_WRITE 0x02000000
658#define FSL_ATA_CTRL_IORDY_EN 0x01000000
659
660#endif
661