LXR uboot/include/configs/kilauea.h

   1/*
   2 * Copyright (c) 2008 Nuovation System Designs, LLC
   3 *   Grant Erickson <gerickson@nuovations.com>
   4 *
   5 * (C) Copyright 2007
   6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7 *
   8 * See file CREDITS for list of people who contributed to this
   9 * project.
  10 *
  11 * This program is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU General Public License as
  13 * published by the Free Software Foundation; either version 2 of
  14 * the License, or (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 * MA 02111-1307 USA
  25 */
  26
  27/************************************************************************
  28 * kilauea.h - configuration for AMCC Kilauea (405EX)
  29 ***********************************************************************/
  30
  31#ifndef __CONFIG_H
  32#define __CONFIG_H
  33
  34/*-----------------------------------------------------------------------
  35 * High Level Configuration Options
  36 *----------------------------------------------------------------------*/
  37#define CONFIG_KILAUEA          1               /* Board is Kilauea     */
  38#define CONFIG_4xx              1               /* ... PPC4xx family    */
  39#define CONFIG_405EX            1               /* Specifc 405EX support*/
  40#define CONFIG_SYS_CLK_FREQ     33333333        /* ext frequency to pll */
  41
  42/*
  43 * Include common defines/options for all AMCC eval boards
  44 */
  45#define CONFIG_HOSTNAME         kilauea
  46#include "amcc-common.h"
  47
  48#define CONFIG_BOARD_EARLY_INIT_F 1             /* Call board_early_init_f */
  49#define CONFIG_MISC_INIT_R      1               /* Call misc_init_r     */
  50#define CONFIG_BOARD_TYPES
  51#define CONFIG_BOARD_EMAC_COUNT
  52
  53/*-----------------------------------------------------------------------
  54 * Base addresses -- Note these are effective addresses where the
  55 * actual resources get mapped (not physical addresses)
  56 *----------------------------------------------------------------------*/
  57#define CONFIG_SYS_FLASH_BASE           0xFC000000
  58#define CONFIG_SYS_NAND_ADDR            0xF8000000
  59#define CONFIG_SYS_FPGA_BASE            0xF0000000
  60#define CONFIG_SYS_PERIPHERAL_BASE      0xEF600000      /* internal peripherals*/
  61
  62/*-----------------------------------------------------------------------
  63 * Initial RAM & Stack Pointer Configuration Options
  64 *
  65 *   There are traditionally three options for the primordial
  66 *   (i.e. initial) stack usage on the 405-series:
  67 *
  68 *      1) On-chip Memory (OCM) (i.e. SRAM)
  69 *      2) Data cache
  70 *      3) SDRAM
  71 *
  72 *   For the 405EX(r), there is no OCM, so we are left with (2) or (3)
  73 *   the latter of which is less than desireable since it requires
  74 *   setting up the SDRAM and ECC in assembly code.
  75 *
  76 *   To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
  77 *   select on the External Bus Controller (EBC) and then select a
  78 *   value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
  79 *   physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
  80 *   select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
  81 *   physical SDRAM to use (3).
  82 *-----------------------------------------------------------------------*/
  83
  84#define CONFIG_SYS_INIT_DCACHE_CS       4
  85
  86#if defined(CONFIG_SYS_INIT_DCACHE_CS)
  87#define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_SDRAM_BASE + ( 1 << 30))    /*  1 GiB */
  88#else
  89#define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_SDRAM_BASE + (32 << 20))    /* 32 MiB */
  90#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
  91
  92#define CONFIG_SYS_INIT_RAM_END        (4 << 10)                        /*  4 KiB */
  93#define CONFIG_SYS_GBL_DATA_SIZE        256             /* num bytes initial data */
  94#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  95
  96/*
  97 * If the data cache is being used for the primordial stack and global
  98 * data area, the POST word must be placed somewhere else. The General
  99 * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
 100 * its compare and mask register contents across reset, so it is used
 101 * for the POST word.
 102 */
 103
 104#if defined(CONFIG_SYS_INIT_DCACHE_CS)
 105# define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 106# define CONFIG_SYS_POST_WORD_ADDR      (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
 107#else
 108# define CONFIG_SYS_INIT_EXTRA_SIZE     16
 109# define CONFIG_SYS_INIT_SP_OFFSET      (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
 110# define CONFIG_SYS_OCM_DATA_ADDR       CONFIG_SYS_INIT_RAM_ADDR
 111#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
 112
 113/*-----------------------------------------------------------------------
 114 * Serial Port
 115 *----------------------------------------------------------------------*/
 116#define CONFIG_SYS_EXT_SERIAL_CLOCK     11059200        /* ext. 11.059MHz clk   */
 117/* define this if you want console on UART1 */
 118#undef CONFIG_UART1_CONSOLE
 119
 120/*-----------------------------------------------------------------------
 121 * Environment
 122 *----------------------------------------------------------------------*/
 123#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 124#define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
 125#else
 126#define CONFIG_ENV_IS_IN_NAND   1       /* use NAND for environment vars        */
 127#define CONFIG_ENV_IS_EMBEDDED  1       /* use embedded environment */
 128#endif
 129
 130/*-----------------------------------------------------------------------
 131 * FLASH related
 132 *----------------------------------------------------------------------*/
 133#define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible  */
 134#define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 135
 136#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
 137#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 138#define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 139
 140#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 141#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 142
 143#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 144#define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 145
 146#ifdef CONFIG_ENV_IS_IN_FLASH
 147#define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector  */
 148#define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 149#define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 150
 151/* Address and size of Redundant Environment Sector     */
 152#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 153#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 154#endif /* CONFIG_ENV_IS_IN_FLASH */
 155
 156/*
 157 * IPL (Initial Program Loader, integrated inside CPU)
 158 * Will load first 4k from NAND (SPL) into cache and execute it from there.
 159 *
 160 * SPL (Secondary Program Loader)
 161 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
 162 * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
 163 * controller and the NAND controller so that the special U-Boot image can be
 164 * loaded from NAND to SDRAM.
 165 *
 166 * NUB (NAND U-Boot)
 167 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
 168 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
 169 *
 170 * On 405EX the SPL is copied to SDRAM before the NAND controller is
 171 * set up. While still running from location 0xfffff000...0xffffffff the
 172 * NAND controller cannot be accessed since it is attached to CS0 too.
 173 */
 174#define CONFIG_SYS_NAND_BOOT_SPL_SRC    0xfffff000      /* SPL location                 */
 175#define CONFIG_SYS_NAND_BOOT_SPL_SIZE   (4 << 10)       /* SPL size                     */
 176#define CONFIG_SYS_NAND_BOOT_SPL_DST    0x00800000      /* Copy SPL here                */
 177#define CONFIG_SYS_NAND_U_BOOT_DST      0x01000000      /* Load NUB to this addr        */
 178#define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr  */
 179#define CONFIG_SYS_NAND_BOOT_SPL_DELTA  (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
 180
 181/*
 182 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
 183 */
 184#define CONFIG_SYS_NAND_U_BOOT_OFFS     (16 << 10)      /* Offset to RAM U-Boot image   */
 185#define CONFIG_SYS_NAND_U_BOOT_SIZE     (384 << 10)     /* Size of RAM U-Boot image     */
 186
 187/*
 188 * Now the NAND chip has to be defined (no autodetection used!)
 189 */
 190#define CONFIG_SYS_NAND_PAGE_SIZE       512             /* NAND chip page size          */
 191#define CONFIG_SYS_NAND_BLOCK_SIZE      (16 << 10)      /* NAND chip block size         */
 192#define CONFIG_SYS_NAND_PAGE_COUNT      32              /* NAND chip page count         */
 193#define CONFIG_SYS_NAND_BAD_BLOCK_POS   5               /* Location of bad block marker */
 194#define CONFIG_SYS_NAND_4_ADDR_CYCLE    1               /* Fourth addr used (>32MB)     */
 195
 196#define CONFIG_SYS_NAND_ECCSIZE 256
 197#define CONFIG_SYS_NAND_ECCBYTES        3
 198#define CONFIG_SYS_NAND_ECCSTEPS        (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
 199#define CONFIG_SYS_NAND_OOBSIZE 16
 200#define CONFIG_SYS_NAND_ECCTOTAL        (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
 201#define CONFIG_SYS_NAND_ECCPOS          {0, 1, 2, 3, 6, 7}
 202
 203#ifdef CONFIG_ENV_IS_IN_NAND
 204/*
 205 * For NAND booting the environment is embedded in the U-Boot image. Please take
 206 * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
 207 */
 208#define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 209#define CONFIG_ENV_OFFSET               (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
 210#define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 211#endif
 212
 213/*-----------------------------------------------------------------------
 214 * NAND FLASH
 215 *----------------------------------------------------------------------*/
 216#define CONFIG_SYS_MAX_NAND_DEVICE      1
 217#define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 218#define CONFIG_SYS_NAND_SELECT_DEVICE  1        /* nand driver supports mutipl. chips   */
 219
 220/*-----------------------------------------------------------------------
 221 * DDR SDRAM
 222 *----------------------------------------------------------------------*/
 223#define CONFIG_SYS_MBYTES_SDRAM        (256)            /* 256MB                        */
 224
 225/*
 226 * CONFIG_PPC4xx_DDR_AUTOCALIBRATION
 227 *
 228 * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
 229 *       SDRAM Controller DDR autocalibration values and takes a lot longer
 230 *       to run than Method_B.
 231 * (See the Method_A and Method_B algorithm discription in the file:
 232 *      arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
 233 * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
 234 *
 235 * DDR Autocalibration Method_B is the default.
 236 */
 237#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 238#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION       /* IBM DDR autocalibration */
 239#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION        /* dynamic DDR autocal debug */
 240#undef  CONFIG_PPC4xx_DDR_METHOD_A
 241#endif
 242
 243#define CONFIG_SYS_SDRAM0_MB0CF_BASE    ((  0 << 20) + CONFIG_SYS_SDRAM_BASE)
 244
 245/* DDR1/2 SDRAM Device Control Register Data Values */
 246#define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3)    | \
 247                                 SDRAM_RXBAS_SDSZ_256MB         | \
 248                                 SDRAM_RXBAS_SDAM_MODE7         | \
 249                                 SDRAM_RXBAS_SDBE_ENABLE)
 250#define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
 251#define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
 252#define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
 253#define CONFIG_SYS_SDRAM0_MCOPT1        (SDRAM_MCOPT1_PMU_OPEN          | \
 254                                 SDRAM_MCOPT1_8_BANKS           | \
 255                                 SDRAM_MCOPT1_DDR2_TYPE         | \
 256                                 SDRAM_MCOPT1_QDEP              | \
 257                                 SDRAM_MCOPT1_DCOO_DISABLED)
 258#define CONFIG_SYS_SDRAM0_MCOPT2        0x00000000
 259#define CONFIG_SYS_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \
 260                                 SDRAM_MODT_EB0R_ENABLE)
 261#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
 262#define CONFIG_SYS_SDRAM0_CODT          (SDRAM_CODT_RK0R_ON             | \
 263                                 SDRAM_CODT_CKLZ_36OHM          | \
 264                                 SDRAM_CODT_DQS_1_8_V_DDR2      | \
 265                                 SDRAM_CODT_IO_NMODE)
 266#define CONFIG_SYS_SDRAM0_RTR           SDRAM_RTR_RINT_ENCODE(1560)
 267#define CONFIG_SYS_SDRAM0_INITPLR0      (SDRAM_INITPLR_ENABLE                   | \
 268                SDRAM_INITPLR_IMWT_ENCODE(80)                           | \
 269                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
 270#define CONFIG_SYS_SDRAM0_INITPLR1      (SDRAM_INITPLR_ENABLE                   | \
 271                SDRAM_INITPLR_IMWT_ENCODE(3)                            | \
 272                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)          | \
 273                SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                   | \
 274                SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
 275#define CONFIG_SYS_SDRAM0_INITPLR2      (SDRAM_INITPLR_ENABLE                   | \
 276                SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 277                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 278                SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2)                 | \
 279                SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
 280#define CONFIG_SYS_SDRAM0_INITPLR3      (SDRAM_INITPLR_ENABLE                   | \
 281                SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 282                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 283                SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3)                 | \
 284                SDRAM_INITPLR_IMA_ENCODE(0))
 285#define CONFIG_SYS_SDRAM0_INITPLR4      (SDRAM_INITPLR_ENABLE                   | \
 286                SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 287                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 288                SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                  | \
 289                SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
 290                                         JEDEC_MA_EMR_RTT_75OHM))
 291#define CONFIG_SYS_SDRAM0_INITPLR5      (SDRAM_INITPLR_ENABLE                   | \
 292                SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 293                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 294                SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                   | \
 295                SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
 296                                         JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
 297                                         JEDEC_MA_MR_BLEN_4 | \
 298                                         JEDEC_MA_MR_DLL_RESET))
 299#define CONFIG_SYS_SDRAM0_INITPLR6      (SDRAM_INITPLR_ENABLE                   | \
 300                SDRAM_INITPLR_IMWT_ENCODE(3)                            | \
 301                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)          | \
 302                SDRAM_INITPLR_IBA_ENCODE(0x0)                           | \
 303                SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
 304#define CONFIG_SYS_SDRAM0_INITPLR7      (SDRAM_INITPLR_ENABLE                   | \
 305                SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
 306                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 307#define CONFIG_SYS_SDRAM0_INITPLR8      (SDRAM_INITPLR_ENABLE                   | \
 308                SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
 309                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 310#define CONFIG_SYS_SDRAM0_INITPLR9      (SDRAM_INITPLR_ENABLE                   | \
 311                SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
 312                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 313#define CONFIG_SYS_SDRAM0_INITPLR10     (SDRAM_INITPLR_ENABLE                   | \
 314                SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
 315                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 316#define CONFIG_SYS_SDRAM0_INITPLR11     (SDRAM_INITPLR_ENABLE                   | \
 317                SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 318                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 319                SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                   | \
 320                SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
 321                                         JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
 322                                         JEDEC_MA_MR_BLEN_4))
 323#define CONFIG_SYS_SDRAM0_INITPLR12     (SDRAM_INITPLR_ENABLE                   | \
 324                SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 325                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 326                SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                  | \
 327                SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
 328                                         JEDEC_MA_EMR_RDQS_DISABLE | \
 329                                         JEDEC_MA_EMR_DQS_DISABLE | \
 330                                         JEDEC_MA_EMR_RTT_DISABLED | \
 331                                         JEDEC_MA_EMR_ODS_NORMAL))
 332#define CONFIG_SYS_SDRAM0_INITPLR13     (SDRAM_INITPLR_ENABLE                   | \
 333                SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 334                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 335                SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                  | \
 336                SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
 337                                         JEDEC_MA_EMR_RDQS_DISABLE | \
 338                                         JEDEC_MA_EMR_DQS_DISABLE | \
 339                                         JEDEC_MA_EMR_RTT_DISABLED | \
 340                                         JEDEC_MA_EMR_ODS_NORMAL))
 341#define CONFIG_SYS_SDRAM0_INITPLR14     (SDRAM_INITPLR_DISABLE)
 342#define CONFIG_SYS_SDRAM0_INITPLR15     (SDRAM_INITPLR_DISABLE)
 343#define CONFIG_SYS_SDRAM0_RQDC          (SDRAM_RQDC_RQDE_ENABLE | \
 344                                 SDRAM_RQDC_RQFD_ENCODE(56))
 345#define CONFIG_SYS_SDRAM0_RFDC          SDRAM_RFDC_RFFD_ENCODE(521)
 346#define CONFIG_SYS_SDRAM0_RDCC          (SDRAM_RDCC_RDSS_T2)
 347#define CONFIG_SYS_SDRAM0_DLCR          (SDRAM_DLCR_DCLM_AUTO           | \
 348                                 SDRAM_DLCR_DLCS_CONT_DONE      | \
 349                                 SDRAM_DLCR_DLCV_ENCODE(165))
 350#define CONFIG_SYS_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV)
 351#define CONFIG_SYS_SDRAM0_WRDTR 0x00000000
 352#define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \
 353                                 SDRAM_SDTR1_RTW_2_CLK  | \
 354                                 SDRAM_SDTR1_RTRO_1_CLK)
 355#define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK          | \
 356                                 SDRAM_SDTR2_WTR_2_CLK          | \
 357                                 SDRAM_SDTR2_XSNR_32_CLK        | \
 358                                 SDRAM_SDTR2_WPC_4_CLK          | \
 359                                 SDRAM_SDTR2_RPC_2_CLK          | \
 360                                 SDRAM_SDTR2_RP_3_CLK           | \
 361                                 SDRAM_SDTR2_RRD_2_CLK)
 362#define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(8)      | \
 363                                 SDRAM_SDTR3_RC_ENCODE(11)      | \
 364                                 SDRAM_SDTR3_XCS                | \
 365                                 SDRAM_SDTR3_RFC_ENCODE(26))
 366#define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \
 367                                 SDRAM_MMODE_DCL_DDR2_4_0_CLK | \
 368                                 SDRAM_MMODE_BLEN_4)
 369#define CONFIG_SYS_SDRAM0_MEMODE        (SDRAM_MEMODE_DQS_DISABLE | \
 370                                 SDRAM_MEMODE_RTT_75OHM)
 371
 372/*-----------------------------------------------------------------------
 373 * I2C
 374 *----------------------------------------------------------------------*/
 375#define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address  */
 376
 377#define CONFIG_SYS_I2C_EEPROM_ADDR      0x52    /* I2C boot EEPROM (24C02BN)    */
 378#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1       /* Bytes of address             */
 379#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 380#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 381
 382/* I2C bootstrap EEPROM */
 383#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x52
 384#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
 385#define CONFIG_4xx_CONFIG_BLOCKSIZE             16
 386
 387/* Standard DTT sensor configuration */
 388#define CONFIG_DTT_DS1775       1
 389#define CONFIG_DTT_SENSORS      { 0 }
 390#define CONFIG_SYS_I2C_DTT_ADDR 0x48
 391
 392/* RTC configuration */
 393#define CONFIG_RTC_DS1338       1
 394#define CONFIG_SYS_I2C_RTC_ADDR 0x68
 395
 396/*-----------------------------------------------------------------------
 397 * Ethernet
 398 *----------------------------------------------------------------------*/
 399#define CONFIG_M88E1111_PHY     1
 400#define CONFIG_IBM_EMAC4_V4     1
 401#define CONFIG_EMAC_PHY_MODE    EMAC_PHY_MODE_RGMII_RGMII
 402#define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
 403
 404#define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 405#define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 406
 407#define CONFIG_HAS_ETH0         1
 408
 409#define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 410#define CONFIG_PHY1_ADDR        2
 411
 412/* Debug messages for the DDR autocalibration */
 413#define CONFIG_AUTOCALIB                "silent\0"  /* default is non-verbose */
 414
 415/*
 416 * Default environment variables
 417 */
 418#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 419        CONFIG_AMCC_DEF_ENV                                             \
 420        CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 421        CONFIG_AMCC_DEF_ENV_PPC_OLD                                     \
 422        CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 423        CONFIG_AMCC_DEF_ENV_NAND_UPD                                    \
 424        "logversion=2\0"                                                \
 425        "kernel_addr=fc000000\0"                                        \
 426        "fdt_addr=fc1e0000\0"                                           \
 427        "ramdisk_addr=fc200000\0"                                       \
 428        "pciconfighost=1\0"                                             \
 429        "pcie_mode=RP:RP\0"                                             \
 430        ""
 431
 432/*
 433 * Commands additional to the ones defined in amcc-common.h
 434 */
 435#define CONFIG_CMD_CHIP_CONFIG
 436#define CONFIG_CMD_DATE
 437#define CONFIG_CMD_LOG
 438#define CONFIG_CMD_NAND
 439#define CONFIG_CMD_PCI
 440#define CONFIG_CMD_SNTP
 441
 442/*
 443 * Don't run the memory POST on the NAND-booting version. It will
 444 * overwrite part of the U-Boot image which is already loaded from NAND
 445 * to SDRAM.
 446 */
 447#if defined(CONFIG_NAND_U_BOOT)
 448#define CONFIG_SYS_POST_MEMORY_ON       0
 449#else
 450#define CONFIG_SYS_POST_MEMORY_ON       CONFIG_SYS_POST_MEMORY
 451#endif
 452
 453/* POST support */
 454#define CONFIG_POST             (CONFIG_SYS_POST_CACHE          | \
 455                                 CONFIG_SYS_POST_CPU            | \
 456                                 CONFIG_SYS_POST_ETHER          | \
 457                                 CONFIG_SYS_POST_I2C            | \
 458                                 CONFIG_SYS_POST_MEMORY_ON      | \
 459                                 CONFIG_SYS_POST_UART)
 460
 461/* Define here the base-addresses of the UARTs to test in POST */
 462#define CONFIG_SYS_POST_UART_TABLE      {UART0_BASE, UART1_BASE}
 463
 464#define CONFIG_LOGBUFFER
 465#define CONFIG_SYS_POST_CACHE_ADDR      0x00800000 /* free virtual address      */
 466
 467#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
 468
 469/*-----------------------------------------------------------------------
 470 * PCI stuff
 471 *----------------------------------------------------------------------*/
 472#define CONFIG_PCI                      /* include pci support          */
 473#define CONFIG_PCI_PNP          1       /* do pci plug-and-play         */
 474#define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
 475#define CONFIG_PCI_CONFIG_HOST_BRIDGE
 476
 477/*-----------------------------------------------------------------------
 478 * PCIe stuff
 479 *----------------------------------------------------------------------*/
 480#define CONFIG_SYS_PCIE_MEMBASE 0x90000000      /* mapped PCIe memory   */
 481#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000      /* 128 Meg, smallest incr per port */
 482
 483#define CONFIG_SYS_PCIE0_CFGBASE        0xa0000000      /* remote access */
 484#define CONFIG_SYS_PCIE0_XCFGBASE       0xb0000000      /* local access */
 485#define CONFIG_SYS_PCIE0_CFGMASK        0xe0000001      /* 512 Meg */
 486
 487#define CONFIG_SYS_PCIE1_CFGBASE        0xc0000000      /* remote access */
 488#define CONFIG_SYS_PCIE1_XCFGBASE       0xd0000000      /* local access */
 489#define CONFIG_SYS_PCIE1_CFGMASK        0xe0000001      /* 512 Meg */
 490
 491#define CONFIG_SYS_PCIE0_UTLBASE        0xef502000
 492#define CONFIG_SYS_PCIE1_UTLBASE        0xef503000
 493
 494/* base address of inbound PCIe window */
 495#define CONFIG_SYS_PCIE_INBOUND_BASE    0x0000000000000000ULL
 496
 497/*-----------------------------------------------------------------------
 498 * External Bus Controller (EBC) Setup
 499 *----------------------------------------------------------------------*/
 500#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 501/* booting from NAND, so NAND chips select has to be on CS 0 */
 502#define CONFIG_SYS_NAND_CS              0               /* NAND chip connected to CSx   */
 503
 504/* Memory Bank 1 (NOR-FLASH) initialization                                     */
 505#define CONFIG_SYS_EBC_PB1AP            0x05806500
 506#define CONFIG_SYS_EBC_PB1CR           0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
 507
 508/* Memory Bank 0 (NAND-FLASH) initialization                                    */
 509#define CONFIG_SYS_EBC_PB0AP            0x018003c0
 510#define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_NAND_ADDR | 0x1e000)
 511#else
 512#define CONFIG_SYS_NAND_CS              1               /* NAND chip connected to CSx   */
 513
 514/* Memory Bank 0 (NOR-FLASH) initialization                                     */
 515#define CONFIG_SYS_EBC_PB0AP            0x05806500
 516#define CONFIG_SYS_EBC_PB0CR           0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
 517
 518/* Memory Bank 1 (NAND-FLASH) initialization                                    */
 519#define CONFIG_SYS_EBC_PB1AP            0x018003c0
 520#define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_NAND_ADDR | 0x1e000)
 521#endif
 522
 523/* Memory Bank 2 (FPGA) initialization                                  */
 524#define CONFIG_SYS_EBC_PB2AP            (EBC_BXAP_BME_ENABLED |         \
 525                                         EBC_BXAP_FWT_ENCODE(6) |       \
 526                                         EBC_BXAP_BWT_ENCODE(1) |       \
 527                                         EBC_BXAP_BCE_DISABLE |         \
 528                                         EBC_BXAP_BCT_2TRANS |          \
 529                                         EBC_BXAP_CSN_ENCODE(0) |       \
 530                                         EBC_BXAP_OEN_ENCODE(0) |       \
 531                                         EBC_BXAP_WBN_ENCODE(3) |       \
 532                                         EBC_BXAP_WBF_ENCODE(1) |       \
 533                                         EBC_BXAP_TH_ENCODE(4) |        \
 534                                         EBC_BXAP_RE_DISABLED |         \
 535                                         EBC_BXAP_SOR_DELAYED |         \
 536                                         EBC_BXAP_BEM_WRITEONLY |       \
 537                                         EBC_BXAP_PEN_DISABLED)
 538#define CONFIG_SYS_EBC_PB2CR    (CONFIG_SYS_FPGA_BASE | 0x18000)
 539
 540#define CONFIG_SYS_EBC_CFG              0x7FC00000 /*  EBC0_CFG */
 541
 542/*-----------------------------------------------------------------------
 543 * GPIO Setup
 544 *----------------------------------------------------------------------*/
 545#define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 546{                                                                                       \
 547/* GPIO Core 0 */                                                                       \
 548{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0)                 */      \
 549{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1)                 */      \
 550{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2)                 */      \
 551{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3)                 */      \
 552{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20)    USB2_DATA(4)    */      \
 553{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21)    USB2_DATA(5)    */      \
 554{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22)    USB2_DATA(6)    */      \
 555{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23)    USB2_DATA(7)    */      \
 556{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1)   IRQ(7)          */      \
 557{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2)   IRQ(8)          */      \
 558{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3)  IRQ(9)          */      \
 559{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 IRQ(6)                         */      \
 560{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16)   USB2_DATA(0)    */      \
 561{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17)   USB2_DATA(1)    */      \
 562{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18)   USB2_DATA(2)    */      \
 563{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19)   USB2_DATA(3)    */      \
 564{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD      UART1_CTS       */      \
 565{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR      UART1_RTS       */      \
 566{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS                      */      \
 567{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS                      */      \
 568{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO20 UART0_DTR      UART1_TX        */      \
 569{GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO21 UART0_RI       UART1_RX        */      \
 570{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ   DMA_ACK2        */      \
 571{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK   DMA_REQ2        */      \
 572{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ    DMA_EOT2        IRQ(4) */ \
 573{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK    DMA_ACK3        IRQ(3) */ \
 574{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5)    DMA_EOT0        TS(3) */ \
 575{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ    DMA_EOT3        IRQ(5) */ \
 576{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO28                                */      \
 577{GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO29 DMA_EOT1       IRQ(2)          */      \
 578{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO30 DMA_REQ1       IRQ(1)          */      \
 579{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO31 DMA_ACK1       IRQ(0)          */      \
 580}                                                                                               \
 581}
 582
 583/*-----------------------------------------------------------------------
 584 * Some Kilauea stuff..., mainly fpga registers
 585 */
 586#define CONFIG_SYS_FPGA_REG_BASE                CONFIG_SYS_FPGA_BASE
 587#define CONFIG_SYS_FPGA_FIFO_BASE               (CONFIG_SYS_FPGA_BASE | (1 << 10))
 588
 589/* interrupt */
 590#define CONFIG_SYS_FPGA_SLIC0_R_DPRAM_INT       0x80000000
 591#define CONFIG_SYS_FPGA_SLIC0_W_DPRAM_INT       0x40000000
 592#define CONFIG_SYS_FPGA_SLIC1_R_DPRAM_INT       0x20000000
 593#define CONFIG_SYS_FPGA_SLIC1_W_DPRAM_INT       0x10000000
 594#define CONFIG_SYS_FPGA_PHY0_INT                0x08000000
 595#define CONFIG_SYS_FPGA_PHY1_INT                0x04000000
 596#define CONFIG_SYS_FPGA_SLIC0_INT               0x02000000
 597#define CONFIG_SYS_FPGA_SLIC1_INT               0x01000000
 598
 599/* DPRAM setting */
 600/* 00: 32B; 01: 64B; 10: 128B; 11: 256B  */
 601#define CONFIG_SYS_FPGA_DPRAM_R_INT_LINE        0x00400000      /* 64 B */
 602#define CONFIG_SYS_FPGA_DPRAM_W_INT_LINE        0x00100000      /* 64 B */
 603#define CONFIG_SYS_FPGA_DPRAM_RW_TYPE           0x00080000
 604#define CONFIG_SYS_FPGA_DPRAM_RST               0x00040000
 605#define CONFIG_SYS_FPGA_UART0_FO                0x00020000
 606#define CONFIG_SYS_FPGA_UART1_FO                0x00010000
 607
 608/* loopback */
 609#define CONFIG_SYS_FPGA_CHIPSIDE_LOOPBACK       0x00004000
 610#define CONFIG_SYS_FPGA_LINESIDE_LOOPBACK       0x00008000
 611#define CONFIG_SYS_FPGA_SLIC0_ENABLE            0x00002000
 612#define CONFIG_SYS_FPGA_SLIC1_ENABLE            0x00001000
 613#define CONFIG_SYS_FPGA_SLIC0_CS                0x00000800
 614#define CONFIG_SYS_FPGA_SLIC1_CS                0x00000400
 615#define CONFIG_SYS_FPGA_USER_LED0               0x00000200
 616#define CONFIG_SYS_FPGA_USER_LED1               0x00000100
 617
 618#define CONFIG_SYS_FPGA_MAGIC_MASK              0xffff0000
 619#define CONFIG_SYS_FPGA_MAGIC                   0xabcd0000
 620#define CONFIG_SYS_FPGA_VER_MASK                0x0000ff00
 621
 622#endif  /* __CONFIG_H */
 623