1/* 2 * Configuration settings for the Gumstix Overo board. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 * MA 02111-1307 USA 18 */ 19 20#ifndef __CONFIG_H 21#define __CONFIG_H 22 23/* 24 * High Level Configuration Options 25 */ 26#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ 27#define CONFIG_OMAP 1 /* in a TI OMAP core */ 28#define CONFIG_OMAP34XX 1 /* which is a 34XX */ 29#define CONFIG_OMAP3430 1 /* which is in a 3430 */ 30#define CONFIG_OMAP3_OVERO 1 /* working with overo */ 31 32#define CONFIG_SDRC /* The chip has SDRC controller */ 33 34#include <asm/arch/cpu.h> /* get chip and board defs */ 35#include <asm/arch/omap3.h> 36 37/* 38 * Display CPU and Board information 39 */ 40#define CONFIG_DISPLAY_CPUINFO 1 41#define CONFIG_DISPLAY_BOARDINFO 1 42 43/* Clock Defines */ 44#define V_OSCK 26000000 /* Clock output from T2 */ 45#define V_SCLK (V_OSCK >> 1) 46 47#undef CONFIG_USE_IRQ /* no support for IRQs */ 48#define CONFIG_MISC_INIT_R 49 50#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 51#define CONFIG_SETUP_MEMORY_TAGS 1 52#define CONFIG_INITRD_TAG 1 53#define CONFIG_REVISION_TAG 1 54 55/* 56 * Size of malloc() pool 57 */ 58#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 59 /* Sector */ 60#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 61#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ 62 /* initial data */ 63 64/* 65 * Hardware drivers 66 */ 67 68/* 69 * NS16550 Configuration 70 */ 71#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 72 73#define CONFIG_SYS_NS16550 74#define CONFIG_SYS_NS16550_SERIAL 75#define CONFIG_SYS_NS16550_REG_SIZE (-4) 76#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 77 78/* 79 * select serial console configuration 80 */ 81#define CONFIG_CONS_INDEX 3 82#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 83#define CONFIG_SERIAL3 3 84 85/* allow to overwrite serial and ethaddr */ 86#define CONFIG_ENV_OVERWRITE 87#define CONFIG_BAUDRATE 115200 88#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 89 115200} 90#define CONFIG_MMC 1 91#define CONFIG_OMAP3_MMC 1 92#define CONFIG_DOS_PARTITION 1 93 94/* DDR - I use Micron DDR */ 95#define CONFIG_OMAP3_MICRON_DDR 1 96 97/* commands to include */ 98#include <config_cmd_default.h> 99 100#define CONFIG_CMD_EXT2 /* EXT2 Support */ 101#define CONFIG_CMD_FAT /* FAT support */ 102#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 103 104#define CONFIG_CMD_I2C /* I2C serial bus support */ 105#define CONFIG_CMD_MMC /* MMC support */ 106#define CONFIG_CMD_NAND /* NAND support */ 107 108#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 109#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 110#undef CONFIG_CMD_IMI /* iminfo */ 111#undef CONFIG_CMD_IMLS /* List all found images */ 112#undef CONFIG_CMD_NFS /* NFS support */ 113#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ 114 115#define CONFIG_SYS_NO_FLASH 116#define CONFIG_HARD_I2C 1 117#define CONFIG_SYS_I2C_SPEED 100000 118#define CONFIG_SYS_I2C_SLAVE 1 119#define CONFIG_SYS_I2C_BUS 0 120#define CONFIG_SYS_I2C_BUS_SELECT 1 121#define CONFIG_DRIVER_OMAP34XX_I2C 1 122 123/* 124 * TWL4030 125 */ 126#define CONFIG_TWL4030_POWER 1 127#define CONFIG_TWL4030_LED 1 128 129/* 130 * Board NAND Info. 131 */ 132#define CONFIG_SYS_NAND_QUIET_TEST 1 133#define CONFIG_NAND_OMAP_GPMC 134#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 135 /* to access nand */ 136#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 137 /* to access nand */ 138 /* at CS0 */ 139#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 140 141#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 142 /* devices */ 143#define CONFIG_JFFS2_NAND 144/* nand device jffs2 lives on */ 145#define CONFIG_JFFS2_DEV "nand0" 146/* start of jffs2 partition */ 147#define CONFIG_JFFS2_PART_OFFSET 0x680000 148#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ 149 /* partition */ 150 151/* Environment information */ 152#define CONFIG_BOOTDELAY 5 153 154#define CONFIG_EXTRA_ENV_SETTINGS \ 155 "loadaddr=0x82000000\0" \ 156 "console=ttyS2,115200n8\0" \ 157 "mpurate=500\0" \ 158 "vram=12M\0" \ 159 "dvimode=1024x768MR-16@60\0" \ 160 "defaultdisplay=dvi\0" \ 161 "mmcroot=/dev/mmcblk0p2 rw\0" \ 162 "mmcrootfstype=ext3 rootwait\0" \ 163 "nandroot=/dev/mtdblock4 rw\0" \ 164 "nandrootfstype=jffs2\0" \ 165 "mmcargs=setenv bootargs console=${console} " \ 166 "mpurate=${mpurate} " \ 167 "vram=${vram} " \ 168 "omapfb.mode=dvi:${dvimode} " \ 169 "omapfb.debug=y " \ 170 "omapdss.def_disp=${defaultdisplay} " \ 171 "root=${mmcroot} " \ 172 "rootfstype=${mmcrootfstype}\0" \ 173 "nandargs=setenv bootargs console=${console} " \ 174 "mpurate=${mpurate} " \ 175 "vram=${vram} " \ 176 "omapfb.mode=dvi:${dvimode} " \ 177 "omapfb.debug=y " \ 178 "omapdss.def_disp=${defaultdisplay} " \ 179 "root=${nandroot} " \ 180 "rootfstype=${nandrootfstype}\0" \ 181 "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ 182 "bootscript=echo Running bootscript from mmc ...; " \ 183 "source ${loadaddr}\0" \ 184 "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ 185 "mmcboot=echo Booting from mmc ...; " \ 186 "run mmcargs; " \ 187 "bootm ${loadaddr}\0" \ 188 "nandboot=echo Booting from nand ...; " \ 189 "run nandargs; " \ 190 "nand read ${loadaddr} 280000 400000; " \ 191 "bootm ${loadaddr}\0" \ 192 193#define CONFIG_BOOTCOMMAND \ 194 "if mmc init; then " \ 195 "if run loadbootscript; then " \ 196 "run bootscript; " \ 197 "else " \ 198 "if run loaduimage; then " \ 199 "run mmcboot; " \ 200 "else run nandboot; " \ 201 "fi; " \ 202 "fi; " \ 203 "else run nandboot; fi" 204 205#define CONFIG_AUTO_COMPLETE 1 206/* 207 * Miscellaneous configurable options 208 */ 209#define CONFIG_SYS_LONGHELP /* undef to save memory */ 210#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 211#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 212#define CONFIG_SYS_PROMPT "Overo # " 213#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 214/* Print Buffer Size */ 215#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 216 sizeof(CONFIG_SYS_PROMPT) + 16) 217#define CONFIG_SYS_MAXARGS 16 /* max number of command */ 218 /* args */ 219/* Boot Argument Buffer Size */ 220#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 221/* memtest works on */ 222#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 223#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 224 0x01F00000) /* 31MB */ 225 226#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 227 /* address */ 228/* 229 * OMAP3 has 12 GP timers, they can be driven by the system clock 230 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 231 * This rate is divided by a local divisor. 232 */ 233#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 234#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 235#define CONFIG_SYS_HZ 1000 236 237/*----------------------------------------------------------------------- 238 * Stack sizes 239 * 240 * The stack sizes are set up in start.S using the settings below 241 */ 242#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ 243#ifdef CONFIG_USE_IRQ 244#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ 245#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ 246#endif 247 248/*----------------------------------------------------------------------- 249 * Physical Memory Map 250 */ 251#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 252#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 253#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ 254#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 255 256/* SDRAM Bank Allocation method */ 257#define SDRC_R_B_C 1 258 259/*----------------------------------------------------------------------- 260 * FLASH and environment organization 261 */ 262 263/* **** PISMO SUPPORT *** */ 264 265/* Configure the PISMO */ 266#define PISMO1_NAND_SIZE GPMC_SIZE_128M 267#define PISMO1_ONEN_SIZE GPMC_SIZE_128M 268 269#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ 270 /* one chip */ 271#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 272#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 273 274#define CONFIG_SYS_FLASH_BASE boot_flash_base 275 276/* Monitor at start of flash */ 277#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 278#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 279 280#define CONFIG_ENV_IS_IN_NAND 1 281#define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */ 282#define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */ 283 284#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec 285#define CONFIG_ENV_OFFSET boot_flash_off 286#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 287 288/*----------------------------------------------------------------------- 289 * CFI FLASH driver setup 290 */ 291/* timeout values are in ticks */ 292#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 293#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 294 295/* Flash banks JFFS2 should use */ 296#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 297 CONFIG_SYS_MAX_NAND_DEVICE) 298#define CONFIG_SYS_JFFS2_MEM_NAND 299/* use flash_info[2] */ 300#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 301#define CONFIG_SYS_JFFS2_NUM_BANKS 1 302 303#ifndef __ASSEMBLY__ 304extern unsigned int boot_flash_base; 305extern volatile unsigned int boot_flash_env_addr; 306extern unsigned int boot_flash_off; 307extern unsigned int boot_flash_sec; 308extern unsigned int boot_flash_type; 309#endif 310 311#if defined(CONFIG_CMD_NET) 312/*---------------------------------------------------------------------------- 313 * SMSC9211 Ethernet from SMSC9118 family 314 *---------------------------------------------------------------------------- 315 */ 316 317#define CONFIG_NET_MULTI 318#define CONFIG_SMC911X 1 319#define CONFIG_SMC911X_32_BIT 320#define CONFIG_SMC911X_BASE 0x2C000000 321 322#endif /* (CONFIG_CMD_NET) */ 323 324#endif /* __CONFIG_H */ 325