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35
36#ifndef __CONFIG_H
37#define __CONFIG_H
38
39
40#define CONFIG_MPC86xx 1
41#define CONFIG_MPC8641 1
42#define CONFIG_SBC8641D 1
43#define CONFIG_MP 1
44#define CONFIG_LINUX_RESET_VEC 0x100
45
46#ifdef RUN_DIAG
47#define CONFIG_SYS_DIAG_ADDR 0xff800000
48#endif
49
50#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
51
52
53
54
55
56#define CONFIG_SYS_SCRATCH_VA 0xe8000000
57
58#define CONFIG_PCI 1
59#define CONFIG_PCIE1 1
60#define CONFIG_PCIE2 1
61#define CONFIG_FSL_PCI_INIT 1
62#define CONFIG_FSL_LAW 1
63
64#define CONFIG_TSEC_ENET
65#define CONFIG_ENV_OVERWRITE
66
67#define CONFIG_HIGH_BATS 1
68
69#undef CONFIG_SPD_EEPROM
70#undef CONFIG_DDR_ECC
71#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
72#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
73#define CONFIG_NUM_DDR_CONTROLLERS 2
74#define CACHE_LINE_INTERLEAVING 0x20000000
75#define PAGE_INTERLEAVING 0x21000000
76#define BANK_INTERLEAVING 0x22000000
77#define SUPER_BANK_INTERLEAVING 0x23000000
78
79
80#define CONFIG_ALTIVEC 1
81
82
83
84
85#define CONFIG_SYS_L2
86#define L2_INIT 0
87#define L2_ENABLE (L2CR_L2E)
88
89#ifndef CONFIG_SYS_CLK_FREQ
90#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
91#endif
92
93#define CONFIG_BOARD_EARLY_INIT_F 1
94
95#undef CONFIG_SYS_DRAM_TEST
96#define CONFIG_SYS_MEMTEST_START 0x00200000
97#define CONFIG_SYS_MEMTEST_END 0x00400000
98
99
100
101
102
103#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
104#define CONFIG_SYS_CCSRBAR 0xf8000000
105#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
106
107#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
108#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
109#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
110
111
112
113
114#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
115#define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000
116#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
117#define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2
118#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000
119#define CONFIG_VERY_BIG_RAM
120
121#define CONFIG_NUM_DDR_CONTROLLERS 2
122#define CONFIG_DIMM_SLOTS_PER_CTLR 2
123#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
124
125#if defined(CONFIG_SPD_EEPROM)
126
127
128
129 #define SPD_EEPROM_ADDRESS1 0x51
130 #define SPD_EEPROM_ADDRESS2 0x52
131 #define SPD_EEPROM_ADDRESS3 0x53
132 #define SPD_EEPROM_ADDRESS4 0x54
133
134#else
135
136
137
138
139 #define CONFIG_SYS_SDRAM_SIZE 512
140
141 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
142 #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
143 #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000
144 #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000
145 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
146 #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
147 #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000
148 #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000
149 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
150 #define CONFIG_SYS_DDR_TIMING_0 0x00220802
151 #define CONFIG_SYS_DDR_TIMING_1 0x38377322
152 #define CONFIG_SYS_DDR_TIMING_2 0x002040c7
153 #define CONFIG_SYS_DDR_CFG_1A 0x43008008
154 #define CONFIG_SYS_DDR_CFG_2 0x24401000
155 #define CONFIG_SYS_DDR_MODE_1 0x23c00542
156 #define CONFIG_SYS_DDR_MODE_2 0x00000000
157 #define CONFIG_SYS_DDR_MODE_CTL 0x00000000
158 #define CONFIG_SYS_DDR_INTERVAL 0x05080100
159 #define CONFIG_SYS_DDR_DATA_INIT 0x00000000
160 #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
161 #define CONFIG_SYS_DDR_CFG_1B 0xC3008008
162
163 #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F
164 #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000
165 #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000
166 #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000
167 #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102
168 #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000
169 #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000
170 #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000
171 #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000
172 #define CONFIG_SYS_DDR2_TIMING_0 0x00220802
173 #define CONFIG_SYS_DDR2_TIMING_1 0x38377322
174 #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7
175 #define CONFIG_SYS_DDR2_CFG_1A 0x43008008
176 #define CONFIG_SYS_DDR2_CFG_2 0x24401000
177 #define CONFIG_SYS_DDR2_MODE_1 0x23c00542
178 #define CONFIG_SYS_DDR2_MODE_2 0x00000000
179 #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000
180 #define CONFIG_SYS_DDR2_INTERVAL 0x05080100
181 #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000
182 #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000
183 #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008
184
185
186#endif
187
188
189
190
191
192
193
194#define CONFIG_SYS_FLASH_BASE 0xff000000
195
196
197#define CONFIG_SYS_BR0_PRELIM 0xff001001
198#define CONFIG_SYS_OR0_PRELIM 0xff006e65
199
200
201#define CONFIG_SYS_BR1_PRELIM 0xf0000801
202#define CONFIG_SYS_OR1_PRELIM 0xffff6e65
203
204
205#define CONFIG_SYS_BR2_PRELIM 0xf1000801
206#define CONFIG_SYS_OR2_PRELIM 0xfff06e65
207
208
209#define CONFIG_SYS_BR3_PRELIM 0xe0001861
210#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0
211#define CONFIG_SYS_BR4_PRELIM 0xe4001861
212#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0
213
214
215#define CONFIG_SYS_BR5_PRELIM 0xe8001001
216#define CONFIG_SYS_OR5_PRELIM 0xf8006e65
217
218
219#define CONFIG_SYS_BR6_PRELIM 0xf4000801
220#define CONFIG_SYS_OR6_PRELIM 0xfff06e65
221
222
223#define CONFIG_SYS_BR7_PRELIM 0xf2000801
224#define CONFIG_SYS_OR7_PRELIM 0xfff06e65
225
226#define CONFIG_SYS_MAX_FLASH_BANKS 1
227#define CONFIG_SYS_MAX_FLASH_SECT 131
228
229#undef CONFIG_SYS_FLASH_CHECKSUM
230#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
231#define CONFIG_SYS_FLASH_WRITE_TOUT 500
232#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
233#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000
234
235#define CONFIG_FLASH_CFI_DRIVER
236#define CONFIG_SYS_FLASH_CFI
237#define CONFIG_SYS_WRITE_SWAPPED_DATA
238#define CONFIG_SYS_FLASH_EMPTY_INFO
239#define CONFIG_SYS_FLASH_PROTECTION
240
241#undef CONFIG_CLOCKS_IN_MHZ
242
243#define CONFIG_SYS_INIT_RAM_LOCK 1
244#ifndef CONFIG_SYS_INIT_RAM_LOCK
245#define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000
246#else
247#define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000
248#endif
249#define CONFIG_SYS_INIT_RAM_END 0x4000
250
251#define CONFIG_SYS_GBL_DATA_SIZE 128
252#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
253#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
254
255#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
256#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
257
258
259#define CONFIG_CONS_INDEX 1
260#undef CONFIG_SERIAL_SOFTWARE_FIFO
261#define CONFIG_SYS_NS16550
262#define CONFIG_SYS_NS16550_SERIAL
263#define CONFIG_SYS_NS16550_REG_SIZE 1
264#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
265
266#define CONFIG_SYS_BAUDRATE_TABLE \
267 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
268
269#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
270#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
271
272
273#define CONFIG_SYS_HUSH_PARSER
274#ifdef CONFIG_SYS_HUSH_PARSER
275#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
276#endif
277
278
279
280
281#define CONFIG_OF_LIBFDT 1
282#define CONFIG_OF_BOARD_SETUP 1
283#define CONFIG_OF_STDOUT_VIA_ALIAS 1
284
285
286
287
288#define CONFIG_FSL_I2C
289#define CONFIG_HARD_I2C
290#undef CONFIG_SOFT_I2C
291#define CONFIG_SYS_I2C_SPEED 400000
292#define CONFIG_SYS_I2C_SLAVE 0x7F
293#define CONFIG_SYS_I2C_NOPROBES {0x69}
294#define CONFIG_SYS_I2C_OFFSET 0x3100
295
296
297
298
299#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000
300#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
301#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000
302
303
304
305
306
307#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
308#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
309#define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS
310#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
311#define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000
312#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS
313#define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS
314#define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000
315
316#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
317#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
318#define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS
319#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
320#define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000
321#define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS
322#define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS
323#define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000
324
325#if defined(CONFIG_PCI)
326
327#define CONFIG_PCI_SCAN_SHOW
328
329#undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
330
331#define CONFIG_NET_MULTI
332#define CONFIG_PCI_PNP
333
334#undef CONFIG_EEPRO100
335#undef CONFIG_TULIP
336
337#if !defined(CONFIG_PCI_PNP)
338 #define PCI_ENET0_IOADDR 0xe0000000
339 #define PCI_ENET0_MEMADDR 0xe0000000
340 #define PCI_IDSEL_NUMBER 0x0c
341#endif
342
343#define CONFIG_PCI_SCAN_SHOW
344
345#define CONFIG_DOS_PARTITION
346#undef CONFIG_SCSI_AHCI
347
348#ifdef CONFIG_SCSI_AHCI
349#define CONFIG_SATA_ULI5288
350#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
351#define CONFIG_SYS_SCSI_MAX_LUN 1
352#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
353#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
354#endif
355
356#endif
357
358#if defined(CONFIG_TSEC_ENET)
359
360#ifndef CONFIG_NET_MULTI
361#define CONFIG_NET_MULTI 1
362#endif
363
364
365
366#define CONFIG_TSEC1 1
367#define CONFIG_TSEC1_NAME "eTSEC1"
368#define CONFIG_TSEC2 1
369#define CONFIG_TSEC2_NAME "eTSEC2"
370#define CONFIG_TSEC3 1
371#define CONFIG_TSEC3_NAME "eTSEC3"
372#define CONFIG_TSEC4 1
373#define CONFIG_TSEC4_NAME "eTSEC4"
374
375#define TSEC1_PHY_ADDR 0x1F
376#define TSEC2_PHY_ADDR 0x00
377#define TSEC3_PHY_ADDR 0x01
378#define TSEC4_PHY_ADDR 0x02
379#define TSEC1_PHYIDX 0
380#define TSEC2_PHYIDX 0
381#define TSEC3_PHYIDX 0
382#define TSEC4_PHYIDX 0
383#define TSEC1_FLAGS TSEC_GIGABIT
384#define TSEC2_FLAGS TSEC_GIGABIT
385#define TSEC3_FLAGS TSEC_GIGABIT
386#define TSEC4_FLAGS TSEC_GIGABIT
387
388#define CONFIG_SYS_TBIPA_VALUE 0x1e
389
390#define CONFIG_ETHPRIME "eTSEC1"
391
392#endif
393
394
395
396
397
398#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
399#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
400#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
401#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
402
403
404
405
406
407
408
409#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \
410 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
411#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP)
412#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
413#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
414
415
416
417
418
419#define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW \
420 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
421#define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP)
422#define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
423#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
424
425
426
427
428
429#define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \
430 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
431#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP)
432#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
433#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
434
435#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
436#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
437 | BATL_PP_RW | BATL_CACHEINHIBIT \
438 | BATL_GUARDEDSTORAGE)
439#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
440 | BATU_BL_1M | BATU_VS | BATU_VP)
441#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
442 | BATL_PP_RW | BATL_CACHEINHIBIT)
443#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
444#endif
445
446
447
448
449
450
451
452#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \
453 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
454#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP)
455#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
456#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
457
458
459
460
461
462#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
463#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
464#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
465#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
466
467
468
469
470
471#define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \
472 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
473#define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP)
474#define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE)
475#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
476
477
478#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
479 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
480#define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
481#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
482 | BATL_MEMCOHERENCE)
483#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
484
485#define CONFIG_SYS_DBAT7L 0x00000000
486#define CONFIG_SYS_DBAT7U 0x00000000
487#define CONFIG_SYS_IBAT7L 0x00000000
488#define CONFIG_SYS_IBAT7U 0x00000000
489
490
491
492
493#define CONFIG_ENV_IS_IN_FLASH 1
494#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
495#define CONFIG_ENV_SECT_SIZE 0x40000
496#define CONFIG_ENV_SIZE 0x2000
497
498#define CONFIG_LOADS_ECHO 1
499#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
500
501#include <config_cmd_default.h>
502 #define CONFIG_CMD_PING
503 #define CONFIG_CMD_I2C
504 #define CONFIG_CMD_REGINFO
505
506#if defined(CONFIG_PCI)
507 #define CONFIG_CMD_PCI
508#endif
509
510#undef CONFIG_WATCHDOG
511
512
513
514
515#define CONFIG_SYS_LONGHELP
516#define CONFIG_SYS_LOAD_ADDR 0x2000000
517#define CONFIG_SYS_PROMPT "=> "
518
519#if defined(CONFIG_CMD_KGDB)
520 #define CONFIG_SYS_CBSIZE 1024
521#else
522 #define CONFIG_SYS_CBSIZE 256
523#endif
524
525#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
526#define CONFIG_SYS_MAXARGS 16
527#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
528#define CONFIG_SYS_HZ 1000
529
530
531
532
533
534
535#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
536
537
538#define CONFIG_SYS_DCACHE_SIZE 32768
539#define CONFIG_SYS_CACHELINE_SIZE 32
540#if defined(CONFIG_CMD_KGDB)
541#define CONFIG_SYS_CACHELINE_SHIFT 5
542#endif
543
544
545
546
547
548
549#define BOOTFLAG_COLD 0x01
550#define BOOTFLAG_WARM 0x02
551
552#if defined(CONFIG_CMD_KGDB)
553#define CONFIG_KGDB_BAUDRATE 230400
554#define CONFIG_KGDB_SER_INDEX 2
555#endif
556
557
558
559
560
561
562#if defined(CONFIG_TSEC_ENET)
563#define CONFIG_ETHADDR 02:E0:0C:00:00:01
564#define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD
565#define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD
566#define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD
567#endif
568
569#define CONFIG_HAS_ETH0 1
570#define CONFIG_HAS_ETH1 1
571#define CONFIG_HAS_ETH2 1
572#define CONFIG_HAS_ETH3 1
573
574#define CONFIG_IPADDR 192.168.0.50
575
576#define CONFIG_HOSTNAME sbc8641d
577#define CONFIG_ROOTPATH /opt/eldk/ppc_74xx
578#define CONFIG_BOOTFILE uImage
579
580#define CONFIG_SERVERIP 192.168.0.2
581#define CONFIG_GATEWAYIP 192.168.0.1
582#define CONFIG_NETMASK 255.255.255.0
583
584
585#define CONFIG_LOADADDR 1000000
586
587#define CONFIG_BOOTDELAY 10
588#undef CONFIG_BOOTARGS
589
590#define CONFIG_BAUDRATE 115200
591
592#define CONFIG_EXTRA_ENV_SETTINGS \
593 "netdev=eth0\0" \
594 "consoledev=ttyS0\0" \
595 "ramdiskaddr=2000000\0" \
596 "ramdiskfile=uRamdisk\0" \
597 "dtbaddr=400000\0" \
598 "dtbfile=sbc8641d.dtb\0" \
599 "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
600 "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
601 "maxcpus=1"
602
603#define CONFIG_NFSBOOTCOMMAND \
604 "setenv bootargs root=/dev/nfs rw " \
605 "nfsroot=$serverip:$rootpath " \
606 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
607 "console=$consoledev,$baudrate $othbootargs;" \
608 "tftp $loadaddr $bootfile;" \
609 "tftp $dtbaddr $dtbfile;" \
610 "bootm $loadaddr - $dtbaddr"
611
612#define CONFIG_RAMBOOTCOMMAND \
613 "setenv bootargs root=/dev/ram rw " \
614 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
615 "console=$consoledev,$baudrate $othbootargs;" \
616 "tftp $ramdiskaddr $ramdiskfile;" \
617 "tftp $loadaddr $bootfile;" \
618 "tftp $dtbaddr $dtbfile;" \
619 "bootm $loadaddr $ramdiskaddr $dtbaddr"
620
621#define CONFIG_FLASHBOOTCOMMAND \
622 "setenv bootargs root=/dev/ram rw " \
623 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
624 "console=$consoledev,$baudrate $othbootargs;" \
625 "bootm ffd00000 ffb00000 ffa00000"
626
627#define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND
628
629#endif
630