1/* 2 * include/asm-ppc/mpc5xxx.h 3 * 4 * Prototypes, etc. for the Motorola MPC5xxx 5 * embedded cpu chips 6 * 7 * 2003 (c) MontaVista, Software, Inc. 8 * Author: Dale Farnsworth <dfarnsworth@mvista.com> 9 * 10 * 2003 (C) Wolfgang Denk, DENX Software Engineering, wd@denx.de. 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30#ifndef __ASMPPC_MPC5XXX_H 31#define __ASMPPC_MPC5XXX_H 32 33#include <asm/types.h> 34 35/* Processor name */ 36#define CPU_ID_STR "MPC5200" 37 38/* Exception offsets (PowerPC standard) */ 39#define EXC_OFF_SYS_RESET 0x0100 40#define _START_OFFSET EXC_OFF_SYS_RESET 41 42/* useful macros for manipulating CSx_START/STOP */ 43#define START_REG(start) ((start) >> 16) 44#define STOP_REG(start, size) (((start) + (size) - 1) >> 16) 45 46/* Internal memory map */ 47 48#define MPC5XXX_CS0_START (CONFIG_SYS_MBAR + 0x0004) 49#define MPC5XXX_CS0_STOP (CONFIG_SYS_MBAR + 0x0008) 50#define MPC5XXX_CS1_START (CONFIG_SYS_MBAR + 0x000c) 51#define MPC5XXX_CS1_STOP (CONFIG_SYS_MBAR + 0x0010) 52#define MPC5XXX_CS2_START (CONFIG_SYS_MBAR + 0x0014) 53#define MPC5XXX_CS2_STOP (CONFIG_SYS_MBAR + 0x0018) 54#define MPC5XXX_CS3_START (CONFIG_SYS_MBAR + 0x001c) 55#define MPC5XXX_CS3_STOP (CONFIG_SYS_MBAR + 0x0020) 56#define MPC5XXX_CS4_START (CONFIG_SYS_MBAR + 0x0024) 57#define MPC5XXX_CS4_STOP (CONFIG_SYS_MBAR + 0x0028) 58#define MPC5XXX_CS5_START (CONFIG_SYS_MBAR + 0x002c) 59#define MPC5XXX_CS5_STOP (CONFIG_SYS_MBAR + 0x0030) 60#define MPC5XXX_BOOTCS_START (CONFIG_SYS_MBAR + 0x004c) 61#define MPC5XXX_BOOTCS_STOP (CONFIG_SYS_MBAR + 0x0050) 62#define MPC5XXX_ADDECR (CONFIG_SYS_MBAR + 0x0054) 63 64#define MPC5XXX_CS6_START (CONFIG_SYS_MBAR + 0x0058) 65#define MPC5XXX_CS6_STOP (CONFIG_SYS_MBAR + 0x005c) 66#define MPC5XXX_CS7_START (CONFIG_SYS_MBAR + 0x0060) 67#define MPC5XXX_CS7_STOP (CONFIG_SYS_MBAR + 0x0064) 68#define MPC5XXX_SDRAM_CS0CFG (CONFIG_SYS_MBAR + 0x0034) 69#define MPC5XXX_SDRAM_CS1CFG (CONFIG_SYS_MBAR + 0x0038) 70 71#define MPC5XXX_SDRAM (CONFIG_SYS_MBAR + 0x0100) 72#define MPC5XXX_CDM (CONFIG_SYS_MBAR + 0x0200) 73#define MPC5XXX_LPB (CONFIG_SYS_MBAR + 0x0300) 74#define MPC5XXX_ICTL (CONFIG_SYS_MBAR + 0x0500) 75#define MPC5XXX_GPT (CONFIG_SYS_MBAR + 0x0600) 76#define MPC5XXX_GPIO (CONFIG_SYS_MBAR + 0x0b00) 77#define MPC5XXX_WU_GPIO (CONFIG_SYS_MBAR + 0x0c00) 78#define MPC5XXX_PCI (CONFIG_SYS_MBAR + 0x0d00) 79#define MPC5XXX_SPI (CONFIG_SYS_MBAR + 0x0f00) 80#define MPC5XXX_USB (CONFIG_SYS_MBAR + 0x1000) 81#define MPC5XXX_SDMA (CONFIG_SYS_MBAR + 0x1200) 82#define MPC5XXX_XLBARB (CONFIG_SYS_MBAR + 0x1f00) 83 84#define MPC5XXX_PSC1 (CONFIG_SYS_MBAR + 0x2000) 85#define MPC5XXX_PSC2 (CONFIG_SYS_MBAR + 0x2200) 86#define MPC5XXX_PSC3 (CONFIG_SYS_MBAR + 0x2400) 87#define MPC5XXX_PSC4 (CONFIG_SYS_MBAR + 0x2600) 88#define MPC5XXX_PSC5 (CONFIG_SYS_MBAR + 0x2800) 89#define MPC5XXX_PSC6 (CONFIG_SYS_MBAR + 0x2c00) 90 91#define MPC5XXX_FEC (CONFIG_SYS_MBAR + 0x3000) 92#define MPC5XXX_ATA (CONFIG_SYS_MBAR + 0x3A00) 93 94#define MPC5XXX_I2C1 (CONFIG_SYS_MBAR + 0x3D00) 95#define MPC5XXX_I2C2 (CONFIG_SYS_MBAR + 0x3D40) 96 97#define MPC5XXX_SRAM (CONFIG_SYS_MBAR + 0x8000) 98#define MPC5XXX_SRAM_SIZE (16*1024) 99 100/* SDRAM Controller */ 101#define MPC5XXX_SDRAM_MODE (MPC5XXX_SDRAM + 0x0000) 102#define MPC5XXX_SDRAM_CTRL (MPC5XXX_SDRAM + 0x0004) 103#define MPC5XXX_SDRAM_CONFIG1 (MPC5XXX_SDRAM + 0x0008) 104#define MPC5XXX_SDRAM_CONFIG2 (MPC5XXX_SDRAM + 0x000c) 105#define MPC5XXX_SDRAM_SDELAY (MPC5XXX_SDRAM + 0x0090) 106 107/* Clock Distribution Module */ 108#define MPC5XXX_CDM_JTAGID (MPC5XXX_CDM + 0x0000) 109#define MPC5XXX_CDM_PORCFG (MPC5XXX_CDM + 0x0004) 110#define MPC5XXX_CDM_BRDCRMB (MPC5XXX_CDM + 0x0008) 111#define MPC5XXX_CDM_CFG (MPC5XXX_CDM + 0x000c) 112#define MPC5XXX_CDM_48_FDC (MPC5XXX_CDM + 0x0010) 113#define MPC5XXX_CDM_CLK_ENA (MPC5XXX_CDM + 0x0014) 114#define MPC5XXX_CDM_SRESET (MPC5XXX_CDM + 0x0020) 115 116/* Local Plus Bus interface */ 117#define MPC5XXX_CS0_CFG (MPC5XXX_LPB + 0x0000) 118#define MPC5XXX_CS1_CFG (MPC5XXX_LPB + 0x0004) 119#define MPC5XXX_CS2_CFG (MPC5XXX_LPB + 0x0008) 120#define MPC5XXX_CS3_CFG (MPC5XXX_LPB + 0x000c) 121#define MPC5XXX_CS4_CFG (MPC5XXX_LPB + 0x0010) 122#define MPC5XXX_CS5_CFG (MPC5XXX_LPB + 0x0014) 123#define MPC5XXX_BOOTCS_CFG MPC5XXX_CS0_CFG 124#define MPC5XXX_CS_CTRL (MPC5XXX_LPB + 0x0018) 125#define MPC5XXX_CS_STATUS (MPC5XXX_LPB + 0x001c) 126#define MPC5XXX_CS6_CFG (MPC5XXX_LPB + 0x0020) 127#define MPC5XXX_CS7_CFG (MPC5XXX_LPB + 0x0024) 128#define MPC5XXX_CS_BURST (MPC5XXX_LPB + 0x0028) 129#define MPC5XXX_CS_DEADCYCLE (MPC5XXX_LPB + 0x002c) 130 131/* XLB Arbiter registers */ 132#define MPC5XXX_XLBARB_CFG (MPC5XXX_XLBARB + 0x40) 133#define MPC5XXX_XLBARB_MPRIEN (MPC5XXX_XLBARB + 0x64) 134#define MPC5XXX_XLBARB_MPRIVAL (MPC5XXX_XLBARB + 0x68) 135 136/* GPIO registers */ 137#define MPC5XXX_GPS_PORT_CONFIG (MPC5XXX_GPIO + 0x0000) 138 139/* Standard GPIO registers (simple, output only and simple interrupt */ 140#define MPC5XXX_GPIO_ENABLE (MPC5XXX_GPIO + 0x0004) 141#define MPC5XXX_GPIO_ODE (MPC5XXX_GPIO + 0x0008) 142#define MPC5XXX_GPIO_DIR (MPC5XXX_GPIO + 0x000c) 143#define MPC5XXX_GPIO_DATA_O (MPC5XXX_GPIO + 0x0010) 144#define MPC5XXX_GPIO_DATA_I (MPC5XXX_GPIO + 0x0014) 145#define MPC5XXX_GPIO_OO_ENABLE (MPC5XXX_GPIO + 0x0018) 146#define MPC5XXX_GPIO_OO_DATA (MPC5XXX_GPIO + 0x001C) 147#define MPC5XXX_GPIO_SI_ENABLE (MPC5XXX_GPIO + 0x0020) 148#define MPC5XXX_GPIO_SI_ODE (MPC5XXX_GPIO + 0x0024) 149#define MPC5XXX_GPIO_SI_DIR (MPC5XXX_GPIO + 0x0028) 150#define MPC5XXX_GPIO_SI_DATA (MPC5XXX_GPIO + 0x002C) 151#define MPC5XXX_GPIO_SI_IEN (MPC5XXX_GPIO + 0x0030) 152#define MPC5XXX_GPIO_SI_ITYPE (MPC5XXX_GPIO + 0x0034) 153#define MPC5XXX_GPIO_SI_MEN (MPC5XXX_GPIO + 0x0038) 154#define MPC5XXX_GPIO_SI_STATUS (MPC5XXX_GPIO + 0x003C) 155 156/* WakeUp GPIO registers */ 157#define MPC5XXX_WU_GPIO_ENABLE (MPC5XXX_WU_GPIO + 0x0000) 158#define MPC5XXX_WU_GPIO_ODE (MPC5XXX_WU_GPIO + 0x0004) 159#define MPC5XXX_WU_GPIO_DIR (MPC5XXX_WU_GPIO + 0x0008) 160#define MPC5XXX_WU_GPIO_DATA_O (MPC5XXX_WU_GPIO + 0x000c) 161#define MPC5XXX_WU_GPIO_DATA_I (MPC5XXX_WU_GPIO + 0x0020) 162 163/* GPIO pins */ 164#define GPIO_WKUP_7 0x80000000UL 165#define GPIO_PSC6_0 0x10000000UL 166#define GPIO_PSC3_9 0x04000000UL 167#define GPIO_PSC1_4 0x01000000UL 168 169#define MPC5XXX_GPIO_SIMPLE_PSC6_3 0x20000000UL 170#define MPC5XXX_GPIO_SIMPLE_PSC6_2 0x10000000UL 171#define MPC5XXX_GPIO_SIMPLE_PSC3_7 0x00002000UL 172#define MPC5XXX_GPIO_SIMPLE_PSC3_6 0x00001000UL 173#define MPC5XXX_GPIO_SIMPLE_PSC3_3 0x00000800UL 174#define MPC5XXX_GPIO_SIMPLE_PSC3_2 0x00000400UL 175#define MPC5XXX_GPIO_SIMPLE_PSC3_1 0x00000200UL 176#define MPC5XXX_GPIO_SIMPLE_PSC3_0 0x00000100UL 177#define MPC5XXX_GPIO_SIMPLE_PSC2_3 0x00000080UL 178#define MPC5XXX_GPIO_SIMPLE_PSC2_2 0x00000040UL 179#define MPC5XXX_GPIO_SIMPLE_PSC2_1 0x00000020UL 180#define MPC5XXX_GPIO_SIMPLE_PSC2_0 0x00000010UL 181#define MPC5XXX_GPIO_SIMPLE_PSC1_3 0x00000008UL 182#define MPC5XXX_GPIO_SIMPLE_PSC1_2 0x00000004UL 183#define MPC5XXX_GPIO_SIMPLE_PSC1_1 0x00000002UL 184#define MPC5XXX_GPIO_SIMPLE_PSC1_0 0x00000001UL 185 186#define MPC5XXX_GPIO_SINT_ETH_16 0x80 187#define MPC5XXX_GPIO_SINT_ETH_15 0x40 188#define MPC5XXX_GPIO_SINT_ETH_14 0x20 189#define MPC5XXX_GPIO_SINT_ETH_13 0x10 190#define MPC5XXX_GPIO_SINT_USB1_9 0x08 191#define MPC5XXX_GPIO_SINT_PSC3_8 0x04 192#define MPC5XXX_GPIO_SINT_PSC3_5 0x02 193#define MPC5XXX_GPIO_SINT_PSC3_4 0x01 194 195#define MPC5XXX_GPIO_WKUP_7 0x80 196#define MPC5XXX_GPIO_WKUP_6 0x40 197#define MPC5XXX_GPIO_WKUP_PSC6_1 0x20 198#define MPC5XXX_GPIO_WKUP_PSC6_0 0x10 199#define MPC5XXX_GPIO_WKUP_ETH17 0x08 200#define MPC5XXX_GPIO_WKUP_PSC3_9 0x04 201#define MPC5XXX_GPIO_WKUP_PSC2_4 0x02 202#define MPC5XXX_GPIO_WKUP_PSC1_4 0x01 203 204/* PCI registers */ 205#define MPC5XXX_PCI_CMD (MPC5XXX_PCI + 0x04) 206#define MPC5XXX_PCI_CFG (MPC5XXX_PCI + 0x0c) 207#define MPC5XXX_PCI_BAR0 (MPC5XXX_PCI + 0x10) 208#define MPC5XXX_PCI_BAR1 (MPC5XXX_PCI + 0x14) 209#define MPC5XXX_PCI_GSCR (MPC5XXX_PCI + 0x60) 210#define MPC5XXX_PCI_TBATR0 (MPC5XXX_PCI + 0x64) 211#define MPC5XXX_PCI_TBATR1 (MPC5XXX_PCI + 0x68) 212#define MPC5XXX_PCI_TCR (MPC5XXX_PCI + 0x6c) 213#define MPC5XXX_PCI_IW0BTAR (MPC5XXX_PCI + 0x70) 214#define MPC5XXX_PCI_IW1BTAR (MPC5XXX_PCI + 0x74) 215#define MPC5XXX_PCI_IW2BTAR (MPC5XXX_PCI + 0x78) 216#define MPC5XXX_PCI_IWCR (MPC5XXX_PCI + 0x80) 217#define MPC5XXX_PCI_ICR (MPC5XXX_PCI + 0x84) 218#define MPC5XXX_PCI_ISR (MPC5XXX_PCI + 0x88) 219#define MPC5XXX_PCI_ARB (MPC5XXX_PCI + 0x8c) 220#define MPC5XXX_PCI_CAR (MPC5XXX_PCI + 0xf8) 221 222/* Interrupt Controller registers */ 223#define MPC5XXX_ICTL_PER_MASK (MPC5XXX_ICTL + 0x0000) 224#define MPC5XXX_ICTL_PER_PRIO1 (MPC5XXX_ICTL + 0x0004) 225#define MPC5XXX_ICTL_PER_PRIO2 (MPC5XXX_ICTL + 0x0008) 226#define MPC5XXX_ICTL_PER_PRIO3 (MPC5XXX_ICTL + 0x000c) 227#define MPC5XXX_ICTL_EXT (MPC5XXX_ICTL + 0x0010) 228#define MPC5XXX_ICTL_CRIT (MPC5XXX_ICTL + 0x0014) 229#define MPC5XXX_ICTL_MAIN_PRIO1 (MPC5XXX_ICTL + 0x0018) 230#define MPC5XXX_ICTL_MAIN_PRIO2 (MPC5XXX_ICTL + 0x001c) 231#define MPC5XXX_ICTL_STS (MPC5XXX_ICTL + 0x0024) 232#define MPC5XXX_ICTL_CRIT_STS (MPC5XXX_ICTL + 0x0028) 233#define MPC5XXX_ICTL_MAIN_STS (MPC5XXX_ICTL + 0x002c) 234#define MPC5XXX_ICTL_PER_STS (MPC5XXX_ICTL + 0x0030) 235#define MPC5XXX_ICTL_BUS_STS (MPC5XXX_ICTL + 0x0038) 236 237#define NR_IRQS 64 238 239/* IRQ mapping - these are our logical IRQ numbers */ 240#define MPC5XXX_CRIT_IRQ_NUM 4 241#define MPC5XXX_MAIN_IRQ_NUM 17 242#define MPC5XXX_SDMA_IRQ_NUM 17 243#define MPC5XXX_PERP_IRQ_NUM 23 244 245#define MPC5XXX_CRIT_IRQ_BASE 1 246#define MPC5XXX_MAIN_IRQ_BASE (MPC5XXX_CRIT_IRQ_BASE + MPC5XXX_CRIT_IRQ_NUM) 247#define MPC5XXX_SDMA_IRQ_BASE (MPC5XXX_MAIN_IRQ_BASE + MPC5XXX_MAIN_IRQ_NUM) 248#define MPC5XXX_PERP_IRQ_BASE (MPC5XXX_SDMA_IRQ_BASE + MPC5XXX_SDMA_IRQ_NUM) 249 250#define MPC5XXX_IRQ0 (MPC5XXX_CRIT_IRQ_BASE + 0) 251#define MPC5XXX_SLICE_TIMER_0_IRQ (MPC5XXX_CRIT_IRQ_BASE + 1) 252#define MPC5XXX_HI_INT_IRQ (MPC5XXX_CRIT_IRQ_BASE + 2) 253#define MPC5XXX_CCS_IRQ (MPC5XXX_CRIT_IRQ_BASE + 3) 254 255#define MPC5XXX_IRQ1 (MPC5XXX_MAIN_IRQ_BASE + 1) 256#define MPC5XXX_IRQ2 (MPC5XXX_MAIN_IRQ_BASE + 2) 257#define MPC5XXX_IRQ3 (MPC5XXX_MAIN_IRQ_BASE + 3) 258#define MPC5XXX_RTC_PINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 5) 259#define MPC5XXX_RTC_SINT_IRQ (MPC5XXX_MAIN_IRQ_BASE + 6) 260#define MPC5XXX_RTC_GPIO_STD_IRQ (MPC5XXX_MAIN_IRQ_BASE + 7) 261#define MPC5XXX_RTC_GPIO_WKUP_IRQ (MPC5XXX_MAIN_IRQ_BASE + 8) 262#define MPC5XXX_TMR0_IRQ (MPC5XXX_MAIN_IRQ_BASE + 9) 263#define MPC5XXX_TMR1_IRQ (MPC5XXX_MAIN_IRQ_BASE + 10) 264#define MPC5XXX_TMR2_IRQ (MPC5XXX_MAIN_IRQ_BASE + 11) 265#define MPC5XXX_TMR3_IRQ (MPC5XXX_MAIN_IRQ_BASE + 12) 266#define MPC5XXX_TMR4_IRQ (MPC5XXX_MAIN_IRQ_BASE + 13) 267#define MPC5XXX_TMR5_IRQ (MPC5XXX_MAIN_IRQ_BASE + 14) 268#define MPC5XXX_TMR6_IRQ (MPC5XXX_MAIN_IRQ_BASE + 15) 269#define MPC5XXX_TMR7_IRQ (MPC5XXX_MAIN_IRQ_BASE + 16) 270 271#define MPC5XXX_SDMA_IRQ (MPC5XXX_PERP_IRQ_BASE + 0) 272#define MPC5XXX_PSC1_IRQ (MPC5XXX_PERP_IRQ_BASE + 1) 273#define MPC5XXX_PSC2_IRQ (MPC5XXX_PERP_IRQ_BASE + 2) 274#define MPC5XXX_PSC3_IRQ (MPC5XXX_PERP_IRQ_BASE + 3) 275#define MPC5XXX_PSC6_IRQ (MPC5XXX_PERP_IRQ_BASE + 4) 276#define MPC5XXX_IRDA_IRQ (MPC5XXX_PERP_IRQ_BASE + 4) 277#define MPC5XXX_FEC_IRQ (MPC5XXX_PERP_IRQ_BASE + 5) 278#define MPC5XXX_USB_IRQ (MPC5XXX_PERP_IRQ_BASE + 6) 279#define MPC5XXX_ATA_IRQ (MPC5XXX_PERP_IRQ_BASE + 7) 280#define MPC5XXX_PCI_CNTRL_IRQ (MPC5XXX_PERP_IRQ_BASE + 8) 281#define MPC5XXX_PCI_SCIRX_IRQ (MPC5XXX_PERP_IRQ_BASE + 9) 282#define MPC5XXX_PCI_SCITX_IRQ (MPC5XXX_PERP_IRQ_BASE + 10) 283#define MPC5XXX_PSC4_IRQ (MPC5XXX_PERP_IRQ_BASE + 11) 284#define MPC5XXX_PSC5_IRQ (MPC5XXX_PERP_IRQ_BASE + 12) 285#define MPC5XXX_SPI_MODF_IRQ (MPC5XXX_PERP_IRQ_BASE + 13) 286#define MPC5XXX_SPI_SPIF_IRQ (MPC5XXX_PERP_IRQ_BASE + 14) 287#define MPC5XXX_I2C1_IRQ (MPC5XXX_PERP_IRQ_BASE + 15) 288#define MPC5XXX_I2C2_IRQ (MPC5XXX_PERP_IRQ_BASE + 16) 289#define MPC5XXX_MSCAN1_IRQ (MPC5XXX_PERP_IRQ_BASE + 17) 290#define MPC5XXX_MSCAN2_IRQ (MPC5XXX_PERP_IRQ_BASE + 18) 291#define MPC5XXX_IR_RX_IRQ (MPC5XXX_PERP_IRQ_BASE + 19) 292#define MPC5XXX_IR_TX_IRQ (MPC5XXX_PERP_IRQ_BASE + 20) 293#define MPC5XXX_XLB_ARB_IRQ (MPC5XXX_PERP_IRQ_BASE + 21) 294#define MPC5XXX_BDLC_IRQ (MPC5XXX_PERP_IRQ_BASE + 22) 295 296/* General Purpose Timers registers */ 297#define MPC5XXX_GPT0_ENABLE (MPC5XXX_GPT + 0x0) 298#define MPC5XXX_GPT0_COUNTER (MPC5XXX_GPT + 0x4) 299#define MPC5XXX_GPT0_STATUS (MPC5XXX_GPT + 0x0C) 300#define MPC5XXX_GPT1_ENABLE (MPC5XXX_GPT + 0x10) 301#define MPC5XXX_GPT1_COUNTER (MPC5XXX_GPT + 0x14) 302#define MPC5XXX_GPT1_STATUS (MPC5XXX_GPT + 0x1C) 303#define MPC5XXX_GPT2_ENABLE (MPC5XXX_GPT + 0x20) 304#define MPC5XXX_GPT2_COUNTER (MPC5XXX_GPT + 0x24) 305#define MPC5XXX_GPT2_STATUS (MPC5XXX_GPT + 0x2C) 306#define MPC5XXX_GPT3_ENABLE (MPC5XXX_GPT + 0x30) 307#define MPC5XXX_GPT3_COUNTER (MPC5XXX_GPT + 0x34) 308#define MPC5XXX_GPT3_STATUS (MPC5XXX_GPT + 0x3C) 309#define MPC5XXX_GPT4_ENABLE (MPC5XXX_GPT + 0x40) 310#define MPC5XXX_GPT4_COUNTER (MPC5XXX_GPT + 0x44) 311#define MPC5XXX_GPT4_STATUS (MPC5XXX_GPT + 0x4C) 312#define MPC5XXX_GPT5_ENABLE (MPC5XXX_GPT + 0x50) 313#define MPC5XXX_GPT5_STATUS (MPC5XXX_GPT + 0x5C) 314#define MPC5XXX_GPT5_COUNTER (MPC5XXX_GPT + 0x54) 315#define MPC5XXX_GPT6_ENABLE (MPC5XXX_GPT + 0x60) 316#define MPC5XXX_GPT6_COUNTER (MPC5XXX_GPT + 0x64) 317#define MPC5XXX_GPT6_STATUS (MPC5XXX_GPT + 0x6C) 318#define MPC5XXX_GPT7_ENABLE (MPC5XXX_GPT + 0x70) 319#define MPC5XXX_GPT7_COUNTER (MPC5XXX_GPT + 0x74) 320#define MPC5XXX_GPT7_STATUS (MPC5XXX_GPT + 0x7C) 321 322#define MPC5XXX_GPT_GPIO_PIN(status) ((0x00000100 & (status)) >> 8) 323 324#define MPC5XXX_GPT7_PWMCFG (MPC5XXX_GPT + 0x78) 325 326/* ATA registers */ 327#define MPC5XXX_ATA_HOST_CONFIG (MPC5XXX_ATA + 0x0000) 328#define MPC5XXX_ATA_PIO1 (MPC5XXX_ATA + 0x0008) 329#define MPC5XXX_ATA_PIO2 (MPC5XXX_ATA + 0x000C) 330#define MPC5XXX_ATA_SHARE_COUNT (MPC5XXX_ATA + 0x002C) 331 332/* I2Cn control register bits */ 333#define I2C_EN 0x80 334#define I2C_IEN 0x40 335#define I2C_STA 0x20 336#define I2C_TX 0x10 337#define I2C_TXAK 0x08 338#define I2C_RSTA 0x04 339#define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA) 340 341/* I2Cn status register bits */ 342#define I2C_CF 0x80 343#define I2C_AAS 0x40 344#define I2C_BB 0x20 345#define I2C_AL 0x10 346#define I2C_SRW 0x04 347#define I2C_IF 0x02 348#define I2C_RXAK 0x01 349 350/* SPI control register 1 bits */ 351#define SPI_CR_LSBFE 0x01 352#define SPI_CR_SSOE 0x02 353#define SPI_CR_CPHA 0x04 354#define SPI_CR_CPOL 0x08 355#define SPI_CR_MSTR 0x10 356#define SPI_CR_SWOM 0x20 357#define SPI_CR_SPE 0x40 358#define SPI_CR_SPIE 0x80 359 360/* SPI status register bits */ 361#define SPI_SR_MODF 0x10 362#define SPI_SR_WCOL 0x40 363#define SPI_SR_SPIF 0x80 364 365/* SPI port data register bits */ 366#define SPI_PDR_SS 0x08 367 368/* Programmable Serial Controller (PSC) status register bits */ 369#define PSC_SR_CDE 0x0080 370#define PSC_SR_RXRDY 0x0100 371#define PSC_SR_RXFULL 0x0200 372#define PSC_SR_TXRDY 0x0400 373#define PSC_SR_TXEMP 0x0800 374#define PSC_SR_OE 0x1000 375#define PSC_SR_PE 0x2000 376#define PSC_SR_FE 0x4000 377#define PSC_SR_RB 0x8000 378 379/* PSC Command values */ 380#define PSC_RX_ENABLE 0x0001 381#define PSC_RX_DISABLE 0x0002 382#define PSC_TX_ENABLE 0x0004 383#define PSC_TX_DISABLE 0x0008 384#define PSC_SEL_MODE_REG_1 0x0010 385#define PSC_RST_RX 0x0020 386#define PSC_RST_TX 0x0030 387#define PSC_RST_ERR_STAT 0x0040 388#define PSC_RST_BRK_CHG_INT 0x0050 389#define PSC_START_BRK 0x0060 390#define PSC_STOP_BRK 0x0070 391 392/* PSC Rx FIFO status bits */ 393#define PSC_RX_FIFO_ERR 0x0040 394#define PSC_RX_FIFO_UF 0x0020 395#define PSC_RX_FIFO_OF 0x0010 396#define PSC_RX_FIFO_FR 0x0008 397#define PSC_RX_FIFO_FULL 0x0004 398#define PSC_RX_FIFO_ALARM 0x0002 399#define PSC_RX_FIFO_EMPTY 0x0001 400 401/* PSC interrupt mask bits */ 402#define PSC_IMR_TXRDY 0x0100 403#define PSC_IMR_RXRDY 0x0200 404#define PSC_IMR_DB 0x0400 405#define PSC_IMR_IPC 0x8000 406 407/* PSC input port change bits */ 408#define PSC_IPCR_CTS 0x01 409#define PSC_IPCR_DCD 0x02 410 411/* PSC mode fields */ 412#define PSC_MODE_5_BITS 0x00 413#define PSC_MODE_6_BITS 0x01 414#define PSC_MODE_7_BITS 0x02 415#define PSC_MODE_8_BITS 0x03 416#define PSC_MODE_PAREVEN 0x00 417#define PSC_MODE_PARODD 0x04 418#define PSC_MODE_PARFORCE 0x08 419#define PSC_MODE_PARNONE 0x10 420#define PSC_MODE_ERR 0x20 421#define PSC_MODE_FFULL 0x40 422#define PSC_MODE_RXRTS 0x80 423 424#define PSC_MODE_ONE_STOP_5_BITS 0x00 425#define PSC_MODE_ONE_STOP 0x07 426#define PSC_MODE_TWO_STOP 0x0f 427 428/* ATA config fields */ 429#define MPC5xxx_ATA_HOSTCONF_SMR 0x80000000UL /* State machine 430 reset */ 431#define MPC5xxx_ATA_HOSTCONF_FR 0x40000000UL /* FIFO Reset */ 432#define MPC5xxx_ATA_HOSTCONF_IE 0x02000000UL /* Enable interrupt 433 in PIO */ 434#define MPC5xxx_ATA_HOSTCONF_IORDY 0x01000000UL /* Drive supports 435 IORDY protocol */ 436 437#ifndef __ASSEMBLY__ 438/* Memory map registers */ 439struct mpc5xxx_mmap_ctl { 440 volatile u32 mbar; 441 volatile u32 cs0_start; /* 0x0004 */ 442 volatile u32 cs0_stop; 443 volatile u32 cs1_start; /* 0x000c */ 444 volatile u32 cs1_stop; 445 volatile u32 cs2_start; /* 0x0014 */ 446 volatile u32 cs2_stop; 447 volatile u32 cs3_start; /* 0x001c */ 448 volatile u32 cs3_stop; 449 volatile u32 cs4_start; /* 0x0024 */ 450 volatile u32 cs4_stop; 451 volatile u32 cs5_start; /* 0x002c */ 452 volatile u32 cs5_stop; 453 volatile u32 sdram0; /* 0x0034 */ 454 volatile u32 sdram1; /* 0x0038 */ 455 volatile u32 dummy1[4]; /* 0x003c */ 456 volatile u32 boot_start; /* 0x004c */ 457 volatile u32 boot_stop; 458 volatile u32 ipbi_ws_ctrl; /* 0x0054 */ 459 volatile u32 cs6_start; /* 0x0058 */ 460 volatile u32 cs6_stop; 461 volatile u32 cs7_start; /* 0x0060 */ 462 volatile u32 cs7_stop; 463}; 464 465/* Clock distribution module */ 466struct mpc5xxx_cdm { 467 volatile u32 jtagid; /* 0x0000 */ 468 volatile u32 porcfg; 469 volatile u32 brdcrmb; /* 0x0008 */ 470 volatile u32 cfg; 471 volatile u32 fourtyeight_fdc;/* 0x0010 */ 472 volatile u32 clock_enable; 473 volatile u32 system_osc; /* 0x0018 */ 474 volatile u32 ccscr; 475 volatile u32 sreset; /* 0x0020 */ 476 volatile u32 pll_status; 477 volatile u32 psc1_mccr; /* 0x0028 */ 478 volatile u32 psc2_mccr; 479 volatile u32 psc3_mccr; /* 0x0030 */ 480 volatile u32 psc6_mccr; 481}; 482 483/* SDRAM controller */ 484struct mpc5xxx_sdram { 485 volatile u32 mode; 486 volatile u32 ctrl; 487 volatile u32 config1; 488 volatile u32 config2; 489 volatile u32 dummy[32]; 490 volatile u32 sdelay; 491}; 492 493struct mpc5xxx_lpb { 494 volatile u32 cs0_cfg; 495 volatile u32 cs1_cfg; 496 volatile u32 cs2_cfg; 497 volatile u32 cs3_cfg; 498 volatile u32 cs4_cfg; 499 volatile u32 cs5_cfg; 500 volatile u32 cs_ctrl; 501 volatile u32 cs_status; 502 volatile u32 cs6_cfg; 503 volatile u32 cs7_cfg; 504 volatile u32 cs_burst; 505 volatile u32 cs_deadcycle; 506}; 507 508 509struct mpc5xxx_psc { 510 volatile u8 mode; /* PSC + 0x00 */ 511 volatile u8 reserved0[3]; 512 union { /* PSC + 0x04 */ 513 volatile u16 status; 514 volatile u16 clock_select; 515 } sr_csr; 516#define psc_status sr_csr.status 517#define psc_clock_select sr_csr.clock_select 518 volatile u16 reserved1; 519 volatile u8 command; /* PSC + 0x08 */ 520 volatile u8 reserved2[3]; 521 union { /* PSC + 0x0c */ 522 volatile u8 buffer_8; 523 volatile u16 buffer_16; 524 volatile u32 buffer_32; 525 } buffer; 526#define psc_buffer_8 buffer.buffer_8 527#define psc_buffer_16 buffer.buffer_16 528#define psc_buffer_32 buffer.buffer_32 529 union { /* PSC + 0x10 */ 530 volatile u8 ipcr; 531 volatile u8 acr; 532 } ipcr_acr; 533#define psc_ipcr ipcr_acr.ipcr 534#define psc_acr ipcr_acr.acr 535 volatile u8 reserved3[3]; 536 union { /* PSC + 0x14 */ 537 volatile u16 isr; 538 volatile u16 imr; 539 } isr_imr; 540#define psc_isr isr_imr.isr 541#define psc_imr isr_imr.imr 542 volatile u16 reserved4; 543 volatile u8 ctur; /* PSC + 0x18 */ 544 volatile u8 reserved5[3]; 545 volatile u8 ctlr; /* PSC + 0x1c */ 546 volatile u8 reserved6[3]; 547 volatile u16 ccr; /* PSC + 0x20 */ 548 volatile u8 reserved7[14]; 549 volatile u8 ivr; /* PSC + 0x30 */ 550 volatile u8 reserved8[3]; 551 volatile u8 ip; /* PSC + 0x34 */ 552 volatile u8 reserved9[3]; 553 volatile u8 op1; /* PSC + 0x38 */ 554 volatile u8 reserved10[3]; 555 volatile u8 op0; /* PSC + 0x3c */ 556 volatile u8 reserved11[3]; 557 volatile u32 sicr; /* PSC + 0x40 */ 558 volatile u8 ircr1; /* PSC + 0x44 */ 559 volatile u8 reserved12[3]; 560 volatile u8 ircr2; /* PSC + 0x44 */ 561 volatile u8 reserved13[3]; 562 volatile u8 irsdr; /* PSC + 0x4c */ 563 volatile u8 reserved14[3]; 564 volatile u8 irmdr; /* PSC + 0x50 */ 565 volatile u8 reserved15[3]; 566 volatile u8 irfdr; /* PSC + 0x54 */ 567 volatile u8 reserved16[3]; 568 volatile u16 rfnum; /* PSC + 0x58 */ 569 volatile u16 reserved17; 570 volatile u16 tfnum; /* PSC + 0x5c */ 571 volatile u16 reserved18; 572 volatile u32 rfdata; /* PSC + 0x60 */ 573 volatile u16 rfstat; /* PSC + 0x64 */ 574 volatile u16 reserved20; 575 volatile u8 rfcntl; /* PSC + 0x68 */ 576 volatile u8 reserved21[5]; 577 volatile u16 rfalarm; /* PSC + 0x6e */ 578 volatile u16 reserved22; 579 volatile u16 rfrptr; /* PSC + 0x72 */ 580 volatile u16 reserved23; 581 volatile u16 rfwptr; /* PSC + 0x76 */ 582 volatile u16 reserved24; 583 volatile u16 rflrfptr; /* PSC + 0x7a */ 584 volatile u16 reserved25; 585 volatile u16 rflwfptr; /* PSC + 0x7e */ 586 volatile u32 tfdata; /* PSC + 0x80 */ 587 volatile u16 tfstat; /* PSC + 0x84 */ 588 volatile u16 reserved26; 589 volatile u8 tfcntl; /* PSC + 0x88 */ 590 volatile u8 reserved27[5]; 591 volatile u16 tfalarm; /* PSC + 0x8e */ 592 volatile u16 reserved28; 593 volatile u16 tfrptr; /* PSC + 0x92 */ 594 volatile u16 reserved29; 595 volatile u16 tfwptr; /* PSC + 0x96 */ 596 volatile u16 reserved30; 597 volatile u16 tflrfptr; /* PSC + 0x9a */ 598 volatile u16 reserved31; 599 volatile u16 tflwfptr; /* PSC + 0x9e */ 600}; 601 602struct mpc5xxx_intr { 603 volatile u32 per_mask; /* INTR + 0x00 */ 604 volatile u32 per_pri1; /* INTR + 0x04 */ 605 volatile u32 per_pri2; /* INTR + 0x08 */ 606 volatile u32 per_pri3; /* INTR + 0x0c */ 607 volatile u32 ctrl; /* INTR + 0x10 */ 608 volatile u32 main_mask; /* INTR + 0x14 */ 609 volatile u32 main_pri1; /* INTR + 0x18 */ 610 volatile u32 main_pri2; /* INTR + 0x1c */ 611 volatile u32 reserved1; /* INTR + 0x20 */ 612 volatile u32 enc_status; /* INTR + 0x24 */ 613 volatile u32 crit_status; /* INTR + 0x28 */ 614 volatile u32 main_status; /* INTR + 0x2c */ 615 volatile u32 per_status; /* INTR + 0x30 */ 616 volatile u32 reserved2; /* INTR + 0x34 */ 617 volatile u32 per_error; /* INTR + 0x38 */ 618}; 619 620struct mpc5xxx_gpio { 621 volatile u32 port_config; /* GPIO + 0x00 */ 622 volatile u32 simple_gpioe; /* GPIO + 0x04 */ 623 volatile u32 simple_ode; /* GPIO + 0x08 */ 624 volatile u32 simple_ddr; /* GPIO + 0x0c */ 625 volatile u32 simple_dvo; /* GPIO + 0x10 */ 626 volatile u32 simple_ival; /* GPIO + 0x14 */ 627 volatile u8 outo_gpioe; /* GPIO + 0x18 */ 628 volatile u8 reserved1[3]; /* GPIO + 0x19 */ 629 volatile u8 outo_dvo; /* GPIO + 0x1c */ 630 volatile u8 reserved2[3]; /* GPIO + 0x1d */ 631 volatile u8 sint_gpioe; /* GPIO + 0x20 */ 632 volatile u8 reserved3[3]; /* GPIO + 0x21 */ 633 volatile u8 sint_ode; /* GPIO + 0x24 */ 634 volatile u8 reserved4[3]; /* GPIO + 0x25 */ 635 volatile u8 sint_ddr; /* GPIO + 0x28 */ 636 volatile u8 reserved5[3]; /* GPIO + 0x29 */ 637 volatile u8 sint_dvo; /* GPIO + 0x2c */ 638 volatile u8 reserved6[3]; /* GPIO + 0x2d */ 639 volatile u8 sint_inten; /* GPIO + 0x30 */ 640 volatile u8 reserved7[3]; /* GPIO + 0x31 */ 641 volatile u16 sint_itype; /* GPIO + 0x34 */ 642 volatile u16 reserved8; /* GPIO + 0x36 */ 643 volatile u8 gpio_control; /* GPIO + 0x38 */ 644 volatile u8 reserved9[3]; /* GPIO + 0x39 */ 645 volatile u8 sint_istat; /* GPIO + 0x3c */ 646 volatile u8 sint_ival; /* GPIO + 0x3d */ 647 volatile u8 bus_errs; /* GPIO + 0x3e */ 648 volatile u8 reserved10; /* GPIO + 0x3f */ 649}; 650 651struct mpc5xxx_wu_gpio { 652 volatile u8 enable; /* WU_GPIO + 0x00 */ 653 volatile u8 reserved1[3]; /* WU_GPIO + 0x01 */ 654 volatile u8 ode; /* WU_GPIO + 0x04 */ 655 volatile u8 reserved2[3]; /* WU_GPIO + 0x05 */ 656 volatile u8 ddr; /* WU_GPIO + 0x08 */ 657 volatile u8 reserved3[3]; /* WU_GPIO + 0x09 */ 658 volatile u8 dvo; /* WU_GPIO + 0x0c */ 659 volatile u8 reserved4[3]; /* WU_GPIO + 0x0d */ 660 volatile u8 inten; /* WU_GPIO + 0x10 */ 661 volatile u8 reserved5[3]; /* WU_GPIO + 0x11 */ 662 volatile u8 iinten; /* WU_GPIO + 0x14 */ 663 volatile u8 reserved6[3]; /* WU_GPIO + 0x15 */ 664 volatile u16 itype; /* WU_GPIO + 0x18 */ 665 volatile u8 reserved7[2]; /* WU_GPIO + 0x1a */ 666 volatile u8 master_enable; /* WU_GPIO + 0x1c */ 667 volatile u8 reserved8[3]; /* WU_GPIO + 0x1d */ 668 volatile u8 ival; /* WU_GPIO + 0x20 */ 669 volatile u8 reserved9[3]; /* WU_GPIO + 0x21 */ 670 volatile u8 status; /* WU_GPIO + 0x24 */ 671 volatile u8 reserved10[3]; /* WU_GPIO + 0x25 */ 672}; 673 674struct mpc5xxx_sdma { 675 volatile u32 taskBar; /* SDMA + 0x00 */ 676 volatile u32 currentPointer; /* SDMA + 0x04 */ 677 volatile u32 endPointer; /* SDMA + 0x08 */ 678 volatile u32 variablePointer; /* SDMA + 0x0c */ 679 680 volatile u8 IntVect1; /* SDMA + 0x10 */ 681 volatile u8 IntVect2; /* SDMA + 0x11 */ 682 volatile u16 PtdCntrl; /* SDMA + 0x12 */ 683 684 volatile u32 IntPend; /* SDMA + 0x14 */ 685 volatile u32 IntMask; /* SDMA + 0x18 */ 686 687 volatile u16 tcr_0; /* SDMA + 0x1c */ 688 volatile u16 tcr_1; /* SDMA + 0x1e */ 689 volatile u16 tcr_2; /* SDMA + 0x20 */ 690 volatile u16 tcr_3; /* SDMA + 0x22 */ 691 volatile u16 tcr_4; /* SDMA + 0x24 */ 692 volatile u16 tcr_5; /* SDMA + 0x26 */ 693 volatile u16 tcr_6; /* SDMA + 0x28 */ 694 volatile u16 tcr_7; /* SDMA + 0x2a */ 695 volatile u16 tcr_8; /* SDMA + 0x2c */ 696 volatile u16 tcr_9; /* SDMA + 0x2e */ 697 volatile u16 tcr_a; /* SDMA + 0x30 */ 698 volatile u16 tcr_b; /* SDMA + 0x32 */ 699 volatile u16 tcr_c; /* SDMA + 0x34 */ 700 volatile u16 tcr_d; /* SDMA + 0x36 */ 701 volatile u16 tcr_e; /* SDMA + 0x38 */ 702 volatile u16 tcr_f; /* SDMA + 0x3a */ 703 704 volatile u8 IPR0; /* SDMA + 0x3c */ 705 volatile u8 IPR1; /* SDMA + 0x3d */ 706 volatile u8 IPR2; /* SDMA + 0x3e */ 707 volatile u8 IPR3; /* SDMA + 0x3f */ 708 volatile u8 IPR4; /* SDMA + 0x40 */ 709 volatile u8 IPR5; /* SDMA + 0x41 */ 710 volatile u8 IPR6; /* SDMA + 0x42 */ 711 volatile u8 IPR7; /* SDMA + 0x43 */ 712 volatile u8 IPR8; /* SDMA + 0x44 */ 713 volatile u8 IPR9; /* SDMA + 0x45 */ 714 volatile u8 IPR10; /* SDMA + 0x46 */ 715 volatile u8 IPR11; /* SDMA + 0x47 */ 716 volatile u8 IPR12; /* SDMA + 0x48 */ 717 volatile u8 IPR13; /* SDMA + 0x49 */ 718 volatile u8 IPR14; /* SDMA + 0x4a */ 719 volatile u8 IPR15; /* SDMA + 0x4b */ 720 volatile u8 IPR16; /* SDMA + 0x4c */ 721 volatile u8 IPR17; /* SDMA + 0x4d */ 722 volatile u8 IPR18; /* SDMA + 0x4e */ 723 volatile u8 IPR19; /* SDMA + 0x4f */ 724 volatile u8 IPR20; /* SDMA + 0x50 */ 725 volatile u8 IPR21; /* SDMA + 0x51 */ 726 volatile u8 IPR22; /* SDMA + 0x52 */ 727 volatile u8 IPR23; /* SDMA + 0x53 */ 728 volatile u8 IPR24; /* SDMA + 0x54 */ 729 volatile u8 IPR25; /* SDMA + 0x55 */ 730 volatile u8 IPR26; /* SDMA + 0x56 */ 731 volatile u8 IPR27; /* SDMA + 0x57 */ 732 volatile u8 IPR28; /* SDMA + 0x58 */ 733 volatile u8 IPR29; /* SDMA + 0x59 */ 734 volatile u8 IPR30; /* SDMA + 0x5a */ 735 volatile u8 IPR31; /* SDMA + 0x5b */ 736 737 volatile u32 res1; /* SDMA + 0x5c */ 738 volatile u32 res2; /* SDMA + 0x60 */ 739 volatile u32 res3; /* SDMA + 0x64 */ 740 volatile u32 MDEDebug; /* SDMA + 0x68 */ 741 volatile u32 ADSDebug; /* SDMA + 0x6c */ 742 volatile u32 Value1; /* SDMA + 0x70 */ 743 volatile u32 Value2; /* SDMA + 0x74 */ 744 volatile u32 Control; /* SDMA + 0x78 */ 745 volatile u32 Status; /* SDMA + 0x7c */ 746 volatile u32 EU00; /* SDMA + 0x80 */ 747 volatile u32 EU01; /* SDMA + 0x84 */ 748 volatile u32 EU02; /* SDMA + 0x88 */ 749 volatile u32 EU03; /* SDMA + 0x8c */ 750 volatile u32 EU04; /* SDMA + 0x90 */ 751 volatile u32 EU05; /* SDMA + 0x94 */ 752 volatile u32 EU06; /* SDMA + 0x98 */ 753 volatile u32 EU07; /* SDMA + 0x9c */ 754 volatile u32 EU10; /* SDMA + 0xa0 */ 755 volatile u32 EU11; /* SDMA + 0xa4 */ 756 volatile u32 EU12; /* SDMA + 0xa8 */ 757 volatile u32 EU13; /* SDMA + 0xac */ 758 volatile u32 EU14; /* SDMA + 0xb0 */ 759 volatile u32 EU15; /* SDMA + 0xb4 */ 760 volatile u32 EU16; /* SDMA + 0xb8 */ 761 volatile u32 EU17; /* SDMA + 0xbc */ 762 volatile u32 EU20; /* SDMA + 0xc0 */ 763 volatile u32 EU21; /* SDMA + 0xc4 */ 764 volatile u32 EU22; /* SDMA + 0xc8 */ 765 volatile u32 EU23; /* SDMA + 0xcc */ 766 volatile u32 EU24; /* SDMA + 0xd0 */ 767 volatile u32 EU25; /* SDMA + 0xd4 */ 768 volatile u32 EU26; /* SDMA + 0xd8 */ 769 volatile u32 EU27; /* SDMA + 0xdc */ 770 volatile u32 EU30; /* SDMA + 0xe0 */ 771 volatile u32 EU31; /* SDMA + 0xe4 */ 772 volatile u32 EU32; /* SDMA + 0xe8 */ 773 volatile u32 EU33; /* SDMA + 0xec */ 774 volatile u32 EU34; /* SDMA + 0xf0 */ 775 volatile u32 EU35; /* SDMA + 0xf4 */ 776 volatile u32 EU36; /* SDMA + 0xf8 */ 777 volatile u32 EU37; /* SDMA + 0xfc */ 778}; 779 780struct mpc5xxx_i2c { 781 volatile u32 madr; /* I2Cn + 0x00 */ 782 volatile u32 mfdr; /* I2Cn + 0x04 */ 783 volatile u32 mcr; /* I2Cn + 0x08 */ 784 volatile u32 msr; /* I2Cn + 0x0C */ 785 volatile u32 mdr; /* I2Cn + 0x10 */ 786}; 787 788struct mpc5xxx_spi { 789 volatile u8 cr1; /* SPI + 0x0F00 */ 790 volatile u8 cr2; /* SPI + 0x0F01 */ 791 volatile u8 reserved1[2]; 792 volatile u8 brr; /* SPI + 0x0F04 */ 793 volatile u8 sr; /* SPI + 0x0F05 */ 794 volatile u8 reserved2[3]; 795 volatile u8 dr; /* SPI + 0x0F09 */ 796 volatile u8 reserved3[3]; 797 volatile u8 pdr; /* SPI + 0x0F0D */ 798 volatile u8 reserved4[2]; 799 volatile u8 ddr; /* SPI + 0x0F10 */ 800}; 801 802 803struct mpc5xxx_gpt { 804 volatile u32 emsr; /* GPT + Timer# * 0x10 + 0x00 */ 805 volatile u32 cir; /* GPT + Timer# * 0x10 + 0x04 */ 806 volatile u32 pwmcr; /* GPT + Timer# * 0x10 + 0x08 */ 807 volatile u32 sr; /* GPT + Timer# * 0x10 + 0x0c */ 808}; 809 810struct mpc5xxx_gpt_0_7 { 811 struct mpc5xxx_gpt gpt0; 812 struct mpc5xxx_gpt gpt1; 813 struct mpc5xxx_gpt gpt2; 814 struct mpc5xxx_gpt gpt3; 815 struct mpc5xxx_gpt gpt4; 816 struct mpc5xxx_gpt gpt5; 817 struct mpc5xxx_gpt gpt6; 818 struct mpc5xxx_gpt gpt7; 819}; 820 821struct mscan_buffer { 822 volatile u8 idr[0x8]; /* 0x00 */ 823 volatile u8 dsr[0x10]; /* 0x08 */ 824 volatile u8 dlr; /* 0x18 */ 825 volatile u8 tbpr; /* 0x19 */ /* This register is not applicable for receive buffers */ 826 volatile u16 rsrv1; /* 0x1A */ 827 volatile u8 tsrh; /* 0x1C */ 828 volatile u8 tsrl; /* 0x1D */ 829 volatile u16 rsrv2; /* 0x1E */ 830}; 831 832struct mpc5xxx_mscan { 833 volatile u8 canctl0; /* MSCAN + 0x00 */ 834 volatile u8 canctl1; /* MSCAN + 0x01 */ 835 volatile u16 rsrv1; /* MSCAN + 0x02 */ 836 volatile u8 canbtr0; /* MSCAN + 0x04 */ 837 volatile u8 canbtr1; /* MSCAN + 0x05 */ 838 volatile u16 rsrv2; /* MSCAN + 0x06 */ 839 volatile u8 canrflg; /* MSCAN + 0x08 */ 840 volatile u8 canrier; /* MSCAN + 0x09 */ 841 volatile u16 rsrv3; /* MSCAN + 0x0A */ 842 volatile u8 cantflg; /* MSCAN + 0x0C */ 843 volatile u8 cantier; /* MSCAN + 0x0D */ 844 volatile u16 rsrv4; /* MSCAN + 0x0E */ 845 volatile u8 cantarq; /* MSCAN + 0x10 */ 846 volatile u8 cantaak; /* MSCAN + 0x11 */ 847 volatile u16 rsrv5; /* MSCAN + 0x12 */ 848 volatile u8 cantbsel; /* MSCAN + 0x14 */ 849 volatile u8 canidac; /* MSCAN + 0x15 */ 850 volatile u16 rsrv6[3]; /* MSCAN + 0x16 */ 851 volatile u8 canrxerr; /* MSCAN + 0x1C */ 852 volatile u8 cantxerr; /* MSCAN + 0x1D */ 853 volatile u16 rsrv7; /* MSCAN + 0x1E */ 854 volatile u8 canidar0; /* MSCAN + 0x20 */ 855 volatile u8 canidar1; /* MSCAN + 0x21 */ 856 volatile u16 rsrv8; /* MSCAN + 0x22 */ 857 volatile u8 canidar2; /* MSCAN + 0x24 */ 858 volatile u8 canidar3; /* MSCAN + 0x25 */ 859 volatile u16 rsrv9; /* MSCAN + 0x26 */ 860 volatile u8 canidmr0; /* MSCAN + 0x28 */ 861 volatile u8 canidmr1; /* MSCAN + 0x29 */ 862 volatile u16 rsrv10; /* MSCAN + 0x2A */ 863 volatile u8 canidmr2; /* MSCAN + 0x2C */ 864 volatile u8 canidmr3; /* MSCAN + 0x2D */ 865 volatile u16 rsrv11; /* MSCAN + 0x2E */ 866 volatile u8 canidar4; /* MSCAN + 0x30 */ 867 volatile u8 canidar5; /* MSCAN + 0x31 */ 868 volatile u16 rsrv12; /* MSCAN + 0x32 */ 869 volatile u8 canidar6; /* MSCAN + 0x34 */ 870 volatile u8 canidar7; /* MSCAN + 0x35 */ 871 volatile u16 rsrv13; /* MSCAN + 0x36 */ 872 volatile u8 canidmr4; /* MSCAN + 0x38 */ 873 volatile u8 canidmr5; /* MSCAN + 0x39 */ 874 volatile u16 rsrv14; /* MSCAN + 0x3A */ 875 volatile u8 canidmr6; /* MSCAN + 0x3C */ 876 volatile u8 canidmr7; /* MSCAN + 0x3D */ 877 volatile u16 rsrv15; /* MSCAN + 0x3E */ 878 879 struct mscan_buffer canrxfg; /* MSCAN + 0x40 */ /* Foreground receive buffer */ 880 struct mscan_buffer cantxfg; /* MSCAN + 0x60 */ /* Foreground transmit buffer */ 881 }; 882 883struct mpc5xxx_xlb { 884 volatile u8 reserved[0x40]; /* XLB + 0x00 */ 885 volatile u32 config; /* XLB + 0x40 */ 886 volatile u32 version; /* XLB + 0x44 */ 887 volatile u32 status; /* XLB + 0x48 */ 888 volatile u32 int_enable; /* XLB + 0x4c */ 889 volatile u32 addr_capture; /* XLB + 0x50 */ 890 volatile u32 bus_sig_capture; /* XLB + 0x54 */ 891 volatile u32 addr_timeout; /* XLB + 0x58 */ 892 volatile u32 data_timeout; /* XLB + 0x5c */ 893 volatile u32 bus_act_timeout; /* XLB + 0x60 */ 894 volatile u32 master_pri_enable; /* XLB + 0x64 */ 895 volatile u32 master_priority; /* XLB + 0x68 */ 896 volatile u32 base_address; /* XLB + 0x6c */ 897 volatile u32 snoop_window; /* XLB + 0x70 */ 898}; 899 900/* function prototypes */ 901void loadtask(int basetask, int tasks); 902 903#endif /* __ASSEMBLY__ */ 904 905#endif /* __ASMPPC_MPC5XXX_H */ 906