LXR uboot/arch/arm/cpu/arm920t/imx/timer.c

   1/*
   2 * (C) Copyright 2002
   3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   4 * Marius Groeger <mgroeger@sysgo.de>
   5 *
   6 * (C) Copyright 2002
   7 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   8 * Alex Zuepke <azu@sysgo.de>
   9 *
  10 * (C) Copyright 2002
  11 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
  12 *
  13 * See file CREDITS for list of people who contributed to this
  14 * project.
  15 *
  16 * This program is free software; you can redistribute it and/or
  17 * modify it under the terms of the GNU General Public License as
  18 * published by the Free Software Foundation; either version 2 of
  19 * the License, or (at your option) any later version.
  20 *
  21 * This program is distributed in the hope that it will be useful,
  22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24 * GNU General Public License for more details.
  25 *
  26 * You should have received a copy of the GNU General Public License
  27 * along with this program; if not, write to the Free Software
  28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29 * MA 02111-1307 USA
  30 */
  31
  32#include <common.h>
  33#if defined (CONFIG_IMX)
  34
  35#include <asm/arch/imx-regs.h>
  36
  37int timer_init (void)
  38{
  39        int i;
  40        /* setup GP Timer 1 */
  41        TCTL1 = TCTL_SWR;
  42        for ( i=0; i<100; i++) TCTL1 = 0; /* We have no udelay by now */
  43        TPRER1 = get_PERCLK1() / 1000000; /* 1 MHz */
  44        TCTL1 |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */
  45
  46        reset_timer_masked();
  47
  48        return (0);
  49}
  50
  51/*
  52 * timer without interrupts
  53 */
  54
  55void reset_timer (void)
  56{
  57        reset_timer_masked ();
  58}
  59
  60ulong get_timer (ulong base)
  61{
  62        return get_timer_masked() - base;
  63}
  64
  65void set_timer (ulong t)
  66{
  67        /* nop */
  68}
  69
  70void reset_timer_masked (void)
  71{
  72        TCTL1 &= ~TCTL_TEN;
  73        TCTL1 |= TCTL_TEN; /* Enable timer */
  74}
  75
  76ulong get_timer_masked (void)
  77{
  78        return TCN1;
  79}
  80
  81void udelay_masked (unsigned long usec)
  82{
  83        ulong endtime = get_timer_masked() + usec;
  84        signed long diff;
  85
  86        do {
  87                ulong now = get_timer_masked ();
  88                diff = endtime - now;
  89        } while (diff >= 0);
  90}
  91
  92void __udelay (unsigned long usec)
  93{
  94        udelay_masked(usec);
  95}
  96
  97/*
  98 * This function is derived from PowerPC code (read timebase as long long).
  99 * On ARM it just returns the timer value.
 100 */
 101unsigned long long get_ticks(void)
 102{
 103        return get_timer(0);
 104}
 105
 106/*
 107 * This function is derived from PowerPC code (timebase clock frequency).
 108 * On ARM it returns the number of timer ticks per second.
 109 */
 110ulong get_tbclk (void)
 111{
 112        ulong tbclk;
 113
 114        tbclk = CONFIG_SYS_HZ;
 115
 116        return tbclk;
 117}
 118
 119/*
 120 * Reset the cpu by setting up the watchdog timer and let him time out
 121 */
 122void reset_cpu (ulong ignored)
 123{
 124        /* Disable watchdog and set Time-Out field to 0 */
 125        WCR = 0x00000000;
 126
 127        /* Write Service Sequence */
 128        WSR = 0x00005555;
 129        WSR = 0x0000AAAA;
 130
 131        /* Enable watchdog */
 132        WCR = 0x00000001;
 133
 134        while (1);
 135        /*NOTREACHED*/
 136}
 137
 138#endif /* defined (CONFIG_IMX) */
 139