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33#ifndef __ASM_ARCH_HARDWARE_H
34#define __ASM_ARCH_HARDWARE_H
35
36#include <config.h>
37#include <asm/sizes.h>
38
39#define REG(addr) (*(volatile unsigned int *)(addr))
40#define REG_P(addr) ((volatile unsigned int *)(addr))
41
42typedef volatile unsigned int dv_reg;
43typedef volatile unsigned int * dv_reg_p;
44
45
46
47
48
49
50
51
52#ifndef CONFIG_SOC_DA8XX
53
54#define DAVINCI_DMA_3PCC_BASE (0x01c00000)
55#define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
56#define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
57#define DAVINCI_UART0_BASE (0x01c20000)
58#define DAVINCI_UART1_BASE (0x01c20400)
59#define DAVINCI_I2C_BASE (0x01c21000)
60#define DAVINCI_TIMER0_BASE (0x01c21400)
61#define DAVINCI_TIMER1_BASE (0x01c21800)
62#define DAVINCI_WDOG_BASE (0x01c21c00)
63#define DAVINCI_PWM0_BASE (0x01c22000)
64#define DAVINCI_PWM1_BASE (0x01c22400)
65#define DAVINCI_PWM2_BASE (0x01c22800)
66#define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000)
67#define DAVINCI_PLL_CNTRL0_BASE (0x01c40800)
68#define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00)
69#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000)
70#define DAVINCI_ARM_INTC_BASE (0x01c48000)
71#define DAVINCI_USB_OTG_BASE (0x01c64000)
72#define DAVINCI_CFC_ATA_BASE (0x01c66000)
73#define DAVINCI_SPI_BASE (0x01c66800)
74#define DAVINCI_GPIO_BASE (0x01c67000)
75#define DAVINCI_VPSS_REGS_BASE (0x01c70000)
76#if !defined(CONFIG_SOC_DM646X)
77#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
78#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
79#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
80#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
81#endif
82#define DAVINCI_DDR_BASE (0x80000000)
83
84#ifdef CONFIG_SOC_DM644X
85#define DAVINCI_UART2_BASE 0x01c20800
86#define DAVINCI_UHPI_BASE 0x01c67800
87#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01c80000
88#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01c81000
89#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01c82000
90#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01c84000
91#define DAVINCI_IMCOP_BASE 0x01cc0000
92#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e00000
93#define DAVINCI_VLYNQ_BASE 0x01e01000
94#define DAVINCI_ASP_BASE 0x01e02000
95#define DAVINCI_MMC_SD_BASE 0x01e10000
96#define DAVINCI_MS_BASE 0x01e20000
97#define DAVINCI_VLYNQ_REMOTE_BASE 0x0c000000
98
99#elif defined(CONFIG_SOC_DM355)
100#define DAVINCI_MMC_SD1_BASE 0x01e00000
101#define DAVINCI_ASP0_BASE 0x01e02000
102#define DAVINCI_ASP1_BASE 0x01e04000
103#define DAVINCI_UART2_BASE 0x01e06000
104#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e10000
105#define DAVINCI_MMC_SD0_BASE 0x01e11000
106
107#elif defined(CONFIG_SOC_DM365)
108#define DAVINCI_MMC_SD1_BASE 0x01d00000
109#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000
110#define DAVINCI_MMC_SD0_BASE 0x01d11000
111
112#elif defined(CONFIG_SOC_DM646X)
113#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x20008000
114#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
115#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x44000000
116#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x46000000
117#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x48000000
118
119#endif
120
121#else
122
123#define DAVINCI_UART0_BASE 0x01c42000
124#define DAVINCI_UART1_BASE 0x01d0c000
125#define DAVINCI_UART2_BASE 0x01d0d000
126#define DAVINCI_I2C0_BASE 0x01c22000
127#define DAVINCI_I2C1_BASE 0x01e28000
128#define DAVINCI_TIMER0_BASE 0x01c20000
129#define DAVINCI_TIMER1_BASE 0x01c21000
130#define DAVINCI_WDOG_BASE 0x01c21000
131#define DAVINCI_PLL_CNTRL0_BASE 0x01c11000
132#define DAVINCI_PSC0_BASE 0x01c10000
133#define DAVINCI_PSC1_BASE 0x01e27000
134#define DAVINCI_SPI0_BASE 0x01c41000
135#define DAVINCI_USB_OTG_BASE 0x01e00000
136#define DAVINCI_SPI1_BASE 0x01e12000
137#define DAVINCI_GPIO_BASE 0x01e26000
138#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01e23000
139#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000
140#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01e20000
141#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01e24000
142#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x68000000
143#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x40000000
144#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x60000000
145#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x62000000
146#define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE 0x64000000
147#define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE 0x66000000
148#define DAVINCI_DDR_EMIF_CTRL_BASE 0xb0000000
149#define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000
150#define DAVINCI_INTC_BASE 0xfffee000
151#define DAVINCI_BOOTCFG_BASE 0x01c14000
152
153#endif
154
155
156#define DAVINCI_GPSC_ARMDOMAIN 0
157#define DAVINCI_GPSC_DSPDOMAIN 1
158
159#ifndef CONFIG_SOC_DA8XX
160
161#define DAVINCI_LPSC_VPSSMSTR 0
162#define DAVINCI_LPSC_VPSSSLV 1
163#define DAVINCI_LPSC_TPCC 2
164#define DAVINCI_LPSC_TPTC0 3
165#define DAVINCI_LPSC_TPTC1 4
166#define DAVINCI_LPSC_EMAC 5
167#define DAVINCI_LPSC_EMAC_WRAPPER 6
168#define DAVINCI_LPSC_MDIO 7
169#define DAVINCI_LPSC_IEEE1394 8
170#define DAVINCI_LPSC_USB 9
171#define DAVINCI_LPSC_ATA 10
172#define DAVINCI_LPSC_VLYNQ 11
173#define DAVINCI_LPSC_UHPI 12
174#define DAVINCI_LPSC_DDR_EMIF 13
175#define DAVINCI_LPSC_AEMIF 14
176#define DAVINCI_LPSC_MMC_SD 15
177#define DAVINCI_LPSC_MEMSTICK 16
178#define DAVINCI_LPSC_McBSP 17
179#define DAVINCI_LPSC_I2C 18
180#define DAVINCI_LPSC_UART0 19
181#define DAVINCI_LPSC_UART1 20
182#define DAVINCI_LPSC_UART2 21
183#define DAVINCI_LPSC_SPI 22
184#define DAVINCI_LPSC_PWM0 23
185#define DAVINCI_LPSC_PWM1 24
186#define DAVINCI_LPSC_PWM2 25
187#define DAVINCI_LPSC_GPIO 26
188#define DAVINCI_LPSC_TIMER0 27
189#define DAVINCI_LPSC_TIMER1 28
190#define DAVINCI_LPSC_TIMER2 29
191#define DAVINCI_LPSC_SYSTEM_SUBSYS 30
192#define DAVINCI_LPSC_ARM 31
193#define DAVINCI_LPSC_SCR2 32
194#define DAVINCI_LPSC_SCR3 33
195#define DAVINCI_LPSC_SCR4 34
196#define DAVINCI_LPSC_CROSSBAR 35
197#define DAVINCI_LPSC_CFG27 36
198#define DAVINCI_LPSC_CFG3 37
199#define DAVINCI_LPSC_CFG5 38
200#define DAVINCI_LPSC_GEM 39
201#define DAVINCI_LPSC_IMCOP 40
202
203#define DAVINCI_DM646X_LPSC_EMAC 14
204#define DAVINCI_DM646X_LPSC_UART0 26
205#define DAVINCI_DM646X_LPSC_I2C 31
206
207#else
208
209enum davinci_lpsc_ids {
210 DAVINCI_LPSC_TPCC = 0,
211 DAVINCI_LPSC_TPTC0,
212 DAVINCI_LPSC_TPTC1,
213 DAVINCI_LPSC_AEMIF,
214 DAVINCI_LPSC_SPI0,
215 DAVINCI_LPSC_MMC_SD,
216 DAVINCI_LPSC_AINTC,
217 DAVINCI_LPSC_ARM_RAM_ROM,
218 DAVINCI_LPSC_SECCTL_KEYMGR,
219 DAVINCI_LPSC_UART0,
220 DAVINCI_LPSC_SCR0,
221 DAVINCI_LPSC_SCR1,
222 DAVINCI_LPSC_SCR2,
223 DAVINCI_LPSC_DMAX,
224 DAVINCI_LPSC_ARM,
225 DAVINCI_LPSC_GEM,
226
227 DAVINCI_LPSC_PSC1_BASE = 32,
228 DAVINCI_LPSC_USB11,
229 DAVINCI_LPSC_USB20,
230 DAVINCI_LPSC_GPIO,
231 DAVINCI_LPSC_UHPI,
232 DAVINCI_LPSC_EMAC,
233 DAVINCI_LPSC_DDR_EMIF,
234 DAVINCI_LPSC_McASP0,
235 DAVINCI_LPSC_McASP1,
236 DAVINCI_LPSC_McASP2,
237 DAVINCI_LPSC_SPI1,
238 DAVINCI_LPSC_I2C1,
239 DAVINCI_LPSC_UART1,
240 DAVINCI_LPSC_UART2,
241 DAVINCI_LPSC_LCDC,
242 DAVINCI_LPSC_ePWM,
243 DAVINCI_LPSC_eCAP,
244 DAVINCI_LPSC_eQEP,
245 DAVINCI_LPSC_SCR_P0,
246 DAVINCI_LPSC_SCR_P1,
247 DAVINCI_LPSC_CR_P3,
248 DAVINCI_LPSC_L3_CBA_RAM
249};
250
251#endif
252
253void lpsc_on(unsigned int id);
254void dsp_on(void);
255
256void davinci_enable_uart0(void);
257void davinci_enable_emac(void);
258void davinci_enable_i2c(void);
259void davinci_errata_workarounds(void);
260
261#ifndef CONFIG_SOC_DA8XX
262
263
264#define PSC_CHP_SHRTSW (0x01c40038)
265#define PSC_GBLCTL (0x01c41010)
266#define PSC_EPCPR (0x01c41070)
267#define PSC_EPCCR (0x01c41078)
268#define PSC_PTCMD (0x01c41120)
269#define PSC_PTSTAT (0x01c41128)
270#define PSC_PDSTAT (0x01c41200)
271#define PSC_PDSTAT1 (0x01c41204)
272#define PSC_PDCTL (0x01c41300)
273#define PSC_PDCTL1 (0x01c41304)
274
275#define PSC_MDCTL_BASE (0x01c41a00)
276#define PSC_MDSTAT_BASE (0x01c41800)
277
278#define VDD3P3V_PWDN (0x01c40048)
279#define UART0_PWREMU_MGMT (0x01c20030)
280
281#define PSC_SILVER_BULLET (0x01c41a20)
282
283#else
284
285#define PSC_PSC0_MODULE_ID_CNT 16
286#define PSC_PSC1_MODULE_ID_CNT 32
287
288struct davinci_psc_regs {
289 dv_reg revid;
290 dv_reg rsvd0[71];
291 dv_reg ptcmd;
292 dv_reg rsvd1;
293 dv_reg ptstat;
294 dv_reg rsvd2[437];
295 union {
296 struct {
297 dv_reg mdstat[PSC_PSC0_MODULE_ID_CNT];
298 dv_reg rsvd3[112];
299 dv_reg mdctl[PSC_PSC0_MODULE_ID_CNT];
300 } psc0;
301 struct {
302 dv_reg mdstat[PSC_PSC1_MODULE_ID_CNT];
303 dv_reg rsvd3[96];
304 dv_reg mdctl[PSC_PSC1_MODULE_ID_CNT];
305 } psc1;
306 };
307};
308
309#define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE)
310#define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE)
311
312#endif
313
314#ifndef CONFIG_SOC_DA8XX
315
316
317#define VBPR (0x20000020)
318
319
320
321
322#define PINMUX0 0x01c40000
323#define PINMUX1 0x01c40004
324#define PINMUX2 0x01c40008
325#define PINMUX3 0x01c4000c
326#define PINMUX4 0x01c40010
327
328#else
329
330struct davinci_pllc_regs {
331 dv_reg revid;
332 dv_reg rsvd1[56];
333 dv_reg rstype;
334 dv_reg rsvd2[6];
335 dv_reg pllctl;
336 dv_reg ocsel;
337 dv_reg rsvd3[2];
338 dv_reg pllm;
339 dv_reg prediv;
340 dv_reg plldiv1;
341 dv_reg plldiv2;
342 dv_reg plldiv3;
343 dv_reg oscdiv;
344 dv_reg postdiv;
345 dv_reg rsvd4[3];
346 dv_reg pllcmd;
347 dv_reg pllstat;
348 dv_reg alnctl;
349 dv_reg dchange;
350 dv_reg cken;
351 dv_reg ckstat;
352 dv_reg systat;
353 dv_reg rsvd5[3];
354 dv_reg plldiv4;
355 dv_reg plldiv5;
356 dv_reg plldiv6;
357 dv_reg plldiv7;
358 dv_reg rsvd6[32];
359 dv_reg emucnt0;
360 dv_reg emucnt1;
361};
362
363#define davinci_pllc_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
364#define DAVINCI_PLLC_DIV_MASK 0x1f
365
366
367enum davinci_clk_ids {
368 DAVINCI_SPI0_CLKID = 2,
369 DAVINCI_UART2_CLKID = 2,
370 DAVINCI_MDIO_CLKID = 4,
371 DAVINCI_ARM_CLKID = 6,
372 DAVINCI_PLLM_CLKID = 0xff,
373 DAVINCI_PLLC_CLKID = 0x100,
374 DAVINCI_AUXCLK_CLKID = 0x101
375};
376
377int clk_get(enum davinci_clk_ids id);
378
379
380struct davinci_syscfg_regs {
381 dv_reg revid;
382 dv_reg rsvd[71];
383 dv_reg pinmux[20];
384 dv_reg suspsrc;
385 dv_reg chipsig;
386 dv_reg chipsig_clr;
387 dv_reg cfgchip0;
388 dv_reg cfgchip1;
389 dv_reg cfgchip2;
390 dv_reg cfgchip3;
391 dv_reg cfgchip4;
392};
393
394#define davinci_syscfg_regs \
395 ((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE)
396
397
398#define DAVINCI_SYSCFG_SUSPSRC_EMAC (1 << 5)
399#define DAVINCI_SYSCFG_SUSPSRC_I2C (1 << 16)
400#define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21)
401#define DAVINCI_SYSCFG_SUSPSRC_SPI1 (1 << 22)
402#define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20)
403#define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27)
404
405
406struct davinci_aintc_regs {
407 dv_reg revid;
408 dv_reg cr;
409 dv_reg dummy0[2];
410 dv_reg ger;
411 dv_reg dummy1[219];
412 dv_reg ecr1;
413 dv_reg ecr2;
414 dv_reg ecr3;
415 dv_reg dummy2[1117];
416 dv_reg hier;
417};
418
419#define davinci_aintc_regs ((struct davinci_aintc_regs *)DAVINCI_INTC_BASE)
420
421struct davinci_uart_ctrl_regs {
422 dv_reg revid1;
423 dv_reg revid2;
424 dv_reg pwremu_mgmt;
425 dv_reg mdr;
426};
427
428#define DAVINCI_UART_CTRL_BASE 0x28
429#define DAVINCI_UART0_CTRL_ADDR (DAVINCI_UART0_BASE + DAVINCI_UART_CTRL_BASE)
430#define DAVINCI_UART1_CTRL_ADDR (DAVINCI_UART1_BASE + DAVINCI_UART_CTRL_BASE)
431#define DAVINCI_UART2_CTRL_ADDR (DAVINCI_UART2_BASE + DAVINCI_UART_CTRL_BASE)
432
433#define davinci_uart0_ctrl_regs \
434 ((struct davinci_uart_ctrl_regs *)DAVINCI_UART0_CTRL_ADDR)
435#define davinci_uart1_ctrl_regs \
436 ((struct davinci_uart_ctrl_regs *)DAVINCI_UART1_CTRL_ADDR)
437#define davinci_uart2_ctrl_regs \
438 ((struct davinci_uart_ctrl_regs *)DAVINCI_UART2_CTRL_ADDR)
439
440
441#define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0)
442#define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13)
443#define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14)
444
445#endif
446
447#endif
448
