LXR uboot/arch/arm/include/asm/arch-omap4/mmc_host

   1/*
   2 * (C) Copyright 2010
   3 * Texas Instruments, <www.ti.com>
   4 * Syed Mohammed Khasim <khasim@ti.com>
   5 *
   6 * See file CREDITS for list of people who contributed to this
   7 * project.
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License as
  11 * published by the Free Software Foundation's version 2 of
  12 * the License.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 * MA 02111-1307 USA
  23 */
  24
  25#ifndef MMC_HOST_DEF_H
  26#define MMC_HOST_DEF_H
  27
  28/*
  29 * OMAP HSMMC register definitions
  30 */
  31
  32#define OMAP_HSMMC1_BASE        0x4809C100
  33#define OMAP_HSMMC2_BASE        0x480B4100
  34#define OMAP_HSMMC3_BASE        0x480AD100
  35
  36typedef struct hsmmc {
  37        unsigned char res1[0x10];
  38        unsigned int sysconfig;         /* 0x10 */
  39        unsigned int sysstatus;         /* 0x14 */
  40        unsigned char res2[0x14];
  41        unsigned int con;               /* 0x2C */
  42        unsigned char res3[0xD4];
  43        unsigned int blk;               /* 0x104 */
  44        unsigned int arg;               /* 0x108 */
  45        unsigned int cmd;               /* 0x10C */
  46        unsigned int rsp10;             /* 0x110 */
  47        unsigned int rsp32;             /* 0x114 */
  48        unsigned int rsp54;             /* 0x118 */
  49        unsigned int rsp76;             /* 0x11C */
  50        unsigned int data;              /* 0x120 */
  51        unsigned int pstate;            /* 0x124 */
  52        unsigned int hctl;              /* 0x128 */
  53        unsigned int sysctl;            /* 0x12C */
  54        unsigned int stat;              /* 0x130 */
  55        unsigned int ie;                /* 0x134 */
  56        unsigned char res4[0x8];
  57        unsigned int capa;              /* 0x140 */
  58} hsmmc_t;
  59
  60/*
  61 * OMAP HS MMC Bit definitions
  62 */
  63#define MMC_SOFTRESET                   (0x1 << 1)
  64#define RESETDONE                       (0x1 << 0)
  65#define NOOPENDRAIN                     (0x0 << 0)
  66#define OPENDRAIN                       (0x1 << 0)
  67#define OD                              (0x1 << 0)
  68#define INIT_NOINIT                     (0x0 << 1)
  69#define INIT_INITSTREAM                 (0x1 << 1)
  70#define HR_NOHOSTRESP                   (0x0 << 2)
  71#define STR_BLOCK                       (0x0 << 3)
  72#define MODE_FUNC                       (0x0 << 4)
  73#define DW8_1_4BITMODE                  (0x0 << 5)
  74#define MIT_CTO                         (0x0 << 6)
  75#define CDP_ACTIVEHIGH                  (0x0 << 7)
  76#define WPP_ACTIVEHIGH                  (0x0 << 8)
  77#define RESERVED_MASK                   (0x3 << 9)
  78#define CTPL_MMC_SD                     (0x0 << 11)
  79#define BLEN_512BYTESLEN                (0x200 << 0)
  80#define NBLK_STPCNT                     (0x0 << 16)
  81#define DE_DISABLE                      (0x0 << 0)
  82#define BCE_DISABLE                     (0x0 << 1)
  83#define BCE_ENABLE                      (0x1 << 1)
  84#define ACEN_DISABLE                    (0x0 << 2)
  85#define DDIR_OFFSET                     (4)
  86#define DDIR_MASK                       (0x1 << 4)
  87#define DDIR_WRITE                      (0x0 << 4)
  88#define DDIR_READ                       (0x1 << 4)
  89#define MSBS_SGLEBLK                    (0x0 << 5)
  90#define MSBS_MULTIBLK                   (0x1 << 5)
  91#define RSP_TYPE_OFFSET                 (16)
  92#define RSP_TYPE_MASK                   (0x3 << 16)
  93#define RSP_TYPE_NORSP                  (0x0 << 16)
  94#define RSP_TYPE_LGHT136                (0x1 << 16)
  95#define RSP_TYPE_LGHT48                 (0x2 << 16)
  96#define RSP_TYPE_LGHT48B                (0x3 << 16)
  97#define CCCE_NOCHECK                    (0x0 << 19)
  98#define CCCE_CHECK                      (0x1 << 19)
  99#define CICE_NOCHECK                    (0x0 << 20)
 100#define CICE_CHECK                      (0x1 << 20)
 101#define DP_OFFSET                       (21)
 102#define DP_MASK                         (0x1 << 21)
 103#define DP_NO_DATA                      (0x0 << 21)
 104#define DP_DATA                         (0x1 << 21)
 105#define CMD_TYPE_NORMAL                 (0x0 << 22)
 106#define INDEX_OFFSET                    (24)
 107#define INDEX_MASK                      (0x3f << 24)
 108#define INDEX(i)                        (i << 24)
 109#define DATI_MASK                       (0x1 << 1)
 110#define DATI_CMDDIS                     (0x1 << 1)
 111#define DTW_1_BITMODE                   (0x0 << 1)
 112#define DTW_4_BITMODE                   (0x1 << 1)
 113#define DTW_8_BITMODE                   (0x1 << 5) /* CON[DW8]*/
 114#define SDBP_PWROFF                     (0x0 << 8)
 115#define SDBP_PWRON                      (0x1 << 8)
 116#define SDVS_1V8                        (0x5 << 9)
 117#define SDVS_3V0                        (0x6 << 9)
 118#define ICE_MASK                        (0x1 << 0)
 119#define ICE_STOP                        (0x0 << 0)
 120#define ICS_MASK                        (0x1 << 1)
 121#define ICS_NOTREADY                    (0x0 << 1)
 122#define ICE_OSCILLATE                   (0x1 << 0)
 123#define CEN_MASK                        (0x1 << 2)
 124#define CEN_DISABLE                     (0x0 << 2)
 125#define CEN_ENABLE                      (0x1 << 2)
 126#define CLKD_OFFSET                     (6)
 127#define CLKD_MASK                       (0x3FF << 6)
 128#define DTO_MASK                        (0xF << 16)
 129#define DTO_15THDTO                     (0xE << 16)
 130#define SOFTRESETALL                    (0x1 << 24)
 131#define CC_MASK                         (0x1 << 0)
 132#define TC_MASK                         (0x1 << 1)
 133#define BWR_MASK                        (0x1 << 4)
 134#define BRR_MASK                        (0x1 << 5)
 135#define ERRI_MASK                       (0x1 << 15)
 136#define IE_CC                           (0x01 << 0)
 137#define IE_TC                           (0x01 << 1)
 138#define IE_BWR                          (0x01 << 4)
 139#define IE_BRR                          (0x01 << 5)
 140#define IE_CTO                          (0x01 << 16)
 141#define IE_CCRC                         (0x01 << 17)
 142#define IE_CEB                          (0x01 << 18)
 143#define IE_CIE                          (0x01 << 19)
 144#define IE_DTO                          (0x01 << 20)
 145#define IE_DCRC                         (0x01 << 21)
 146#define IE_DEB                          (0x01 << 22)
 147#define IE_CERR                         (0x01 << 28)
 148#define IE_BADA                         (0x01 << 29)
 149
 150#define VS30_3V0SUP                     (1 << 25)
 151#define VS18_1V8SUP                     (1 << 26)
 152
 153/* Driver definitions */
 154#define MMCSD_SECTOR_SIZE               512
 155#define MMC_CARD                        0
 156#define SD_CARD                         1
 157#define BYTE_MODE                       0
 158#define SECTOR_MODE                     1
 159#define CLK_INITSEQ                     0
 160#define CLK_400KHZ                      1
 161#define CLK_MISC                        2
 162
 163typedef struct {
 164        unsigned int card_type;
 165        unsigned int version;
 166        unsigned int mode;
 167        unsigned int size;
 168        unsigned int RCA;
 169} mmc_card_data;
 170#define RSP_TYPE_NONE   (RSP_TYPE_NORSP   | CCCE_NOCHECK | CICE_NOCHECK)
 171#define MMC_CMD0        (INDEX(0)  | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
 172
 173/* Clock Configurations and Macros */
 174#define MMC_CLOCK_REFERENCE     96 /* MHz */
 175
 176#define mmc_reg_out(addr, mask, val)\
 177        writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
 178
 179int omap_mmc_init(int dev_index);
 180
 181#endif /* MMC_HOST_DEF_H */
 182