1/* DO NOT EDIT THIS FILE 2 * Automatically generated by generate-def-headers.xsl 3 * DO NOT EDIT THIS FILE 4 */ 5 6#ifndef __BFIN_DEF_ADSP_BF512_proc__ 7#define __BFIN_DEF_ADSP_BF512_proc__ 8 9#include "../mach-common/ADSP-EDN-core_def.h" 10 11#define PLL_CTL 0xFFC00000 /* PLL Control Register */ 12#define PLL_DIV 0xFFC00004 /* PLL Divide Register */ 13#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */ 14#define PLL_STAT 0xFFC0000C /* PLL Status Register */ 15#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */ 16#define CHIPID 0xFFC00014 17#define SWRST 0xFFC00100 /* Software Reset Register */ 18#define SYSCR 0xFFC00104 /* System Configuration register */ 19#define SIC_IMASK0 0xFFC0010C /* Interrupt Mask Register */ 20#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ 21#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ 22#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ 23#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */ 24#define SIC_ISR0 0xFFC00120 /* Interrupt Status Register */ 25#define SIC_IWR0 0xFFC00124 /* Interrupt Wakeup Register */ 26#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */ 27#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */ 28#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */ 29#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */ 30#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */ 31#define SIC_ISR1 0xFFC00160 /* Interrupt Status register */ 32#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */ 33#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ 34#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ 35#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ 36#define RTC_STAT 0xFFC00300 /* RTC Status Register */ 37#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ 38#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ 39#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ 40#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ 41#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register */ 42#define UART0_THR 0xFFC00400 /* Transmit Holding register */ 43#define UART0_RBR 0xFFC00400 /* Receive Buffer register */ 44#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ 45#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */ 46#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ 47#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */ 48#define UART0_LCR 0xFFC0040C /* Line Control Register */ 49#define UART0_MCR 0xFFC00410 /* Modem Control Register */ 50#define UART0_LSR 0xFFC00414 /* Line Status Register */ 51#define UART0_MSR 0xFFC00418 /* Modem Status Register */ 52#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */ 53#define UART0_GCTL 0xFFC00424 /* Global Control Register */ 54#define SPI0_CTL 0xFFC00500 /* SPI0 Control Register */ 55#define SPI0_FLG 0xFFC00504 /* SPI0 Flag register */ 56#define SPI0_STAT 0xFFC00508 /* SPI0 Status register */ 57#define SPI0_TDBR 0xFFC0050C /* SPI0 Transmit Data Buffer Register */ 58#define SPI0_RDBR 0xFFC00510 /* SPI0 Receive Data Buffer Register */ 59#define SPI0_BAUD 0xFFC00514 /* SPI0 Baud rate Register */ 60#define SPI0_SHADOW 0xFFC00518 /* SPI0_RDBR Shadow Register */ 61#define SPI1_CTL 0xFFC03400 /* SPI1 Control */ 62#define SPI1_FLG 0xFFC03404 /* SPI1 Flag Register */ 63#define SPI1_STAT 0xFFC03408 /* SPI1 Status Register */ 64#define SPI1_TDBR 0xFFC0340C /* SPI1 Transmit Data Buffer */ 65#define SPI1_RDBR 0xFFC03410 /* SPI1 Receive Data Buffer */ 66#define SPI1_BAUD 0xFFC03414 /* SPI1 Baud Rate */ 67#define SPI1_SHADOW 0xFFC03418 /* SPI1_RDBR Shadow Register */ 68#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ 69#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ 70#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ 71#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ 72#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ 73#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ 74#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ 75#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ 76#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ 77#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ 78#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ 79#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ 80#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */ 81#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */ 82#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */ 83#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */ 84#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */ 85#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */ 86#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */ 87#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */ 88#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */ 89#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */ 90#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */ 91#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */ 92#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */ 93#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */ 94#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */ 95#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register\n */ 96#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */ 97#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */ 98#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */ 99#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */ 100#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */ 101#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */ 102#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */ 103#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */ 104#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */ 105#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */ 106#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */ 107#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */ 108#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */ 109#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */ 110#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */ 111#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */ 112#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */ 113#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */ 114#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */ 115#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */ 116#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */ 117#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */ 118#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */ 119#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */ 120#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ 121#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ 122#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ 123#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ 124#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ 125#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ 126#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ 127#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ 128#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ 129#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ 130#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ 131#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ 132#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ 133#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ 134#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ 135#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ 136#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ 137#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ 138#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ 139#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ 140#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ 141#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ 142#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ 143#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ 144#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ 145#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ 146#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ 147#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ 148#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ 149#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ 150#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ 151#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ 152#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ 153#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ 154#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ 155#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ 156#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ 157#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ 158#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ 159#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ 160#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ 161#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ 162#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ 163#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ 164#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ 165#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ 166#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ 167#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ 168#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ 169#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ 170#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ 171#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ 172#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ 173#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ 174#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ 175#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ 176#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ 177#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ 178#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ 179#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ 180#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ 181#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ 182#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ 183#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ 184#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ 185#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ 186#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ 187#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ 188#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ 189#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ 190#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ 191#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ 192#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ 193#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ 194#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ 195#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ 196#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ 197#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ 198#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ 199#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ 200#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ 201#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ 202#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ 203#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ 204#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ 205#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ 206#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ 207#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ 208#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ 209#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ 210#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ 211#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ 212#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ 213#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ 214#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ 215#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ 216#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ 217#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ 218#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ 219#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ 220#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ 221#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ 222#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ 223#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ 224#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ 225#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ 226#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ 227#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ 228#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ 229#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ 230#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ 231#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ 232#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ 233#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ 234#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ 235#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ 236#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ 237#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ 238#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ 239#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ 240#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ 241#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ 242#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ 243#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ 244#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ 245#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ 246#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ 247#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ 248#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ 249#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ 250#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ 251#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ 252#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ 253#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ 254#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ 255#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ 256#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ 257#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ 258#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ 259#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ 260#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ 261#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ 262#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ 263#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ 264#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ 265#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ 266#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ 267#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ 268#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ 269#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ 270#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ 271#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ 272#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ 273#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ 274#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ 275#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */ 276#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */ 277#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */ 278#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */ 279#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */ 280#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */ 281#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */ 282#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */ 283#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */ 284#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */ 285#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */ 286#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */ 287#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */ 288#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */ 289#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */ 290#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */ 291#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */ 292#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */ 293#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */ 294#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */ 295#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */ 296#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */ 297#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */ 298#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */ 299#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */ 300#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */ 301#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */ 302#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */ 303#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */ 304#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */ 305#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */ 306#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */ 307#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */ 308#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */ 309#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */ 310#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */ 311#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */ 312#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */ 313#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */ 314#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */ 315#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */ 316#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */ 317#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */ 318#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */ 319#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */ 320#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */ 321#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */ 322#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */ 323#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */ 324#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */ 325#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */ 326#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */ 327#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ 328#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */ 329#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */ 330#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */ 331#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */ 332#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */ 333#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */ 334#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ 335#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */ 336#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */ 337#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */ 338#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */ 339#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */ 340#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ 341#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */ 342#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */ 343#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */ 344#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */ 345#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */ 346#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */ 347#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ 348#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */ 349#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ 350#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */ 351#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */ 352#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */ 353#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ 354#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */ 355#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */ 356#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */ 357#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */ 358#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */ 359#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */ 360#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ 361#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */ 362#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ 363#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */ 364#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */ 365#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */ 366#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ 367#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */ 368#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */ 369#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */ 370#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */ 371#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */ 372#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */ 373#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ 374#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */ 375#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ 376#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */ 377#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */ 378#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */ 379#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ 380#define PPI_STATUS 0xFFC01004 /* PPI Status Register */ 381#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ 382#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ 383#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ 384#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ 385#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ 386#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ 387#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */ 388#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */ 389#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */ 390#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */ 391#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */ 392#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */ 393#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */ 394#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */ 395#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */ 396#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */ 397#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */ 398#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */ 399#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */ 400#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */ 401#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */ 402#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */ 403#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */ 404#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */ 405#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */ 406#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */ 407#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */ 408#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */ 409#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */ 410#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */ 411#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */ 412#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */ 413#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */ 414#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */ 415#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */ 416#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */ 417#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */ 418#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */ 419#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */ 420#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */ 421#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */ 422#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */ 423#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */ 424#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */ 425#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */ 426#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */ 427#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */ 428#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */ 429#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */ 430#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */ 431#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */ 432#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */ 433#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */ 434#define UART1_THR 0xFFC02000 /* Transmit Holding register */ 435#define UART1_RBR 0xFFC02000 /* Receive Buffer register */ 436#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */ 437#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */ 438#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */ 439#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */ 440#define UART1_LCR 0xFFC0200C /* Line Control Register */ 441#define UART1_MCR 0xFFC02010 /* Modem Control Register */ 442#define UART1_LSR 0xFFC02014 /* Line Status Register */ 443#define UART1_MSR 0xFFC02018 /* Modem Status Register */ 444#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */ 445#define UART1_GCTL 0xFFC02024 /* Global Control Register */ 446#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */ 447#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */ 448#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */ 449#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */ 450#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */ 451#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */ 452#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */ 453#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */ 454#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */ 455#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */ 456#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */ 457#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */ 458#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */ 459#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */ 460#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */ 461#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */ 462#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */ 463#define PORTF_MUX 0xFFC03210 /* Port F mux control */ 464#define PORTG_MUX 0xFFC03214 /* Port G mux control */ 465#define PORTH_MUX 0xFFC03218 /* Port H mux control */ 466#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */ 467#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */ 468#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */ 469#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */ 470#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */ 471#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */ 472#define NONGPIO_DRIVE 0xFFC03280 /* Non-GPIO Port drive strength control */ 473#define NONGPIO_HYSTERESIS 0xFFC03288 /* Non-GPIO Port Schmitt trigger control */ 474#define CNT_CONFIG 0xFFC03500 /* Configuration/Control Register */ 475#define CNT_IMASK 0xFFC03504 /* Interrupt Mask Register */ 476#define CNT_STATUS 0xFFC03508 /* Status Register */ 477#define CNT_COMMAND 0xFFC0350C /* Command Register */ 478#define CNT_DEBOUNCE 0xFFC03510 /* Debounce Prescaler Register */ 479#define CNT_COUNTER 0xFFC03514 /* Counter Register */ 480#define CNT_MAX 0xFFC03518 /* Maximal Count Boundary Value Register */ 481#define CNT_MIN 0xFFC0351C /* Minimal Count Boundary Value Register */ 482#define SECURE_SYSSWT 0xFFC03620 /* Secure System Switches */ 483#define SECURE_CONTROL 0xFFC03624 /* Secure Control */ 484#define SECURE_STATUS 0xFFC03628 /* Secure Status */ 485#define OTP_DATA0 0xFFC03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ 486#define OTP_DATA1 0xFFC03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ 487#define OTP_DATA2 0xFFC03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ 488#define OTP_DATA3 0xFFC0368C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */ 489#define PWM_CTRL 0xFFC03700 /* PWM Control Register */ 490#define PWM_STAT 0xFFC03704 /* PWM Status Register */ 491#define PWM_TM 0xFFC03708 /* PWM Period Register */ 492#define PWM_DT 0xFFC0370C /* PWM Dead Time Register */ 493#define PWM_GATE 0xFFC03710 /* PWM Chopping Control */ 494#define PWM_CHA 0xFFC03714 /* PWM Channel A Duty Control */ 495#define PWM_CHB 0xFFC03718 /* PWM Channel B Duty Control */ 496#define PWM_CHC 0xFFC0371C /* PWM Channel C Duty Control */ 497#define PWM_SEG 0xFFC03720 /* PWM Crossover and Output Enable */ 498#define PWM_SYNCWT 0xFFC03724 /* PWM Sync pulse width control */ 499#define PWM_CHAL 0xFFC03728 /* PWM Channel AL Duty Control (SR mode only) */ 500#define PWM_CHBL 0xFFC0372C /* PWM Channel BL Duty Control (SR mode only) */ 501#define PWM_CHCL 0xFFC03730 /* PWM Channel CL Duty Control (SR mode only) */ 502#define PWM_LSI 0xFFC03734 /* Low Side Invert (SR mode only) */ 503#define PWM_STAT2 0xFFC03738 /* PWM Status Register */ 504#define DMA_TC_CNT 0xFFC00B0C 505#define DMA_TC_PER 0xFFC00B10 506 507#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */ 508#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1) 509#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) 510#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */ 511#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1) 512#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) 513#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */ 514#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1) 515#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) 516#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */ 517#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1) 518#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE) 519#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */ 520#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1) 521#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE) 522 523#endif /* __BFIN_DEF_ADSP_BF512_proc__ */ 524