1/* 2 * Edge Port Memory Map 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26#ifndef __EPORT_H__ 27#define __EPORT_H__ 28 29/* Edge Port Module (EPORT) */ 30typedef struct eport { 31#ifdef CONFIG_MCF547x_8x 32 u16 par; /* 0x00 */ 33 u16 res0; /* 0x02 */ 34 u8 ddr; /* 0x04 */ 35 u8 ier; /* 0x05 */ 36 u16 res1; /* 0x06 */ 37 u8 dr; /* 0x08 */ 38 u8 pdr; /* 0x09 */ 39 u16 res2; /* 0x0A */ 40 u8 fr; /* 0x0C */ 41 u8 res3[3]; /* 0x0D */ 42#else 43 u16 par; /* 0x00 Pin Assignment */ 44 u8 ddr; /* 0x02 Data Direction */ 45 u8 ier; /* 0x03 Interrupt Enable */ 46 u8 dr; /* 0x04 Data */ 47 u8 pdr; /* 0x05 Pin Data */ 48 u8 fr; /* 0x06 Flag */ 49 u8 res0; 50#endif 51} eport_t; 52 53/* EPPAR */ 54#define EPORT_PAR_EPPA1(x) (((x)&0x0003)<<2) 55#define EPORT_PAR_EPPA2(x) (((x)&0x0003)<<4) 56#define EPORT_PAR_EPPA3(x) (((x)&0x0003)<<6) 57#define EPORT_PAR_EPPA4(x) (((x)&0x0003)<<8) 58#define EPORT_PAR_EPPA5(x) (((x)&0x0003)<<10) 59#define EPORT_PAR_EPPA6(x) (((x)&0x0003)<<12) 60#define EPORT_PAR_EPPA7(x) (((x)&0x0003)<<14) 61#define EPORT_PAR_LEVEL (0) 62#define EPORT_PAR_RISING (1) 63#define EPORT_PAR_FALLING (2) 64#define EPORT_PAR_BOTH (3) 65#define EPORT_PAR_EPPA7_LEVEL (0x0000) 66#define EPORT_PAR_EPPA7_RISING (0x4000) 67#define EPORT_PAR_EPPA7_FALLING (0x8000) 68#define EPORT_PAR_EPPA7_BOTH (0xC000) 69#define EPORT_PAR_EPPA6_LEVEL (0x0000) 70#define EPORT_PAR_EPPA6_RISING (0x1000) 71#define EPORT_PAR_EPPA6_FALLING (0x2000) 72#define EPORT_PAR_EPPA6_BOTH (0x3000) 73#define EPORT_PAR_EPPA5_LEVEL (0x0000) 74#define EPORT_PAR_EPPA5_RISING (0x0400) 75#define EPORT_PAR_EPPA5_FALLING (0x0800) 76#define EPORT_PAR_EPPA5_BOTH (0x0C00) 77#define EPORT_PAR_EPPA4_LEVEL (0x0000) 78#define EPORT_PAR_EPPA4_RISING (0x0100) 79#define EPORT_PAR_EPPA4_FALLING (0x0200) 80#define EPORT_PAR_EPPA4_BOTH (0x0300) 81#define EPORT_PAR_EPPA3_LEVEL (0x0000) 82#define EPORT_PAR_EPPA3_RISING (0x0040) 83#define EPORT_PAR_EPPA3_FALLING (0x0080) 84#define EPORT_PAR_EPPA3_BOTH (0x00C0) 85#define EPORT_PAR_EPPA2_LEVEL (0x0000) 86#define EPORT_PAR_EPPA2_RISING (0x0010) 87#define EPORT_PAR_EPPA2_FALLING (0x0020) 88#define EPORT_PAR_EPPA2_BOTH (0x0030) 89#define EPORT_PAR_EPPA1_LEVEL (0x0000) 90#define EPORT_PAR_EPPA1_RISING (0x0004) 91#define EPORT_PAR_EPPA1_FALLING (0x0008) 92#define EPORT_PAR_EPPA1_BOTH (0x000C) 93 94/* EPDDR */ 95#define EPORT_DDR_EPDD1 (0x02) 96#define EPORT_DDR_EPDD2 (0x04) 97#define EPORT_DDR_EPDD3 (0x08) 98#define EPORT_DDR_EPDD4 (0x10) 99#define EPORT_DDR_EPDD5 (0x20) 100#define EPORT_DDR_EPDD6 (0x40) 101#define EPORT_DDR_EPDD7 (0x80) 102 103/* EPIER */ 104#define EPORT_IER_EPIE1 (0x02) 105#define EPORT_IER_EPIE2 (0x04) 106#define EPORT_IER_EPIE3 (0x08) 107#define EPORT_IER_EPIE4 (0x10) 108#define EPORT_IER_EPIE5 (0x20) 109#define EPORT_IER_EPIE6 (0x40) 110#define EPORT_IER_EPIE7 (0x80) 111 112/* EPDR */ 113#define EPORT_DR_EPD1 (0x02) 114#define EPORT_DR_EPD2 (0x04) 115#define EPORT_DR_EPD3 (0x08) 116#define EPORT_DR_EPD4 (0x10) 117#define EPORT_DR_EPD5 (0x20) 118#define EPORT_DR_EPD6 (0x40) 119#define EPORT_DR_EPD7 (0x80) 120 121/* EPPDR */ 122#define EPORT_PDR_EPPD1 (0x02) 123#define EPORT_PDR_EPPD2 (0x04) 124#define EPORT_PDR_EPPD3 (0x08) 125#define EPORT_PDR_EPPD4 (0x10) 126#define EPORT_PDR_EPPD5 (0x20) 127#define EPORT_PDR_EPPD6 (0x40) 128#define EPORT_PDR_EPPD7 (0x80) 129 130/* EPFR */ 131#define EPORT_FR_EPF1 (0x02) 132#define EPORT_FR_EPF2 (0x04) 133#define EPORT_FR_EPF3 (0x08) 134#define EPORT_FR_EPF4 (0x10) 135#define EPORT_FR_EPF5 (0x20) 136#define EPORT_FR_EPF6 (0x40) 137#define EPORT_FR_EPF7 (0x80) 138 139#endif /* __EPORT_H__ */ 140