1/* 2 * Interrupt Controller Memory Map 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26#ifndef __INTCTRL_H__ 27#define __INTCTRL_H__ 28 29#if defined(CONFIG_M5235) || defined(CONFIG_M5271) || \ 30 defined(CONFIG_M5275) || defined(CONFIG_M5282) || \ 31 defined(CONFIG_M547x) || defined(CONFIG_M548x) 32# define CONFIG_SYS_CF_INTC_REG1 33#endif 34 35typedef struct int0_ctrl { 36 /* Interrupt Controller 0 */ 37 u32 iprh0; /* 0x00 Pending High */ 38 u32 iprl0; /* 0x04 Pending Low */ 39 u32 imrh0; /* 0x08 Mask High */ 40 u32 imrl0; /* 0x0C Mask Low */ 41 u32 frch0; /* 0x10 Force High */ 42 u32 frcl0; /* 0x14 Force Low */ 43#if defined(CONFIG_SYS_CF_INTC_REG1) 44 u8 irlr; /* 0x18 */ 45 u8 iacklpr; /* 0x19 */ 46 u16 res1[19]; /* 0x1a - 0x3c */ 47#else 48 u16 res1; /* 0x18 - 0x19 */ 49 u16 icfg0; /* 0x1A Configuration */ 50 u8 simr0; /* 0x1C Set Interrupt Mask */ 51 u8 cimr0; /* 0x1D Clear Interrupt Mask */ 52 u8 clmask0; /* 0x1E Current Level Mask */ 53 u8 slmask; /* 0x1F Saved Level Mask */ 54 u32 res2[8]; /* 0x20 - 0x3F */ 55#endif 56 u8 icr0[64]; /* 0x40 - 0x7F Control registers */ 57 u32 res3[24]; /* 0x80 - 0xDF */ 58 u8 swiack0; /* 0xE0 Software Interrupt ack */ 59 u8 res4[3]; /* 0xE1 - 0xE3 */ 60 u8 L1iack0; /* 0xE4 Level n interrupt ack */ 61 u8 res5[3]; /* 0xE5 - 0xE7 */ 62 u8 L2iack0; /* 0xE8 Level n interrupt ack */ 63 u8 res6[3]; /* 0xE9 - 0xEB */ 64 u8 L3iack0; /* 0xEC Level n interrupt ack */ 65 u8 res7[3]; /* 0xED - 0xEF */ 66 u8 L4iack0; /* 0xF0 Level n interrupt ack */ 67 u8 res8[3]; /* 0xF1 - 0xF3 */ 68 u8 L5iack0; /* 0xF4 Level n interrupt ack */ 69 u8 res9[3]; /* 0xF5 - 0xF7 */ 70 u8 L6iack0; /* 0xF8 Level n interrupt ack */ 71 u8 resa[3]; /* 0xF9 - 0xFB */ 72 u8 L7iack0; /* 0xFC Level n interrupt ack */ 73 u8 resb[3]; /* 0xFD - 0xFF */ 74} int0_t; 75 76typedef struct int1_ctrl { 77 /* Interrupt Controller 1 */ 78 u32 iprh1; /* 0x00 Pending High */ 79 u32 iprl1; /* 0x04 Pending Low */ 80 u32 imrh1; /* 0x08 Mask High */ 81 u32 imrl1; /* 0x0C Mask Low */ 82 u32 frch1; /* 0x10 Force High */ 83 u32 frcl1; /* 0x14 Force Low */ 84#if defined(CONFIG_SYS_CF_INTC_REG1) 85 u8 irlr; /* 0x18 */ 86 u8 iacklpr; /* 0x19 */ 87 u16 res1[19]; /* 0x1a - 0x3c */ 88#else 89 u16 res1; /* 0x18 */ 90 u16 icfg1; /* 0x1A Configuration */ 91 u8 simr1; /* 0x1C Set Interrupt Mask */ 92 u8 cimr1; /* 0x1D Clear Interrupt Mask */ 93 u16 res2; /* 0x1E - 0x1F */ 94 u32 res3[8]; /* 0x20 - 0x3F */ 95#endif 96 u8 icr1[64]; /* 0x40 - 0x7F */ 97 u32 res4[24]; /* 0x80 - 0xDF */ 98 u8 swiack1; /* 0xE0 Software Interrupt ack */ 99 u8 res5[3]; /* 0xE1 - 0xE3 */ 100 u8 L1iack1; /* 0xE4 Level n interrupt ack */ 101 u8 res6[3]; /* 0xE5 - 0xE7 */ 102 u8 L2iack1; /* 0xE8 Level n interrupt ack */ 103 u8 res7[3]; /* 0xE9 - 0xEB */ 104 u8 L3iack1; /* 0xEC Level n interrupt ack */ 105 u8 res8[3]; /* 0xED - 0xEF */ 106 u8 L4iack1; /* 0xF0 Level n interrupt ack */ 107 u8 res9[3]; /* 0xF1 - 0xF3 */ 108 u8 L5iack1; /* 0xF4 Level n interrupt ack */ 109 u8 resa[3]; /* 0xF5 - 0xF7 */ 110 u8 L6iack1; /* 0xF8 Level n interrupt ack */ 111 u8 resb[3]; /* 0xF9 - 0xFB */ 112 u8 L7iack1; /* 0xFC Level n interrupt ack */ 113 u8 resc[3]; /* 0xFD - 0xFF */ 114} int1_t; 115 116typedef struct intgack_ctrl1 { 117 /* Global IACK Registers */ 118 u8 swiack; /* 0x00 Global Software Interrupt ack */ 119 u8 res0[0x3]; 120 u8 gl1iack; /* 0x04 */ 121 u8 resv1[0x3]; 122 u8 gl2iack; /* 0x08 */ 123 u8 res2[0x3]; 124 u8 gl3iack; /* 0x0C */ 125 u8 res3[0x3]; 126 u8 gl4iack; /* 0x10 */ 127 u8 res4[0x3]; 128 u8 gl5iack; /* 0x14 */ 129 u8 res5[0x3]; 130 u8 gl6iack; /* 0x18 */ 131 u8 res6[0x3]; 132 u8 gl7iack; /* 0x1C */ 133 u8 res7[0x3]; 134} intgack_t; 135 136#define INTC_IPRH_INT63 (0x80000000) 137#define INTC_IPRH_INT62 (0x40000000) 138#define INTC_IPRH_INT61 (0x20000000) 139#define INTC_IPRH_INT60 (0x10000000) 140#define INTC_IPRH_INT59 (0x08000000) 141#define INTC_IPRH_INT58 (0x04000000) 142#define INTC_IPRH_INT57 (0x02000000) 143#define INTC_IPRH_INT56 (0x01000000) 144#define INTC_IPRH_INT55 (0x00800000) 145#define INTC_IPRH_INT54 (0x00400000) 146#define INTC_IPRH_INT53 (0x00200000) 147#define INTC_IPRH_INT52 (0x00100000) 148#define INTC_IPRH_INT51 (0x00080000) 149#define INTC_IPRH_INT50 (0x00040000) 150#define INTC_IPRH_INT49 (0x00020000) 151#define INTC_IPRH_INT48 (0x00010000) 152#define INTC_IPRH_INT47 (0x00008000) 153#define INTC_IPRH_INT46 (0x00004000) 154#define INTC_IPRH_INT45 (0x00002000) 155#define INTC_IPRH_INT44 (0x00001000) 156#define INTC_IPRH_INT43 (0x00000800) 157#define INTC_IPRH_INT42 (0x00000400) 158#define INTC_IPRH_INT41 (0x00000200) 159#define INTC_IPRH_INT40 (0x00000100) 160#define INTC_IPRH_INT39 (0x00000080) 161#define INTC_IPRH_INT38 (0x00000040) 162#define INTC_IPRH_INT37 (0x00000020) 163#define INTC_IPRH_INT36 (0x00000010) 164#define INTC_IPRH_INT35 (0x00000008) 165#define INTC_IPRH_INT34 (0x00000004) 166#define INTC_IPRH_INT33 (0x00000002) 167#define INTC_IPRH_INT32 (0x00000001) 168 169#define INTC_IPRL_INT31 (0x80000000) 170#define INTC_IPRL_INT30 (0x40000000) 171#define INTC_IPRL_INT29 (0x20000000) 172#define INTC_IPRL_INT28 (0x10000000) 173#define INTC_IPRL_INT27 (0x08000000) 174#define INTC_IPRL_INT26 (0x04000000) 175#define INTC_IPRL_INT25 (0x02000000) 176#define INTC_IPRL_INT24 (0x01000000) 177#define INTC_IPRL_INT23 (0x00800000) 178#define INTC_IPRL_INT22 (0x00400000) 179#define INTC_IPRL_INT21 (0x00200000) 180#define INTC_IPRL_INT20 (0x00100000) 181#define INTC_IPRL_INT19 (0x00080000) 182#define INTC_IPRL_INT18 (0x00040000) 183#define INTC_IPRL_INT17 (0x00020000) 184#define INTC_IPRL_INT16 (0x00010000) 185#define INTC_IPRL_INT15 (0x00008000) 186#define INTC_IPRL_INT14 (0x00004000) 187#define INTC_IPRL_INT13 (0x00002000) 188#define INTC_IPRL_INT12 (0x00001000) 189#define INTC_IPRL_INT11 (0x00000800) 190#define INTC_IPRL_INT10 (0x00000400) 191#define INTC_IPRL_INT9 (0x00000200) 192#define INTC_IPRL_INT8 (0x00000100) 193#define INTC_IPRL_INT7 (0x00000080) 194#define INTC_IPRL_INT6 (0x00000040) 195#define INTC_IPRL_INT5 (0x00000020) 196#define INTC_IPRL_INT4 (0x00000010) 197#define INTC_IPRL_INT3 (0x00000008) 198#define INTC_IPRL_INT2 (0x00000004) 199#define INTC_IPRL_INT1 (0x00000002) 200#define INTC_IPRL_INT0 (0x00000001) 201 202#define INTC_IMRLn_MASKALL (0x00000001) 203 204#define INTC_IRLR(x) (((x) & 0x7F) << 1) 205#define INTC_IRLR_MASK (0x01) 206 207#define INTC_IACKLPR_LVL(x) (((x) & 0x07) << 4) 208#define INTC_IACKLPR_LVL_MASK (0x8F) 209#define INTC_IACKLPR_PRI(x) ((x) & 0x0F) 210#define INTC_IACKLPR_PRI_MASK (0xF0) 211 212#if defined(CONFIG_SYS_CF_INTC_REG1) 213#define INTC_ICR_IL(x) (((x) & 0x07) << 3) 214#define INTC_ICR_IL_MASK (0xC7) 215#define INTC_ICR_IP(x) ((x) & 0x07) 216#define INTC_ICR_IP_MASK (0xF8) 217#else 218#define INTC_ICR_IL(x) ((x) & 0x07) 219#define INTC_ICR_IL_MASK (0xF8) 220#endif 221 222#define INTC_ICONFIG_ELVLPRI_MASK (0x01FF) 223#define INTC_ICONFIG_ELVLPRI7 (0x8000) 224#define INTC_ICONFIG_ELVLPRI6 (0x4000) 225#define INTC_ICONFIG_ELVLPRI5 (0x2000) 226#define INTC_ICONFIG_ELVLPRI4 (0x1000) 227#define INTC_ICONFIG_ELVLPRI3 (0x0800) 228#define INTC_ICONFIG_ELVLPRI2 (0x0400) 229#define INTC_ICONFIG_ELVLPRI1 (0x0200) 230#define INTC_ICONFIG_EMASK (0x0020) 231 232#define INTC_SIMR_ALL (0x40) 233#define INTC_SIMR(x) ((x) & 0x3F) 234#define INTC_SIMR_MASK (0x80) 235 236#define INTC_CIMR_ALL (0x40) 237#define INTC_CIMR(x) ((x) & 0x3F) 238#define INTC_CIMR_MASK (0x80) 239 240#define INTC_CLMASK(x) ((x) & 0x0F) 241#define INTC_CLMASK_MASK (0xF0) 242 243#define INTC_SLMASK(x) ((x) & 0x0F) 244#define INTC_SLMASK_MASK (0xF0) 245 246#endif /* __INTCTRL_H__ */ 247