LXR uboot/arch/m68k/include/asm/coldfire/ssi.h

   1/*
   2 * SSI Internal Memory Map
   3 *
   4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6 *
   7 * See file CREDITS for list of people who contributed to this
   8 * project.
   9 *
  10 * This program is free software; you can redistribute it and/or
  11 * modify it under the terms of the GNU General Public License as
  12 * published by the Free Software Foundation; either version 2 of
  13 * the License, or (at your option) any later version.
  14 *
  15 * This program is distributed in the hope that it will be useful,
  16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 * GNU General Public License for more details.
  19 *
  20 * You should have received a copy of the GNU General Public License
  21 * along with this program; if not, write to the Free Software
  22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23 * MA 02111-1307 USA
  24 */
  25
  26#ifndef __SSI_H__
  27#define __SSI_H__
  28
  29typedef struct ssi {
  30        u32 tx0;
  31        u32 tx1;
  32        u32 rx0;
  33        u32 rx1;
  34        u32 cr;
  35        u32 isr;
  36        u32 ier;
  37        u32 tcr;
  38        u32 rcr;
  39        u32 ccr;
  40        u8 resv0[0x4];
  41        u32 fcsr;
  42        u8 resv1[0x8];
  43        u32 acr;
  44        u32 acadd;
  45        u32 acdat;
  46        u32 atag;
  47        u32 tmask;
  48        u32 rmask;
  49} ssi_t;
  50
  51#define SSI_CR_CIS                      (0x00000200)
  52#define SSI_CR_TCH                      (0x00000100)
  53#define SSI_CR_MCE                      (0x00000080)
  54#define SSI_CR_I2S_MASK                 (0xFFFFFF9F)
  55#define SSI_CR_I2S_SLAVE                (0x00000040)
  56#define SSI_CR_I2S_MASTER               (0x00000020)
  57#define SSI_CR_I2S_NORMAL               (0x00000000)
  58#define SSI_CR_SYN                      (0x00000010)
  59#define SSI_CR_NET                      (0x00000008)
  60#define SSI_CR_RE                       (0x00000004)
  61#define SSI_CR_TE                       (0x00000002)
  62#define SSI_CR_SSI_EN                   (0x00000001)
  63
  64#define SSI_ISR_CMDAU                   (0x00040000)
  65#define SSI_ISR_CMDDU                   (0x00020000)
  66#define SSI_ISR_RXT                     (0x00010000)
  67#define SSI_ISR_RDR1                    (0x00008000)
  68#define SSI_ISR_RDR0                    (0x00004000)
  69#define SSI_ISR_TDE1                    (0x00002000)
  70#define SSI_ISR_TDE0                    (0x00001000)
  71#define SSI_ISR_ROE1                    (0x00000800)
  72#define SSI_ISR_ROE0                    (0x00000400)
  73#define SSI_ISR_TUE1                    (0x00000200)
  74#define SSI_ISR_TUE0                    (0x00000100)
  75#define SSI_ISR_TFS                     (0x00000080)
  76#define SSI_ISR_RFS                     (0x00000040)
  77#define SSI_ISR_TLS                     (0x00000020)
  78#define SSI_ISR_RLS                     (0x00000010)
  79#define SSI_ISR_RFF1                    (0x00000008)
  80#define SSI_ISR_RFF0                    (0x00000004)
  81#define SSI_ISR_TFE1                    (0x00000002)
  82#define SSI_ISR_TFE0                    (0x00000001)
  83
  84#define SSI_IER_RDMAE                   (0x00400000)
  85#define SSI_IER_RIE                     (0x00200000)
  86#define SSI_IER_TDMAE                   (0x00100000)
  87#define SSI_IER_TIE                     (0x00080000)
  88#define SSI_IER_CMDAU                   (0x00040000)
  89#define SSI_IER_CMDU                    (0x00020000)
  90#define SSI_IER_RXT                     (0x00010000)
  91#define SSI_IER_RDR1                    (0x00008000)
  92#define SSI_IER_RDR0                    (0x00004000)
  93#define SSI_IER_TDE1                    (0x00002000)
  94#define SSI_IER_TDE0                    (0x00001000)
  95#define SSI_IER_ROE1                    (0x00000800)
  96#define SSI_IER_ROE0                    (0x00000400)
  97#define SSI_IER_TUE1                    (0x00000200)
  98#define SSI_IER_TUE0                    (0x00000100)
  99#define SSI_IER_TFS                     (0x00000080)
 100#define SSI_IER_RFS                     (0x00000040)
 101#define SSI_IER_TLS                     (0x00000020)
 102#define SSI_IER_RLS                     (0x00000010)
 103#define SSI_IER_RFF1                    (0x00000008)
 104#define SSI_IER_RFF0                    (0x00000004)
 105#define SSI_IER_TFE1                    (0x00000002)
 106#define SSI_IER_TFE0                    (0x00000001)
 107
 108#define SSI_TCR_TXBIT0                  (0x00000200)
 109#define SSI_TCR_TFEN1                   (0x00000100)
 110#define SSI_TCR_TFEN0                   (0x00000080)
 111#define SSI_TCR_TFDIR                   (0x00000040)
 112#define SSI_TCR_TXDIR                   (0x00000020)
 113#define SSI_TCR_TSHFD                   (0x00000010)
 114#define SSI_TCR_TSCKP                   (0x00000008)
 115#define SSI_TCR_TFSI                    (0x00000004)
 116#define SSI_TCR_TFSL                    (0x00000002)
 117#define SSI_TCR_TEFS                    (0x00000001)
 118
 119#define SSI_RCR_RXEXT                   (0x00000400)
 120#define SSI_RCR_RXBIT0                  (0x00000200)
 121#define SSI_RCR_RFEN1                   (0x00000100)
 122#define SSI_RCR_RFEN0                   (0x00000080)
 123#define SSI_RCR_RSHFD                   (0x00000010)
 124#define SSI_RCR_RSCKP                   (0x00000008)
 125#define SSI_RCR_RFSI                    (0x00000004)
 126#define SSI_RCR_RFSL                    (0x00000002)
 127#define SSI_RCR_REFS                    (0x00000001)
 128
 129#define SSI_CCR_DIV2                    (0x00040000)
 130#define SSI_CCR_PSR                     (0x00020000)
 131#define SSI_CCR_WL(x)                   (((x) & 0x0F) << 13)
 132#define SSI_CCR_WL_MASK                 (0xFFFE1FFF)
 133#define SSI_CCR_DC(x)                   (((x)& 0x1F) << 8)
 134#define SSI_CCR_DC_MASK                 (0xFFFFE0FF)
 135#define SSI_CCR_PM(x)                   ((x) & 0xFF)
 136#define SSI_CCR_PM_MASK                 (0xFFFFFF00)
 137
 138#define SSI_FCSR_RFCNT1(x)              (((x) & 0x0F) << 28)
 139#define SSI_FCSR_RFCNT1_MASK            (0x0FFFFFFF)
 140#define SSI_FCSR_TFCNT1(x)              (((x) & 0x0F) << 24)
 141#define SSI_FCSR_TFCNT1_MASK            (0xF0FFFFFF)
 142#define SSI_FCSR_RFWM1(x)               (((x) & 0x0F) << 20)
 143#define SSI_FCSR_RFWM1_MASK             (0xFF0FFFFF)
 144#define SSI_FCSR_TFWM1(x)               (((x) & 0x0F) << 16)
 145#define SSI_FCSR_TFWM1_MASK             (0xFFF0FFFF)
 146#define SSI_FCSR_RFCNT0(x)              (((x) & 0x0F) << 12)
 147#define SSI_FCSR_RFCNT0_MASK            (0xFFFF0FFF)
 148#define SSI_FCSR_TFCNT0(x)              (((x) & 0x0F) << 8)
 149#define SSI_FCSR_TFCNT0_MASK            (0xFFFFF0FF)
 150#define SSI_FCSR_RFWM0(x)               (((x) & 0x0F) << 4)
 151#define SSI_FCSR_RFWM0_MASK             (0xFFFFFF0F)
 152#define SSI_FCSR_TFWM0(x)               ((x) & 0x0F)
 153#define SSI_FCSR_TFWM0_MASK             (0xFFFFFFF0)
 154
 155#define SSI_ACR_FRDIV(x)                (((x) & 0x3F) << 5)
 156#define SSI_ACR_FRDIV_MASK              (0xFFFFF81F)
 157#define SSI_ACR_WR                      (0x00000010)
 158#define SSI_ACR_RD                      (0x00000008)
 159#define SSI_ACR_TIF                     (0x00000004)
 160#define SSI_ACR_FV                      (0x00000002)
 161#define SSI_ACR_AC97EN                  (0x00000001)
 162
 163#define SSI_ACADD_SSI_ACADD(x)          ((x) & 0x0007FFFF)
 164
 165#define SSI_ACDAT_SSI_ACDAT(x)          ((x) & 0x0007FFFF)
 166
 167#define SSI_ATAG_DDI_ATAG(x)            ((x) & 0x0000FFFF)
 168
 169#endif                                  /* __SSI_H__ */
 170