LXR uboot/arch/powerpc/cpu/ppc4xx/cpu.c

   1/*
   2 * (C) Copyright 2000-2007
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24/*
  25 * CPU specific code
  26 *
  27 * written or collected and sometimes rewritten by
  28 * Magnus Damm <damm@bitsmart.com>
  29 *
  30 * minor modifications by
  31 * Wolfgang Denk <wd@denx.de>
  32 */
  33
  34#include <common.h>
  35#include <watchdog.h>
  36#include <command.h>
  37#include <asm/cache.h>
  38#include <asm/ppc4xx.h>
  39#include <netdev.h>
  40
  41DECLARE_GLOBAL_DATA_PTR;
  42
  43void board_reset(void);
  44
  45/*
  46 * To provide an interface to detect CPU number for boards that support
  47 * more then one CPU, we implement the "weak" default functions here.
  48 *
  49 * Returns CPU number
  50 */
  51int __get_cpu_num(void)
  52{
  53        return NA_OR_UNKNOWN_CPU;
  54}
  55int get_cpu_num(void) __attribute__((weak, alias("__get_cpu_num")));
  56
  57#if defined(CONFIG_PCI)
  58#if defined(CONFIG_405GP) || \
  59    defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
  60    defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
  61
  62#define PCI_ASYNC
  63
  64static int pci_async_enabled(void)
  65{
  66#if defined(CONFIG_405GP)
  67        return (mfdcr(CPC0_PSR) & PSR_PCI_ASYNC_EN);
  68#endif
  69
  70#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
  71    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
  72    defined(CONFIG_460EX) || defined(CONFIG_460GT)
  73        unsigned long val;
  74
  75        mfsdr(SDR0_SDSTP1, val);
  76        return (val & SDR0_SDSTP1_PAME_MASK);
  77#endif
  78}
  79#endif
  80#endif /* CONFIG_PCI */
  81
  82#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
  83    !defined(CONFIG_405) && !defined(CONFIG_405EX)
  84int pci_arbiter_enabled(void)
  85{
  86#if defined(CONFIG_405GP)
  87        return (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN);
  88#endif
  89
  90#if defined(CONFIG_405EP)
  91        return (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN);
  92#endif
  93
  94#if defined(CONFIG_440GP)
  95        return (mfdcr(CPC0_STRP1) & CPC0_STRP1_PAE_MASK);
  96#endif
  97
  98#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
  99        unsigned long val;
 100
 101        mfsdr(SDR0_XCR0, val);
 102        return (val & SDR0_XCR0_PAE_MASK);
 103#endif
 104#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
 105    defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
 106    defined(CONFIG_460EX) || defined(CONFIG_460GT)
 107        unsigned long val;
 108
 109        mfsdr(SDR0_PCI0, val);
 110        return (val & SDR0_PCI0_PAE_MASK);
 111#endif
 112}
 113#endif
 114
 115#if defined(CONFIG_405EP)
 116#define I2C_BOOTROM
 117
 118static int i2c_bootrom_enabled(void)
 119{
 120#if defined(CONFIG_405EP)
 121        return (mfdcr(CPC0_BOOT) & CPC0_BOOT_SEP);
 122#else
 123        unsigned long val;
 124
 125        mfsdr(SDR0_SDCS0, val);
 126        return (val & SDR0_SDCS_SDD);
 127#endif
 128}
 129#endif
 130
 131#if defined(CONFIG_440GX)
 132#define SDR0_PINSTP_SHIFT       29
 133static char *bootstrap_str[] = {
 134        "EBC (16 bits)",
 135        "EBC (8 bits)",
 136        "EBC (32 bits)",
 137        "EBC (8 bits)",
 138        "PCI",
 139        "I2C (Addr 0x54)",
 140        "Reserved",
 141        "I2C (Addr 0x50)",
 142};
 143static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' };
 144#endif
 145
 146#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 147#define SDR0_PINSTP_SHIFT       30
 148static char *bootstrap_str[] = {
 149        "EBC (8 bits)",
 150        "PCI",
 151        "I2C (Addr 0x54)",
 152        "I2C (Addr 0x50)",
 153};
 154static char bootstrap_char[] = { 'A', 'B', 'C', 'D'};
 155#endif
 156
 157#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 158#define SDR0_PINSTP_SHIFT       29
 159static char *bootstrap_str[] = {
 160        "EBC (8 bits)",
 161        "PCI",
 162        "NAND (8 bits)",
 163        "EBC (16 bits)",
 164        "EBC (16 bits)",
 165        "I2C (Addr 0x54)",
 166        "PCI",
 167        "I2C (Addr 0x52)",
 168};
 169static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
 170#endif
 171
 172#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 173#define SDR0_PINSTP_SHIFT       29
 174static char *bootstrap_str[] = {
 175        "EBC (8 bits)",
 176        "EBC (16 bits)",
 177        "EBC (16 bits)",
 178        "NAND (8 bits)",
 179        "PCI",
 180        "I2C (Addr 0x54)",
 181        "PCI",
 182        "I2C (Addr 0x52)",
 183};
 184static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
 185#endif
 186
 187#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
 188#define SDR0_PINSTP_SHIFT       29
 189static char *bootstrap_str[] = {
 190        "EBC (8 bits)",
 191        "EBC (16 bits)",
 192        "PCI",
 193        "PCI",
 194        "EBC (16 bits)",
 195        "NAND (8 bits)",
 196        "I2C (Addr 0x54)",      /* A8 */
 197        "I2C (Addr 0x52)",      /* A4 */
 198};
 199static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
 200#endif
 201
 202#if defined(CONFIG_460SX)
 203#define SDR0_PINSTP_SHIFT       29
 204static char *bootstrap_str[] = {
 205        "EBC (8 bits)",
 206        "EBC (16 bits)",
 207        "EBC (32 bits)",
 208        "NAND (8 bits)",
 209        "I2C (Addr 0x54)",      /* A8 */
 210        "I2C (Addr 0x52)",      /* A4 */
 211};
 212static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G' };
 213#endif
 214
 215#if defined(CONFIG_405EZ)
 216#define SDR0_PINSTP_SHIFT       28
 217static char *bootstrap_str[] = {
 218        "EBC (8 bits)",
 219        "SPI (fast)",
 220        "NAND (512 page, 4 addr cycle)",
 221        "I2C (Addr 0x50)",
 222        "EBC (32 bits)",
 223        "I2C (Addr 0x50)",
 224        "NAND (2K page, 5 addr cycle)",
 225        "I2C (Addr 0x50)",
 226        "EBC (16 bits)",
 227        "Reserved",
 228        "NAND (2K page, 4 addr cycle)",
 229        "I2C (Addr 0x50)",
 230        "NAND (512 page, 3 addr cycle)",
 231        "I2C (Addr 0x50)",
 232        "SPI (slow)",
 233        "I2C (Addr 0x50)",
 234};
 235static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \
 236                                 'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' };
 237#endif
 238
 239#if defined(CONFIG_405EX)
 240#define SDR0_PINSTP_SHIFT       29
 241static char *bootstrap_str[] = {
 242        "EBC (8 bits)",
 243        "EBC (16 bits)",
 244        "EBC (16 bits)",
 245        "NAND (8 bits)",
 246        "NAND (8 bits)",
 247        "I2C (Addr 0x54)",
 248        "EBC (8 bits)",
 249        "I2C (Addr 0x52)",
 250};
 251static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
 252#endif
 253#if defined(CONFIG_APM821XX)
 254#define SDR0_PINSTP_SHIFT       29
 255static char *bootstrap_str[] = {
 256        "RESERVED",
 257        "RESERVED",
 258        "RESERVED",
 259        "NAND (8 bits)",
 260        "NOR  (8 bits)",
 261        "NOR  (8 bits) w/PLL Bypassed",
 262        "I2C (Addr 0x54)",
 263        "I2C (Addr 0x52)",
 264};
 265static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
 266#endif
 267
 268#if defined(SDR0_PINSTP_SHIFT)
 269static int bootstrap_option(void)
 270{
 271        unsigned long val;
 272
 273        mfsdr(SDR0_PINSTP, val);
 274        return ((val & 0xf0000000) >> SDR0_PINSTP_SHIFT);
 275}
 276#endif /* SDR0_PINSTP_SHIFT */
 277
 278
 279#if defined(CONFIG_440GP)
 280static int do_chip_reset (unsigned long sys0, unsigned long sys1)
 281{
 282        /* Changes to CPC0_SYS0 and CPC0_SYS1 require chip
 283         * reset.
 284         */
 285        mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) | 0x80000000);        /* Set SWE */
 286        mtdcr (CPC0_SYS0, sys0);
 287        mtdcr (CPC0_SYS1, sys1);
 288        mtdcr (CPC0_CR0, mfdcr (CPC0_CR0) & ~0x80000000);       /* Clr SWE */
 289        mtspr (SPRN_DBCR0, 0x20000000); /* Reset the chip */
 290
 291        return 1;
 292}
 293#endif /* CONFIG_440GP */
 294
 295
 296int checkcpu (void)
 297{
 298#if !defined(CONFIG_405)        /* not used on Xilinx 405 FPGA implementations */
 299        uint pvr = get_pvr();
 300        ulong clock = gd->cpu_clk;
 301        char buf[32];
 302#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
 303        u32 reg;
 304#endif
 305
 306#if !defined(CONFIG_IOP480)
 307        char addstr[64] = "";
 308        sys_info_t sys_info;
 309        int cpu_num;
 310
 311        cpu_num = get_cpu_num();
 312        if (cpu_num >= 0)
 313                printf("CPU%d:  ", cpu_num);
 314        else
 315                puts("CPU:   ");
 316
 317        get_sys_info(&sys_info);
 318
 319#if defined(CONFIG_XILINX_440)
 320        puts("IBM PowerPC ");
 321#else
 322        puts("AMCC PowerPC ");
 323#endif
 324
 325        switch (pvr) {
 326
 327#if !defined(CONFIG_440)
 328        case PVR_405GP_RB:
 329                puts("405GP Rev. B");
 330                break;
 331
 332        case PVR_405GP_RC:
 333                puts("405GP Rev. C");
 334                break;
 335
 336        case PVR_405GP_RD:
 337                puts("405GP Rev. D");
 338                break;
 339
 340#ifdef CONFIG_405GP
 341        case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */
 342                puts("405GP Rev. E");
 343                break;
 344#endif
 345
 346        case PVR_405CR_RA:
 347                puts("405CR Rev. A");
 348                break;
 349
 350        case PVR_405CR_RB:
 351                puts("405CR Rev. B");
 352                break;
 353
 354#ifdef CONFIG_405CR
 355        case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */
 356                puts("405CR Rev. C");
 357                break;
 358#endif
 359
 360        case PVR_405GPR_RB:
 361                puts("405GPr Rev. B");
 362                break;
 363
 364        case PVR_405EP_RB:
 365                puts("405EP Rev. B");
 366                break;
 367
 368        case PVR_405EZ_RA:
 369                puts("405EZ Rev. A");
 370                break;
 371
 372        case PVR_405EX1_RA:
 373                puts("405EX Rev. A");
 374                strcpy(addstr, "Security support");
 375                break;
 376
 377        case PVR_405EXR2_RA:
 378                puts("405EXr Rev. A");
 379                strcpy(addstr, "No Security support");
 380                break;
 381
 382        case PVR_405EX1_RC:
 383                puts("405EX Rev. C");
 384                strcpy(addstr, "Security support");
 385                break;
 386
 387        case PVR_405EX2_RC:
 388                puts("405EX Rev. C");
 389                strcpy(addstr, "No Security support");
 390                break;
 391
 392        case PVR_405EXR1_RC:
 393                puts("405EXr Rev. C");
 394                strcpy(addstr, "Security support");
 395                break;
 396
 397        case PVR_405EXR2_RC:
 398                puts("405EXr Rev. C");
 399                strcpy(addstr, "No Security support");
 400                break;
 401
 402        case PVR_405EX1_RD:
 403                puts("405EX Rev. D");
 404                strcpy(addstr, "Security support");
 405                break;
 406
 407        case PVR_405EX2_RD:
 408                puts("405EX Rev. D");
 409                strcpy(addstr, "No Security support");
 410                break;
 411
 412        case PVR_405EXR1_RD:
 413                puts("405EXr Rev. D");
 414                strcpy(addstr, "Security support");
 415                break;
 416
 417        case PVR_405EXR2_RD:
 418                puts("405EXr Rev. D");
 419                strcpy(addstr, "No Security support");
 420                break;
 421
 422#else /* CONFIG_440 */
 423
 424#if defined(CONFIG_440GP)
 425        case PVR_440GP_RB:
 426                puts("440GP Rev. B");
 427                /* See errata 1.12: CHIP_4 */
 428                if ((mfdcr(CPC0_SYS0) != mfdcr(CPC0_STRP0)) ||
 429                    (mfdcr(CPC0_SYS1) != mfdcr(CPC0_STRP1)) ){
 430                        puts (  "\n\t CPC0_SYSx DCRs corrupted. "
 431                                "Resetting chip ...\n");
 432                        udelay( 1000 * 1000 ); /* Give time for serial buf to clear */
 433                        do_chip_reset ( mfdcr(CPC0_STRP0),
 434                                        mfdcr(CPC0_STRP1) );
 435                }
 436                break;
 437
 438        case PVR_440GP_RC:
 439                puts("440GP Rev. C");
 440                break;
 441#endif /* CONFIG_440GP */
 442
 443        case PVR_440GX_RA:
 444                puts("440GX Rev. A");
 445                break;
 446
 447        case PVR_440GX_RB:
 448                puts("440GX Rev. B");
 449                break;
 450
 451        case PVR_440GX_RC:
 452                puts("440GX Rev. C");
 453                break;
 454
 455        case PVR_440GX_RF:
 456                puts("440GX Rev. F");
 457                break;
 458
 459        case PVR_440EP_RA:
 460                puts("440EP Rev. A");
 461                break;
 462
 463#ifdef CONFIG_440EP
 464        case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */
 465                puts("440EP Rev. B");
 466                break;
 467
 468        case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */
 469                puts("440EP Rev. C");
 470                break;
 471#endif /*  CONFIG_440EP */
 472
 473#ifdef CONFIG_440GR
 474        case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */
 475                puts("440GR Rev. A");
 476                break;
 477
 478        case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */
 479                puts("440GR Rev. B");
 480                break;
 481#endif /* CONFIG_440GR */
 482
 483#ifdef CONFIG_440EPX
 484        case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
 485                puts("440EPx Rev. A");
 486                strcpy(addstr, "Security/Kasumi support");
 487                break;
 488
 489        case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
 490                puts("440EPx Rev. A");
 491                strcpy(addstr, "No Security/Kasumi support");
 492                break;
 493#endif /* CONFIG_440EPX */
 494
 495#ifdef CONFIG_440GRX
 496        case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
 497                puts("440GRx Rev. A");
 498                strcpy(addstr, "Security/Kasumi support");
 499                break;
 500
 501        case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */
 502                puts("440GRx Rev. A");
 503                strcpy(addstr, "No Security/Kasumi support");
 504                break;
 505#endif /* CONFIG_440GRX */
 506
 507        case PVR_440SP_6_RAB:
 508                puts("440SP Rev. A/B");
 509                strcpy(addstr, "RAID 6 support");
 510                break;
 511
 512        case PVR_440SP_RAB:
 513                puts("440SP Rev. A/B");
 514                strcpy(addstr, "No RAID 6 support");
 515                break;
 516
 517        case PVR_440SP_6_RC:
 518                puts("440SP Rev. C");
 519                strcpy(addstr, "RAID 6 support");
 520                break;
 521
 522        case PVR_440SP_RC:
 523                puts("440SP Rev. C");
 524                strcpy(addstr, "No RAID 6 support");
 525                break;
 526
 527        case PVR_440SPe_6_RA:
 528                puts("440SPe Rev. A");
 529                strcpy(addstr, "RAID 6 support");
 530                break;
 531
 532        case PVR_440SPe_RA:
 533                puts("440SPe Rev. A");
 534                strcpy(addstr, "No RAID 6 support");
 535                break;
 536
 537        case PVR_440SPe_6_RB:
 538                puts("440SPe Rev. B");
 539                strcpy(addstr, "RAID 6 support");
 540                break;
 541
 542        case PVR_440SPe_RB:
 543                puts("440SPe Rev. B");
 544                strcpy(addstr, "No RAID 6 support");
 545                break;
 546
 547#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
 548        case PVR_460EX_RA:
 549                puts("460EX Rev. A");
 550                strcpy(addstr, "No Security/Kasumi support");
 551                break;
 552
 553        case PVR_460EX_SE_RA:
 554                puts("460EX Rev. A");
 555                strcpy(addstr, "Security/Kasumi support");
 556                break;
 557
 558        case PVR_460EX_RB:
 559                puts("460EX Rev. B");
 560                mfsdr(SDR0_ECID3, reg);
 561                if (reg & 0x00100000)
 562                        strcpy(addstr, "No Security/Kasumi support");
 563                else
 564                        strcpy(addstr, "Security/Kasumi support");
 565                break;
 566
 567        case PVR_460GT_RA:
 568                puts("460GT Rev. A");
 569                strcpy(addstr, "No Security/Kasumi support");
 570                break;
 571
 572        case PVR_460GT_SE_RA:
 573                puts("460GT Rev. A");
 574                strcpy(addstr, "Security/Kasumi support");
 575                break;
 576
 577        case PVR_460GT_RB:
 578                puts("460GT Rev. B");
 579                mfsdr(SDR0_ECID3, reg);
 580                if (reg & 0x00100000)
 581                        strcpy(addstr, "No Security/Kasumi support");
 582                else
 583                        strcpy(addstr, "Security/Kasumi support");
 584                break;
 585#endif
 586
 587        case PVR_460SX_RA:
 588                puts("460SX Rev. A");
 589                strcpy(addstr, "Security support");
 590                break;
 591
 592        case PVR_460SX_RA_V1:
 593                puts("460SX Rev. A");
 594                strcpy(addstr, "No Security support");
 595                break;
 596
 597        case PVR_460GX_RA:
 598                puts("460GX Rev. A");
 599                strcpy(addstr, "Security support");
 600                break;
 601
 602        case PVR_460GX_RA_V1:
 603                puts("460GX Rev. A");
 604                strcpy(addstr, "No Security support");
 605                break;
 606
 607        case PVR_APM821XX_RA:
 608                puts("APM821XX Rev. A");
 609                strcpy(addstr, "Security support");
 610                break;
 611
 612        case PVR_VIRTEX5:
 613                puts("440x5 VIRTEX5");
 614                break;
 615#endif /* CONFIG_440 */
 616
 617        default:
 618                printf (" UNKNOWN (PVR=%08x)", pvr);
 619                break;
 620        }
 621
 622        printf (" at %s MHz (PLB=%lu OPB=%lu EBC=%lu",
 623                strmhz(buf, clock),
 624                sys_info.freqPLB / 1000000,
 625                get_OPB_freq() / 1000000,
 626                sys_info.freqEBC / 1000000);
 627#if defined(CONFIG_PCI) && \
 628        (defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
 629         defined(CONFIG_440GR) || defined(CONFIG_440GRX))
 630        printf(" PCI=%lu MHz", sys_info.freqPCI / 1000000);
 631#endif
 632        printf(")\n");
 633
 634        if (addstr[0] != 0)
 635                printf("       %s\n", addstr);
 636
 637#if defined(I2C_BOOTROM)
 638        printf ("       I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
 639#endif  /* I2C_BOOTROM */
 640#if defined(SDR0_PINSTP_SHIFT)
 641        printf ("       Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
 642        printf ("Boot ROM Location %s", bootstrap_str[bootstrap_option()]);
 643#ifdef CONFIG_NAND_U_BOOT
 644        puts(", booting from NAND");
 645#endif /* CONFIG_NAND_U_BOOT */
 646        putc('\n');
 647#endif  /* SDR0_PINSTP_SHIFT */
 648
 649#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
 650        printf ("       Internal PCI arbiter %sabled", pci_arbiter_enabled() ? "en" : "dis");
 651#endif
 652
 653#if defined(CONFIG_PCI) && defined(PCI_ASYNC)
 654        if (pci_async_enabled()) {
 655                printf (", PCI async ext clock used");
 656        } else {
 657                printf (", PCI sync clock at %lu MHz",
 658                       sys_info.freqPLB / sys_info.pllPciDiv / 1000000);
 659        }
 660#endif
 661
 662#if defined(CONFIG_PCI) && !defined(CONFIG_405EX)
 663        putc('\n');
 664#endif
 665
 666#if defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX)
 667        printf ("       16 kB I-Cache 16 kB D-Cache");
 668#elif defined(CONFIG_440)
 669        printf ("       32 kB I-Cache 32 kB D-Cache");
 670#else
 671        printf ("       16 kB I-Cache %d kB D-Cache",
 672                ((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
 673#endif
 674#endif /* !defined(CONFIG_IOP480) */
 675
 676#if defined(CONFIG_IOP480)
 677        printf ("PLX IOP480 (PVR=%08x)", pvr);
 678        printf (" at %s MHz:", strmhz(buf, clock));
 679        printf (" %u kB I-Cache", 4);
 680        printf (" %u kB D-Cache", 2);
 681#endif
 682
 683#endif /* !defined(CONFIG_405) */
 684
 685        putc ('\n');
 686
 687        return 0;
 688}
 689
 690int ppc440spe_revB() {
 691        unsigned int pvr;
 692
 693        pvr = get_pvr();
 694        if ((pvr == PVR_440SPe_6_RB) || (pvr == PVR_440SPe_RB))
 695                return 1;
 696        else
 697                return 0;
 698}
 699
 700/* ------------------------------------------------------------------------- */
 701
 702int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 703{
 704#if defined(CONFIG_BOARD_RESET)
 705        board_reset();
 706#else
 707#if defined(CONFIG_SYS_4xx_RESET_TYPE)
 708        mtspr(SPRN_DBCR0, CONFIG_SYS_4xx_RESET_TYPE << 28);
 709#else
 710        /*
 711         * Initiate system reset in debug control register DBCR
 712         */
 713        mtspr(SPRN_DBCR0, 0x30000000);
 714#endif /* defined(CONFIG_SYS_4xx_RESET_TYPE) */
 715#endif /* defined(CONFIG_BOARD_RESET) */
 716
 717        return 1;
 718}
 719
 720
 721/*
 722 * Get timebase clock frequency
 723 */
 724unsigned long get_tbclk (void)
 725{
 726#if !defined(CONFIG_IOP480)
 727        sys_info_t  sys_info;
 728
 729        get_sys_info(&sys_info);
 730        return (sys_info.freqProcessor);
 731#else
 732        return (66000000);
 733#endif
 734
 735}
 736
 737
 738#if defined(CONFIG_WATCHDOG)
 739void watchdog_reset(void)
 740{
 741        int re_enable = disable_interrupts();
 742        reset_4xx_watchdog();
 743        if (re_enable) enable_interrupts();
 744}
 745
 746void reset_4xx_watchdog(void)
 747{
 748        /*
 749         * Clear TSR(WIS) bit
 750         */
 751        mtspr(SPRN_TSR, 0x40000000);
 752}
 753#endif  /* CONFIG_WATCHDOG */
 754
 755/*
 756 * Initializes on-chip ethernet controllers.
 757 * to override, implement board_eth_init()
 758 */
 759int cpu_eth_init(bd_t *bis)
 760{
 761#if defined(CONFIG_PPC4xx_EMAC)
 762        ppc_4xx_eth_initialize(bis);
 763#endif
 764        return 0;
 765}
 766