LXR uboot/arch/powerpc/cpu/ppc4xx/tlb.c

   1/*
   2 * (C) Copyright 2007
   3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#include <common.h>
  25
  26#if defined(CONFIG_440)
  27
  28#include <asm/ppc440.h>
  29#include <asm/cache.h>
  30#include <asm/io.h>
  31#include <asm/mmu.h>
  32
  33typedef struct region {
  34        u64 base;
  35        u32 size;
  36        u32 tlb_word2_i_value;
  37} region_t;
  38
  39void remove_tlb(u32 vaddr, u32 size)
  40{
  41        int i;
  42        u32 tlb_word0_value;
  43        u32 tlb_vaddr;
  44        u32 tlb_size = 0;
  45
  46        for (i=0; i<PPC4XX_TLB_SIZE; i++) {
  47                tlb_word0_value = mftlb1(i);
  48                tlb_vaddr = TLB_WORD0_EPN_DECODE(tlb_word0_value);
  49                if (((tlb_word0_value & TLB_WORD0_V_MASK) == TLB_WORD0_V_ENABLE) &&
  50                    (tlb_vaddr >= vaddr)) {
  51                        /*
  52                         * TLB is enabled and start address is lower or equal
  53                         * than the area we are looking for. Now we only have
  54                         * to check the size/end address for a match.
  55                         */
  56                        switch (tlb_word0_value & TLB_WORD0_SIZE_MASK) {
  57                        case TLB_WORD0_SIZE_1KB:
  58                                tlb_size = 1 << 10;
  59                                break;
  60                        case TLB_WORD0_SIZE_4KB:
  61                                tlb_size = 4 << 10;
  62                                break;
  63                        case TLB_WORD0_SIZE_16KB:
  64                                tlb_size = 16 << 10;
  65                                break;
  66                        case TLB_WORD0_SIZE_64KB:
  67                                tlb_size = 64 << 10;
  68                                break;
  69                        case TLB_WORD0_SIZE_256KB:
  70                                tlb_size = 256 << 10;
  71                                break;
  72                        case TLB_WORD0_SIZE_1MB:
  73                                tlb_size = 1 << 20;
  74                                break;
  75                        case TLB_WORD0_SIZE_16MB:
  76                                tlb_size = 16 << 20;
  77                                break;
  78                        case TLB_WORD0_SIZE_256MB:
  79                                tlb_size = 256 << 20;
  80                                break;
  81                        }
  82
  83                        /*
  84                         * Now check the end-address if it's in the range
  85                         */
  86                        if ((tlb_vaddr + tlb_size - 1) <= (vaddr + size - 1))
  87                                /*
  88                                 * Found a TLB in the range.
  89                                 * Disable it by writing 0 to tlb0 word.
  90                                 */
  91                                mttlb1(i, 0);
  92                }
  93        }
  94
  95        /* Execute an ISYNC instruction so that the new TLB entry takes effect */
  96        asm("isync");
  97}
  98
  99/*
 100 * Change the I attribute (cache inhibited) of a TLB or multiple TLB's.
 101 * This function is used to either turn cache on or off in a specific
 102 * memory area.
 103 */
 104void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value)
 105{
 106        int i;
 107        u32 tlb_word0_value;
 108        u32 tlb_word2_value;
 109        u32 tlb_vaddr;
 110        u32 tlb_size = 0;
 111
 112        for (i=0; i<PPC4XX_TLB_SIZE; i++) {
 113                tlb_word0_value = mftlb1(i);
 114                tlb_vaddr = TLB_WORD0_EPN_DECODE(tlb_word0_value);
 115                if (((tlb_word0_value & TLB_WORD0_V_MASK) == TLB_WORD0_V_ENABLE) &&
 116                    (tlb_vaddr >= vaddr)) {
 117                        /*
 118                         * TLB is enabled and start address is lower or equal
 119                         * than the area we are looking for. Now we only have
 120                         * to check the size/end address for a match.
 121                         */
 122                        switch (tlb_word0_value & TLB_WORD0_SIZE_MASK) {
 123                        case TLB_WORD0_SIZE_1KB:
 124                                tlb_size = 1 << 10;
 125                                break;
 126                        case TLB_WORD0_SIZE_4KB:
 127                                tlb_size = 4 << 10;
 128                                break;
 129                        case TLB_WORD0_SIZE_16KB:
 130                                tlb_size = 16 << 10;
 131                                break;
 132                        case TLB_WORD0_SIZE_64KB:
 133                                tlb_size = 64 << 10;
 134                                break;
 135                        case TLB_WORD0_SIZE_256KB:
 136                                tlb_size = 256 << 10;
 137                                break;
 138                        case TLB_WORD0_SIZE_1MB:
 139                                tlb_size = 1 << 20;
 140                                break;
 141                        case TLB_WORD0_SIZE_16MB:
 142                                tlb_size = 16 << 20;
 143                                break;
 144                        case TLB_WORD0_SIZE_256MB:
 145                                tlb_size = 256 << 20;
 146                                break;
 147                        }
 148
 149                        /*
 150                         * Now check the end-address if it's in the range
 151                         */
 152                        if (((tlb_vaddr + tlb_size - 1) <= (vaddr + size - 1)) ||
 153                            ((tlb_vaddr < (vaddr + size - 1)) &&
 154                             ((tlb_vaddr + tlb_size - 1) > (vaddr + size - 1)))) {
 155                                /*
 156                                 * Found a TLB in the range.
 157                                 * Change cache attribute in tlb2 word.
 158                                 */
 159                                tlb_word2_value =
 160                                        TLB_WORD2_U0_DISABLE | TLB_WORD2_U1_DISABLE |
 161                                        TLB_WORD2_U2_DISABLE | TLB_WORD2_U3_DISABLE |
 162                                        TLB_WORD2_W_DISABLE | tlb_word2_i_value |
 163                                        TLB_WORD2_M_DISABLE | TLB_WORD2_G_DISABLE |
 164                                        TLB_WORD2_E_DISABLE | TLB_WORD2_UX_ENABLE |
 165                                        TLB_WORD2_UW_ENABLE | TLB_WORD2_UR_ENABLE |
 166                                        TLB_WORD2_SX_ENABLE | TLB_WORD2_SW_ENABLE |
 167                                        TLB_WORD2_SR_ENABLE;
 168
 169                                /*
 170                                 * Now either flush or invalidate the dcache
 171                                 */
 172                                if (tlb_word2_i_value)
 173                                        flush_dcache();
 174                                else
 175                                        invalidate_dcache();
 176
 177                                mttlb3(i, tlb_word2_value);
 178                                asm("iccci 0,0");
 179                        }
 180                }
 181        }
 182
 183        /* Execute an ISYNC instruction so that the new TLB entry takes effect */
 184        asm("isync");
 185}
 186
 187static int add_tlb_entry(u64 phys_addr,
 188                         u32 virt_addr,
 189                         u32 tlb_word0_size_value,
 190                         u32 tlb_word2_i_value)
 191{
 192        int i;
 193        unsigned long tlb_word0_value;
 194        unsigned long tlb_word1_value;
 195        unsigned long tlb_word2_value;
 196
 197        /* First, find the index of a TLB entry not being used */
 198        for (i=0; i<PPC4XX_TLB_SIZE; i++) {
 199                tlb_word0_value = mftlb1(i);
 200                if ((tlb_word0_value & TLB_WORD0_V_MASK) == TLB_WORD0_V_DISABLE)
 201                        break;
 202        }
 203        if (i >= PPC4XX_TLB_SIZE)
 204                return -1;
 205
 206        /* Second, create the TLB entry */
 207        tlb_word0_value = TLB_WORD0_EPN_ENCODE(virt_addr) | TLB_WORD0_V_ENABLE |
 208                TLB_WORD0_TS_0 | tlb_word0_size_value;
 209        tlb_word1_value = TLB_WORD1_RPN_ENCODE((u32)phys_addr) |
 210                TLB_WORD1_ERPN_ENCODE(phys_addr >> 32);
 211        tlb_word2_value = TLB_WORD2_U0_DISABLE | TLB_WORD2_U1_DISABLE |
 212                TLB_WORD2_U2_DISABLE | TLB_WORD2_U3_DISABLE |
 213                TLB_WORD2_W_DISABLE | tlb_word2_i_value |
 214                TLB_WORD2_M_DISABLE | TLB_WORD2_G_DISABLE |
 215                TLB_WORD2_E_DISABLE | TLB_WORD2_UX_ENABLE |
 216                TLB_WORD2_UW_ENABLE | TLB_WORD2_UR_ENABLE |
 217                TLB_WORD2_SX_ENABLE | TLB_WORD2_SW_ENABLE |
 218                TLB_WORD2_SR_ENABLE;
 219
 220        /* Wait for all memory accesses to complete */
 221        sync();
 222
 223        /* Third, add the TLB entries */
 224        mttlb1(i, tlb_word0_value);
 225        mttlb2(i, tlb_word1_value);
 226        mttlb3(i, tlb_word2_value);
 227
 228        /* Execute an ISYNC instruction so that the new TLB entry takes effect */
 229        asm("isync");
 230
 231        return 0;
 232}
 233
 234static void program_tlb_addr(u64 phys_addr,
 235                             u32 virt_addr,
 236                             u32 mem_size,
 237                             u32 tlb_word2_i_value)
 238{
 239        int rc;
 240        int tlb_i;
 241
 242        tlb_i = tlb_word2_i_value;
 243        while (mem_size != 0) {
 244                rc = 0;
 245                /* Add the TLB entries in to map the region. */
 246                if (((phys_addr & TLB_256MB_ALIGN_MASK) == phys_addr) &&
 247                    (mem_size >= TLB_256MB_SIZE)) {
 248                        /* Add a 256MB TLB entry */
 249                        if ((rc = add_tlb_entry(phys_addr, virt_addr,
 250                                                TLB_WORD0_SIZE_256MB, tlb_i)) == 0) {
 251                                mem_size -= TLB_256MB_SIZE;
 252                                phys_addr += TLB_256MB_SIZE;
 253                                virt_addr += TLB_256MB_SIZE;
 254                        }
 255                } else if (((phys_addr & TLB_16MB_ALIGN_MASK) == phys_addr) &&
 256                           (mem_size >= TLB_16MB_SIZE)) {
 257                        /* Add a 16MB TLB entry */
 258                        if ((rc = add_tlb_entry(phys_addr, virt_addr,
 259                                                TLB_WORD0_SIZE_16MB, tlb_i)) == 0) {
 260                                mem_size -= TLB_16MB_SIZE;
 261                                phys_addr += TLB_16MB_SIZE;
 262                                virt_addr += TLB_16MB_SIZE;
 263                        }
 264                } else if (((phys_addr & TLB_1MB_ALIGN_MASK) == phys_addr) &&
 265                           (mem_size >= TLB_1MB_SIZE)) {
 266                        /* Add a 1MB TLB entry */
 267                        if ((rc = add_tlb_entry(phys_addr, virt_addr,
 268                                                TLB_WORD0_SIZE_1MB, tlb_i)) == 0) {
 269                                mem_size -= TLB_1MB_SIZE;
 270                                phys_addr += TLB_1MB_SIZE;
 271                                virt_addr += TLB_1MB_SIZE;
 272                        }
 273                } else if (((phys_addr & TLB_256KB_ALIGN_MASK) == phys_addr) &&
 274                           (mem_size >= TLB_256KB_SIZE)) {
 275                        /* Add a 256KB TLB entry */
 276                        if ((rc = add_tlb_entry(phys_addr, virt_addr,
 277                                                TLB_WORD0_SIZE_256KB, tlb_i)) == 0) {
 278                                mem_size -= TLB_256KB_SIZE;
 279                                phys_addr += TLB_256KB_SIZE;
 280                                virt_addr += TLB_256KB_SIZE;
 281                        }
 282                } else if (((phys_addr & TLB_64KB_ALIGN_MASK) == phys_addr) &&
 283                           (mem_size >= TLB_64KB_SIZE)) {
 284                        /* Add a 64KB TLB entry */
 285                        if ((rc = add_tlb_entry(phys_addr, virt_addr,
 286                                                TLB_WORD0_SIZE_64KB, tlb_i)) == 0) {
 287                                mem_size -= TLB_64KB_SIZE;
 288                                phys_addr += TLB_64KB_SIZE;
 289                                virt_addr += TLB_64KB_SIZE;
 290                        }
 291                } else if (((phys_addr & TLB_16KB_ALIGN_MASK) == phys_addr) &&
 292                           (mem_size >= TLB_16KB_SIZE)) {
 293                        /* Add a 16KB TLB entry */
 294                        if ((rc = add_tlb_entry(phys_addr, virt_addr,
 295                                                TLB_WORD0_SIZE_16KB, tlb_i)) == 0) {
 296                                mem_size -= TLB_16KB_SIZE;
 297                                phys_addr += TLB_16KB_SIZE;
 298                                virt_addr += TLB_16KB_SIZE;
 299                        }
 300                } else if (((phys_addr & TLB_4KB_ALIGN_MASK) == phys_addr) &&
 301                           (mem_size >= TLB_4KB_SIZE)) {
 302                        /* Add a 4KB TLB entry */
 303                        if ((rc = add_tlb_entry(phys_addr, virt_addr,
 304                                                TLB_WORD0_SIZE_4KB, tlb_i)) == 0) {
 305                                mem_size -= TLB_4KB_SIZE;
 306                                phys_addr += TLB_4KB_SIZE;
 307                                virt_addr += TLB_4KB_SIZE;
 308                        }
 309                } else if (((phys_addr & TLB_1KB_ALIGN_MASK) == phys_addr) &&
 310                           (mem_size >= TLB_1KB_SIZE)) {
 311                        /* Add a 1KB TLB entry */
 312                        if ((rc = add_tlb_entry(phys_addr, virt_addr,
 313                                                TLB_WORD0_SIZE_1KB, tlb_i)) == 0) {
 314                                mem_size -= TLB_1KB_SIZE;
 315                                phys_addr += TLB_1KB_SIZE;
 316                                virt_addr += TLB_1KB_SIZE;
 317                        }
 318                } else {
 319                        printf("ERROR: no TLB size exists for the base address 0x%llx.\n",
 320                                phys_addr);
 321                }
 322
 323                if (rc != 0)
 324                        printf("ERROR: no TLB entries available for the base addr 0x%llx.\n",
 325                                phys_addr);
 326        }
 327
 328        return;
 329}
 330
 331/*
 332 * Program one (or multiple) TLB entries for one memory region
 333 *
 334 * Common usage for boards with SDRAM DIMM modules to dynamically
 335 * configure the TLB's for the SDRAM
 336 */
 337void program_tlb(u64 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value)
 338{
 339        region_t region_array;
 340
 341        region_array.base = phys_addr;
 342        region_array.size = size;
 343        region_array.tlb_word2_i_value = tlb_word2_i_value;     /* en-/disable cache */
 344
 345        /* Call the routine to add in the tlb entries for the memory regions */
 346        program_tlb_addr(region_array.base, virt_addr, region_array.size,
 347                         region_array.tlb_word2_i_value);
 348
 349        return;
 350}
 351
 352#endif /* CONFIG_440 */
 353