1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35#include <common.h>
36#include <command.h>
37#include <kgdb.h>
38#include <asm/processor.h>
39
40DECLARE_GLOBAL_DATA_PTR;
41
42
43extern unsigned long search_exception_table(unsigned long);
44
45
46
47#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize)
48
49static __inline__ unsigned long get_esr(void)
50{
51 unsigned long val;
52
53#if defined(CONFIG_440)
54 asm volatile("mfspr %0, 0x03e" : "=r" (val) :);
55#else
56 asm volatile("mfesr %0" : "=r" (val) :);
57#endif
58 return val;
59}
60
61#define ESR_MCI 0x80000000
62#define ESR_PIL 0x08000000
63#define ESR_PPR 0x04000000
64#define ESR_PTR 0x02000000
65#define ESR_DST 0x00800000
66#define ESR_DIZ 0x00400000
67#define ESR_U0F 0x00008000
68
69#if defined(CONFIG_CMD_BEDBUG)
70extern void do_bedbug_breakpoint(struct pt_regs *);
71#endif
72
73
74
75
76
77void
78print_backtrace(unsigned long *sp)
79{
80 int cnt = 0;
81 unsigned long i;
82
83 printf("Call backtrace: ");
84 while (sp) {
85 if ((uint)sp > END_OF_MEM)
86 break;
87
88 i = sp[1];
89 if (cnt++ % 7 == 0)
90 printf("\n");
91 printf("%08lX ", i);
92 if (cnt > 32) break;
93 sp = (unsigned long *)*sp;
94 }
95 printf("\n");
96}
97
98void show_regs(struct pt_regs * regs)
99{
100 int i;
101
102 printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DEAR: %08lX\n",
103 regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar);
104 printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n",
105 regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0,
106 regs->msr & MSR_FP ? 1 : 0,regs->msr&MSR_ME ? 1 : 0,
107 regs->msr&MSR_IR ? 1 : 0,
108 regs->msr&MSR_DR ? 1 : 0);
109
110 printf("\n");
111 for (i = 0; i < 32; i++) {
112 if ((i % 8) == 0) {
113 printf("GPR%02d: ", i);
114 }
115
116 printf("%08lX ", regs->gpr[i]);
117 if ((i % 8) == 7) {
118 printf("\n");
119 }
120 }
121}
122
123
124void
125_exception(int signr, struct pt_regs *regs)
126{
127 show_regs(regs);
128 print_backtrace((unsigned long *)regs->gpr[1]);
129 panic("Exception");
130}
131
132void
133MachineCheckException(struct pt_regs *regs)
134{
135 unsigned long fixup, val;
136#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
137 u32 value2;
138 int corr_ecc = 0;
139 int uncorr_ecc = 0;
140#endif
141
142 if ((fixup = search_exception_table(regs->nip)) != 0) {
143 regs->nip = fixup;
144 val = mfspr(MCSR);
145
146 mtspr(SPRN_MCSR, val);
147 return;
148 }
149
150#if defined(CONFIG_CMD_KGDB)
151 if (debugger_exception_handler && (*debugger_exception_handler)(regs))
152 return;
153#endif
154
155 printf("Machine Check Exception.\n");
156 printf("Caused by (from msr): ");
157 printf("regs %p ", regs);
158
159 val = get_esr();
160
161#if !defined(CONFIG_440) && !defined(CONFIG_405EX)
162 if (val& ESR_IMCP) {
163 printf("Instruction");
164 mtspr(ESR, val & ~ESR_IMCP);
165 } else {
166 printf("Data");
167 }
168 printf(" machine check.\n");
169
170#elif defined(CONFIG_440) || defined(CONFIG_405EX)
171 if (val& ESR_IMCP){
172 printf("Instruction Synchronous Machine Check exception\n");
173 mtspr(SPRN_ESR, val & ~ESR_IMCP);
174 } else {
175 val = mfspr(MCSR);
176 if (val & MCSR_IB)
177 printf("Instruction Read PLB Error\n");
178#if defined(CONFIG_440)
179 if (val & MCSR_DRB)
180 printf("Data Read PLB Error\n");
181 if (val & MCSR_DWB)
182 printf("Data Write PLB Error\n");
183#else
184 if (val & MCSR_DB)
185 printf("Data PLB Error\n");
186#endif
187 if (val & MCSR_TLBP)
188 printf("TLB Parity Error\n");
189 if (val & MCSR_ICP){
190
191 printf("I-Cache Parity Error\n");
192 }
193 if (val & MCSR_DCSP)
194 printf("D-Cache Search Parity Error\n");
195 if (val & MCSR_DCFP)
196 printf("D-Cache Flush Parity Error\n");
197 if (val & MCSR_IMPE)
198 printf("Machine Check exception is imprecise\n");
199
200
201 mtspr(SPRN_MCSR, val);
202 }
203
204#if defined(CONFIG_DDR_ECC) && defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2)
205
206
207
208
209
210 mfsdram(SDRAM_ECCES, val);
211 if (val & SDRAM_ECCES_CE)
212 printf("ECC: Correctable error\n");
213 if (val & SDRAM_ECCES_UE) {
214 printf("ECC: Uncorrectable error at 0x%02x%08x\n",
215 mfdcr(SDRAM_ERRADDULL), mfdcr(SDRAM_ERRADDLLL));
216 }
217#endif
218
219#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
220 mfsdram(DDR0_00, val) ;
221 printf("DDR0: DDR0_00 %lx\n", val);
222 val = (val >> 16) & 0xff;
223 if (val & 0x80)
224 printf("DDR0: At least one interrupt active\n");
225 if (val & 0x40)
226 printf("DDR0: DRAM initialization complete.\n");
227 if (val & 0x20) {
228 printf("DDR0: Multiple uncorrectable ECC events.\n");
229 uncorr_ecc = 1;
230 }
231 if (val & 0x10) {
232 printf("DDR0: Single uncorrectable ECC event.\n");
233 uncorr_ecc = 1;
234 }
235 if (val & 0x08) {
236 printf("DDR0: Multiple correctable ECC events.\n");
237 corr_ecc = 1;
238 }
239 if (val & 0x04) {
240 printf("DDR0: Single correctable ECC event.\n");
241 corr_ecc = 1;
242 }
243 if (val & 0x02)
244 printf("Multiple accesses outside the defined"
245 " physical memory space detected\n");
246 if (val & 0x01)
247 printf("DDR0: Single access outside the defined"
248 " physical memory space detected.\n");
249
250 mfsdram(DDR0_01, val);
251 val = (val >> 8) & 0x7;
252 switch (val ) {
253 case 0:
254 printf("DDR0: Write Out-of-Range command\n");
255 break;
256 case 1:
257 printf("DDR0: Read Out-of-Range command\n");
258 break;
259 case 2:
260 printf("DDR0: Masked write Out-of-Range command\n");
261 break;
262 case 4:
263 printf("DDR0: Wrap write Out-of-Range command\n");
264 break;
265 case 5:
266 printf("DDR0: Wrap read Out-of-Range command\n");
267 break;
268 default:
269 mfsdram(DDR0_01, value2);
270 printf("DDR0: No DDR0 error know 0x%lx %x\n", val, value2);
271 }
272 mfsdram(DDR0_23, val);
273 if (((val >> 16) & 0xff) && corr_ecc)
274 printf("DDR0: Syndrome for correctable ECC event 0x%lx\n",
275 (val >> 16) & 0xff);
276 mfsdram(DDR0_23, val);
277 if (((val >> 8) & 0xff) && uncorr_ecc)
278 printf("DDR0: Syndrome for uncorrectable ECC event 0x%lx\n",
279 (val >> 8) & 0xff);
280 mfsdram(DDR0_33, val);
281 if (val)
282 printf("DDR0: Address of command that caused an "
283 "Out-of-Range interrupt %lx\n", val);
284 mfsdram(DDR0_34, val);
285 if (val && uncorr_ecc)
286 printf("DDR0: Address of uncorrectable ECC event %lx\n", val);
287 mfsdram(DDR0_35, val);
288 if (val && uncorr_ecc)
289 printf("DDR0: Address of uncorrectable ECC event %lx\n", val);
290 mfsdram(DDR0_36, val);
291 if (val && uncorr_ecc)
292 printf("DDR0: Data of uncorrectable ECC event 0x%08lx\n", val);
293 mfsdram(DDR0_37, val);
294 if (val && uncorr_ecc)
295 printf("DDR0: Data of uncorrectable ECC event 0x%08lx\n", val);
296 mfsdram(DDR0_38, val);
297 if (val && corr_ecc)
298 printf("DDR0: Address of correctable ECC event %lx\n", val);
299 mfsdram(DDR0_39, val);
300 if (val && corr_ecc)
301 printf("DDR0: Address of correctable ECC event %lx\n", val);
302 mfsdram(DDR0_40, val);
303 if (val && corr_ecc)
304 printf("DDR0: Data of correctable ECC event 0x%08lx\n", val);
305 mfsdram(DDR0_41, val);
306 if (val && corr_ecc)
307 printf("DDR0: Data of correctable ECC event 0x%08lx\n", val);
308#endif
309#endif
310 show_regs(regs);
311 print_backtrace((unsigned long *)regs->gpr[1]);
312 panic("machine check");
313}
314
315void
316AlignmentException(struct pt_regs *regs)
317{
318#if defined(CONFIG_CMD_KGDB)
319 if (debugger_exception_handler && (*debugger_exception_handler)(regs))
320 return;
321#endif
322
323 show_regs(regs);
324 print_backtrace((unsigned long *)regs->gpr[1]);
325 panic("Alignment Exception");
326}
327
328void
329ProgramCheckException(struct pt_regs *regs)
330{
331 long esr_val;
332
333#if defined(CONFIG_CMD_KGDB)
334 if (debugger_exception_handler && (*debugger_exception_handler)(regs))
335 return;
336#endif
337
338 show_regs(regs);
339
340 esr_val = get_esr();
341 if( esr_val & ESR_PIL )
342 printf( "** Illegal Instruction **\n" );
343 else if( esr_val & ESR_PPR )
344 printf( "** Privileged Instruction **\n" );
345 else if( esr_val & ESR_PTR )
346 printf( "** Trap Instruction **\n" );
347
348 print_backtrace((unsigned long *)regs->gpr[1]);
349 panic("Program Check Exception");
350}
351
352void
353DecrementerPITException(struct pt_regs *regs)
354{
355
356
357
358 mtspr(SPRN_TSR, 0x08000000);
359
360
361
362
363 timer_interrupt(NULL);
364}
365
366
367void
368UnknownException(struct pt_regs *regs)
369{
370#if defined(CONFIG_CMD_KGDB)
371 if (debugger_exception_handler && (*debugger_exception_handler)(regs))
372 return;
373#endif
374
375 printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
376 regs->nip, regs->msr, regs->trap);
377 _exception(0, regs);
378}
379
380void
381DebugException(struct pt_regs *regs)
382{
383 printf("Debugger trap at @ %lx\n", regs->nip );
384 show_regs(regs);
385#if defined(CONFIG_CMD_BEDBUG)
386 do_bedbug_breakpoint( regs );
387#endif
388}
389
390
391
392
393int
394addr_probe(uint *addr)
395{
396#if 0
397 int retval;
398
399 __asm__ __volatile__( \
400 "1: lwz %0,0(%1)\n" \
401 " eieio\n" \
402 " li %0,0\n" \
403 "2:\n" \
404 ".section .fixup,\"ax\"\n" \
405 "3: li %0,-1\n" \
406 " b 2b\n" \
407 ".section __ex_table,\"a\"\n" \
408 " .align 2\n" \
409 " .long 1b,3b\n" \
410 ".text" \
411 : "=r" (retval) : "r"(addr));
412
413 return (retval);
414#endif
415 return 0;
416}
417
