LXR uboot/board/davedenx/qong/qong.c

   1/*
   2 *
   3 * (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#include <common.h>
  25#include <netdev.h>
  26#include <asm/arch/mx31.h>
  27#include <asm/arch/mx31-regs.h>
  28#include <asm/io.h>
  29#include <nand.h>
  30#include <fsl_pmic.h>
  31#include <mxc_gpio.h>
  32#include "qong_fpga.h"
  33
  34DECLARE_GLOBAL_DATA_PTR;
  35
  36int dram_init (void)
  37{
  38        /* dram_init must store complete ramsize in gd->ram_size */
  39        gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE,
  40                                PHYS_SDRAM_1_SIZE);
  41        return 0;
  42}
  43
  44static void qong_fpga_reset(void)
  45{
  46        mxc_gpio_set(QONG_FPGA_RST_PIN, 0);
  47        udelay(30);
  48        mxc_gpio_set(QONG_FPGA_RST_PIN, 1);
  49
  50        udelay(300);
  51}
  52
  53int board_early_init_f (void)
  54{
  55#ifdef CONFIG_QONG_FPGA
  56        /* CS1: FPGA/Network Controller/GPIO */
  57        /* 16-bit, no DTACK */
  58        __REG(CSCR_U(1)) = 0x00000A01;
  59        __REG(CSCR_L(1)) = 0x20040501;
  60        __REG(CSCR_A(1)) = 0x04020C00;
  61
  62        /* setup pins for FPGA */
  63        mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO));
  64        mx31_gpio_mux(IOMUX_MODE(0x7e, MUX_CTL_GPIO));
  65        mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO));
  66        mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO));
  67        mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO));
  68
  69        /* FPGA reset  Pin */
  70        /* rstn = 0 */
  71        mxc_gpio_set(QONG_FPGA_RST_PIN, 0);
  72        mxc_gpio_direction(QONG_FPGA_RST_PIN, MXC_GPIO_DIRECTION_OUT);
  73
  74        /* set interrupt pin as input */
  75        mxc_gpio_direction(QONG_FPGA_IRQ_PIN, MXC_GPIO_DIRECTION_IN);
  76
  77        /* FPGA JTAG Interface */
  78        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS6, MUX_CTL_GPIO));
  79        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK6, MUX_CTL_GPIO));
  80        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CAPTURE, MUX_CTL_GPIO));
  81        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_COMPARE, MUX_CTL_GPIO));
  82        mxc_gpio_direction(QONG_FPGA_TCK_PIN, MXC_GPIO_DIRECTION_OUT);
  83        mxc_gpio_direction(QONG_FPGA_TMS_PIN, MXC_GPIO_DIRECTION_OUT);
  84        mxc_gpio_direction(QONG_FPGA_TDI_PIN, MXC_GPIO_DIRECTION_OUT);
  85        mxc_gpio_direction(QONG_FPGA_TDO_PIN, MXC_GPIO_DIRECTION_IN);
  86#endif
  87
  88        /* setup pins for UART1 */
  89        mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
  90        mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
  91        mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
  92        mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
  93
  94        /* setup pins for SPI (pmic) */
  95        mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
  96        mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
  97        mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
  98        mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
  99        mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
 100
 101        /* Setup pins for USB2 Host */
 102        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_CLK, MUX_CTL_FUNC));
 103        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DIR, MUX_CTL_FUNC));
 104        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_NXT, MUX_CTL_FUNC));
 105        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC));
 106        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC));
 107        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC));
 108        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD3, MUX_CTL_FUNC));
 109        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD3, MUX_CTL_FUNC));
 110        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK3, MUX_CTL_FUNC));
 111        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS3, MUX_CTL_FUNC));
 112        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD6, MUX_CTL_FUNC));
 113        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD6, MUX_CTL_FUNC));
 114
 115#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
 116                        PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
 117
 118        mx31_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
 119        mx31_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
 120        mx31_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
 121        mx31_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
 122        mx31_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
 123        mx31_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
 124        mx31_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG);       /* USBH2_DATA2 */
 125        mx31_set_pad(MX31_PIN_STXD6, H2_PAD_CFG);       /* USBH2_DATA3 */
 126        mx31_set_pad(MX31_PIN_SFS3, H2_PAD_CFG);        /* USBH2_DATA4 */
 127        mx31_set_pad(MX31_PIN_SCK3, H2_PAD_CFG);        /* USBH2_DATA5 */
 128        mx31_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG);       /* USBH2_DATA6 */
 129        mx31_set_pad(MX31_PIN_STXD3, H2_PAD_CFG);       /* USBH2_DATA7 */
 130
 131        writel(readl((IOMUXC_BASE + 0x8)) | (1 << 11), IOMUXC_BASE + 0x8);
 132
 133        return 0;
 134
 135}
 136
 137int board_init (void)
 138{
 139        /* Chip selects */
 140        /* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */
 141        /* Assumptions: HCLK = 133 MHz, tACC = 130ns */
 142        __REG(CSCR_U(0)) = ((0 << 31)   | /* SP */
 143                                                (0 << 30)       | /* WP */
 144                                                (0 << 28)       | /* BCD */
 145                                                (0 << 24)       | /* BCS */
 146                                                (0 << 22)       | /* PSZ */
 147                                                (0 << 21)       | /* PME */
 148                                                (0 << 20)       | /* SYNC */
 149                                                (0 << 16)       | /* DOL */
 150                                                (3 << 14)       | /* CNC */
 151                                                (21 << 8)       | /* WSC */
 152                                                (0 << 7)        | /* EW */
 153                                                (0 << 4)        | /* WWS */
 154                                                (6 << 0)          /* EDC */
 155                                           );
 156
 157        __REG(CSCR_L(0)) = ((2 << 28)   | /* OEA */
 158                                                (1 << 24)       | /* OEN */
 159                                                (3 << 20)       | /* EBWA */
 160                                                (3 << 16)       | /* EBWN */
 161                                                (1 << 12)       | /* CSA */
 162                                                (1 << 11)       | /* EBC */
 163                                                (5 << 8)        | /* DSZ */
 164                                                (1 << 4)        | /* CSN */
 165                                                (0 << 3)        | /* PSR */
 166                                                (0 << 2)        | /* CRE */
 167                                                (0 << 1)        | /* WRAP */
 168                                                (1 << 0)          /* CSEN */
 169                                           );
 170
 171        __REG(CSCR_A(0)) = ((2 << 28)   | /* EBRA */
 172                                                (1 << 24)       | /* EBRN */
 173                                                (2 << 20)       | /* RWA */
 174                                                (2 << 16)       | /* RWN */
 175                                                (0 << 15)       | /* MUM */
 176                                                (0 << 13)       | /* LAH */
 177                                                (2 << 10)       | /* LBN */
 178                                                (0 << 8)        | /* LBA */
 179                                                (0 << 6)        | /* DWW */
 180                                                (0 << 4)        | /* DCT */
 181                                                (0 << 3)        | /* WWU */
 182                                                (0 << 2)        | /* AGE */
 183                                                (0 << 1)        | /* CNC2 */
 184                                                (0 << 0)          /* FCE */
 185                                           );
 186
 187        /* board id for linux */
 188        gd->bd->bi_arch_number = MACH_TYPE_QONG;
 189        gd->bd->bi_boot_params = (0x80000100);  /* adress of boot parameters */
 190
 191        qong_fpga_init();
 192
 193        return 0;
 194}
 195
 196int board_late_init(void)
 197{
 198        u32 val;
 199
 200        /* Enable RTC battery */
 201        val = pmic_reg_read(REG_POWER_CTL0);
 202        pmic_reg_write(REG_POWER_CTL0, val | COINCHEN);
 203        pmic_reg_write(REG_INT_STATUS1, RTCRSTI);
 204
 205        return 0;
 206}
 207
 208int checkboard (void)
 209{
 210        printf("Board: DAVE/DENX Qong\n");
 211        return 0;
 212}
 213
 214int misc_init_r (void)
 215{
 216#ifdef CONFIG_QONG_FPGA
 217        u32 tmp;
 218
 219        tmp = *(volatile u32*)QONG_FPGA_CTRL_VERSION;
 220        printf("FPGA:  ");
 221        printf("version register = %u.%u.%u\n",
 222                (tmp & 0xF000) >> 12, (tmp & 0x0F00) >> 8, tmp & 0x00FF);
 223#endif
 224        return 0;
 225}
 226
 227int board_eth_init(bd_t *bis)
 228{
 229#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_DNET)
 230        return dnet_eth_initialize(0, (void *)CONFIG_DNET_BASE, -1);
 231#else
 232        return 0;
 233#endif
 234}
 235
 236#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT)
 237static void board_nand_setup(void)
 238{
 239
 240        /* CS3: NAND 8-bit */
 241        __REG(CSCR_U(3)) = 0x00004f00;
 242        __REG(CSCR_L(3)) = 0x20013b31;
 243        __REG(CSCR_A(3)) = 0x00020800;
 244        __REG(IOMUXC_GPR) |= 1 << 13;
 245
 246        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO));
 247        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO));
 248        mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_RB, MUX_CTL_IN_GPIO));
 249
 250        /* Make sure to reset the fpga else you cannot access NAND */
 251        qong_fpga_reset();
 252
 253        /* Enable NAND flash */
 254        mxc_gpio_set(15, 1);
 255        mxc_gpio_set(14, 1);
 256        mxc_gpio_direction(15, MXC_GPIO_DIRECTION_OUT);
 257        mxc_gpio_direction(16, MXC_GPIO_DIRECTION_IN);
 258        mxc_gpio_direction(14, MXC_GPIO_DIRECTION_IN);
 259        mxc_gpio_set(15, 0);
 260
 261}
 262
 263int qong_nand_rdy(void *chip)
 264{
 265        udelay(1);
 266        return mxc_gpio_get(16);
 267}
 268
 269void qong_nand_select_chip(struct mtd_info *mtd, int chip)
 270{
 271        if (chip >= 0)
 272                mxc_gpio_set(15, 0);
 273        else
 274                mxc_gpio_set(15, 1);
 275
 276}
 277
 278void qong_nand_plat_init(void *chip)
 279{
 280        struct nand_chip *nand = (struct nand_chip *)chip;
 281        nand->chip_delay = 20;
 282        nand->select_chip = qong_nand_select_chip;
 283        nand->options &= ~NAND_BUSWIDTH_16;
 284        board_nand_setup();
 285}
 286
 287#endif
 288