LXR uboot/board/freescale/m5271evb/m5271evb.c

   1/*
   2 * (C) Copyright 2000-2006
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#include <common.h>
  25#include <asm/immap.h>
  26
  27int checkboard (void) {
  28        puts ("Board: Freescale M5271EVB\n");
  29        return 0;
  30};
  31
  32phys_size_t initdram (int board_type) {
  33
  34        int i;
  35
  36        /* Enable Address lines 23-21 and lower 16bits of data path */
  37        mbar_writeByte(MCF_GPIO_PAR_AD, MCF_GPIO_AD_ADDR23 |
  38                        MCF_GPIO_AD_ADDR22 | MCF_GPIO_AD_ADDR21 |
  39                        MCF_GPIO_AD_DATAL);
  40
  41        /* Set CS2 pin to be SD_CS0 */
  42        mbar_writeByte(MCF_GPIO_PAR_CS, mbar_readByte(MCF_GPIO_PAR_CS)
  43                        | MCF_GPIO_PAR_CS_PAR_CS2);
  44
  45        /* Configure SDRAM Control Pin Assignemnt Register */
  46        mbar_writeByte(MCF_GPIO_PAR_SDRAM, MCF_GPIO_SDRAM_CSSDCS_00 |
  47                        MCF_GPIO_SDRAM_SDWE | MCF_GPIO_SDRAM_SCAS |
  48                        MCF_GPIO_SDRAM_SRAS | MCF_GPIO_SDRAM_SCKE |
  49                        MCF_GPIO_SDRAM_SDCS_11);
  50        asm(" nop");
  51
  52        /*
  53         * Check to see if the SDRAM has already been initialized
  54         * by a run control tool
  55         */
  56        if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) {
  57                /* Initialize DRAM Control Register: DCR */
  58                mbar_writeShort(MCF_SDRAMC_DCR,
  59                                MCF_SDRAMC_DCR_RTIM(2)
  60                                | MCF_SDRAMC_DCR_RC(0x2E));
  61                asm(" nop");
  62
  63                /*
  64                 * Initialize DACR0
  65                 *
  66                 * CASL: 01
  67                 * CBM: cmd at A20, bank select bits 21 and up
  68                 * PS: 32bit port size
  69                 */
  70                mbar_writeLong(MCF_SDRAMC_DACR0,
  71                                MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18)
  72                                | MCF_SDRAMC_DACRn_CASL(1)
  73                                | MCF_SDRAMC_DACRn_CBM(3)
  74                                | MCF_SDRAMC_DACRn_PS(0));
  75                asm(" nop");
  76
  77                /* Initialize DMR0 */
  78                mbar_writeLong(MCF_SDRAMC_DMR0,
  79                                MCF_SDRAMC_DMRn_BAM_16M
  80                                | MCF_SDRAMC_DMRn_V);
  81                asm(" nop");
  82
  83                /* Set IP bit in DACR */
  84                mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
  85                                | MCF_SDRAMC_DACRn_IP);
  86                asm(" nop");
  87
  88                /* Wait at least 20ns to allow banks to precharge */
  89                for (i = 0; i < 5; i++)
  90                        asm(" nop");
  91
  92                /* Write to this block to initiate precharge */
  93                *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
  94                asm(" nop");
  95
  96                /* Set RE bit in DACR */
  97                mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
  98                                | MCF_SDRAMC_DACRn_RE);
  99
 100                /* Wait for at least 8 auto refresh cycles to occur */
 101                for (i = 0; i < 2000; i++)
 102                        asm(" nop");
 103
 104                /* Finish the configuration by issuing the MRS */
 105                mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
 106                                | MCF_SDRAMC_DACRn_MRS);
 107                asm(" nop");
 108
 109                /*
 110                 * Write to the SDRAM Mode Register A0-A11 = 0x400
 111                 *
 112                 * Write Burst Mode = Programmed Burst Length
 113                 * Op Mode = Standard Op
 114                 * CAS Latency = 2
 115                 * Burst Type = Sequential
 116                 * Burst Length = 1
 117                 */
 118                *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xa5a5a5a5;
 119                asm(" nop");
 120        }
 121
 122        return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 123};
 124
 125int testdram (void) {
 126
 127        /* TODO: XXX XXX XXX */
 128        printf ("DRAM test not implemented!\n");
 129
 130        return (0);
 131}
 132