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23#include <common.h>
24#include <command.h>
25#include <pci.h>
26#include <asm/processor.h>
27#include <asm/mmu.h>
28#include <asm/cache.h>
29#include <asm/immap_85xx.h>
30#include <asm/fsl_pci.h>
31#include <asm/fsl_ddr_sdram.h>
32#include <asm/io.h>
33#include <asm/fsl_serdes.h>
34#include <spd.h>
35#include <miiphy.h>
36#include <libfdt.h>
37#include <spd_sdram.h>
38#include <fdt_support.h>
39#include <tsec.h>
40#include <netdev.h>
41#include <sata.h>
42
43#include "../common/sgmii_riser.h"
44
45phys_size_t fixed_sdram(void);
46
47int board_early_init_f (void)
48{
49#ifdef CONFIG_MMC
50 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
51
52 setbits_be32(&gur->pmuxcr,
53 (MPC85xx_PMUXCR_SD_DATA |
54 MPC85xx_PMUXCR_SDHC_CD |
55 MPC85xx_PMUXCR_SDHC_WP));
56
57#endif
58 return 0;
59}
60
61int checkboard (void)
62{
63 u8 vboot;
64 u8 *pixis_base = (u8 *)PIXIS_BASE;
65
66 puts("Board: MPC8536DS ");
67#ifdef CONFIG_PHYS_64BIT
68 puts("(36-bit addrmap) ");
69#endif
70
71 printf ("Sys ID: 0x%02x, "
72 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
73 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
74 in_8(pixis_base + PIXIS_PVER));
75
76 vboot = in_8(pixis_base + PIXIS_VBOOT);
77 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) {
78 case PIXIS_VBOOT_LBMAP_NOR0:
79 puts ("vBank: 0\n");
80 break;
81 case PIXIS_VBOOT_LBMAP_NOR1:
82 puts ("vBank: 1\n");
83 break;
84 case PIXIS_VBOOT_LBMAP_NOR2:
85 puts ("vBank: 2\n");
86 break;
87 case PIXIS_VBOOT_LBMAP_NOR3:
88 puts ("vBank: 3\n");
89 break;
90 case PIXIS_VBOOT_LBMAP_PJET:
91 puts ("Promjet\n");
92 break;
93 case PIXIS_VBOOT_LBMAP_NAND:
94 puts ("NAND\n");
95 break;
96 }
97
98 return 0;
99}
100
101phys_size_t
102initdram(int board_type)
103{
104 phys_size_t dram_size = 0;
105
106 puts("Initializing....");
107
108#ifdef CONFIG_SPD_EEPROM
109 dram_size = fsl_ddr_sdram();
110#else
111 dram_size = fixed_sdram();
112#endif
113 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
114 dram_size *= 0x100000;
115
116 puts(" DDR: ");
117 return dram_size;
118}
119
120#if !defined(CONFIG_SPD_EEPROM)
121
122
123
124
125phys_size_t fixed_sdram (void)
126{
127 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
128 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
129 uint d_init;
130
131 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
132 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
133
134 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
135 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
136 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
137 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
138 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
139 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
140 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
141 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
142 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
143 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
144
145#if defined (CONFIG_DDR_ECC)
146 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
147 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
148 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
149#endif
150 asm("sync;isync");
151
152 udelay(500);
153
154 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
155
156#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
157 d_init = 1;
158 debug("DDR - 1st controller: memory initializing\n");
159
160
161
162
163 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
164 udelay(1000);
165 }
166 debug("DDR: memory initialized\n\n");
167 asm("sync; isync");
168 udelay(500);
169#endif
170
171 return 512 * 1024 * 1024;
172}
173
174#endif
175
176#ifdef CONFIG_PCI1
177static struct pci_controller pci1_hose;
178#endif
179
180#ifdef CONFIG_PCIE1
181static struct pci_controller pcie1_hose;
182#endif
183
184#ifdef CONFIG_PCIE2
185static struct pci_controller pcie2_hose;
186#endif
187
188#ifdef CONFIG_PCIE3
189static struct pci_controller pcie3_hose;
190#endif
191
192#ifdef CONFIG_PCI
193void pci_init_board(void)
194{
195 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
196 struct fsl_pci_info pci_info[4];
197 u32 devdisr, pordevsr, io_sel, sdrs2_io_sel;
198 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
199 int first_free_busno = 0;
200 int num = 0;
201
202 int pcie_ep, pcie_configured;
203
204 devdisr = in_be32(&gur->devdisr);
205 pordevsr = in_be32(&gur->pordevsr);
206 porpllsr = in_be32(&gur->porpllsr);
207 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
208 sdrs2_io_sel = (pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
209
210 debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x\n",
211 devdisr, sdrs2_io_sel, io_sel);
212
213 if (sdrs2_io_sel == 7)
214 printf("Serdes2 disalbed\n");
215 else if (sdrs2_io_sel == 4) {
216 printf("eTSEC1 is in sgmii mode.\n");
217 printf("eTSEC3 is in sgmii mode.\n");
218 } else if (sdrs2_io_sel == 6)
219 printf("eTSEC1 is in sgmii mode.\n");
220
221 puts("\n");
222#ifdef CONFIG_PCIE3
223 pcie_configured = is_serdes_configured(PCIE3);
224
225 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
226 set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M,
227 LAW_TRGT_IF_PCIE_3);
228 set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K,
229 LAW_TRGT_IF_PCIE_3);
230 SET_STD_PCIE_INFO(pci_info[num], 3);
231 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
232 printf("PCIE3: connected to Slot3 as %s (base address %lx)\n",
233 pcie_ep ? "Endpoint" : "Root Complex",
234 pci_info[num].regs);
235 first_free_busno = fsl_pci_init_port(&pci_info[num++],
236 &pcie3_hose, first_free_busno);
237 } else {
238 printf("PCIE3: disabled\n");
239 }
240
241 puts("\n");
242#else
243 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3);
244#endif
245
246#ifdef CONFIG_PCIE1
247 pcie_configured = is_serdes_configured(PCIE1);
248
249 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
250 set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M,
251 LAW_TRGT_IF_PCIE_1);
252 set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K,
253 LAW_TRGT_IF_PCIE_1);
254 SET_STD_PCIE_INFO(pci_info[num], 1);
255 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
256 printf("PCIE1: connected to Slot1 as %s (base address %lx)\n",
257 pcie_ep ? "Endpoint" : "Root Complex",
258 pci_info[num].regs);
259 first_free_busno = fsl_pci_init_port(&pci_info[num++],
260 &pcie1_hose, first_free_busno);
261 } else {
262 printf("PCIE1: disabled\n");
263 }
264
265 puts("\n");
266#else
267 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE);
268#endif
269
270#ifdef CONFIG_PCIE2
271 pcie_configured = is_serdes_configured(PCIE2);
272
273 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
274 set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M,
275 LAW_TRGT_IF_PCIE_2);
276 set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K,
277 LAW_TRGT_IF_PCIE_2);
278 SET_STD_PCIE_INFO(pci_info[num], 2);
279 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
280 printf("PCIE2: connected to Slot 2 as %s (base address %lx)\n",
281 pcie_ep ? "Endpoint" : "Root Complex",
282 pci_info[num].regs);
283 first_free_busno = fsl_pci_init_port(&pci_info[num++],
284 &pcie2_hose, first_free_busno);
285 } else {
286 printf("PCIE2: disabled\n");
287 }
288
289 puts("\n");
290#else
291 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2);
292#endif
293
294#ifdef CONFIG_PCI1
295 pci_speed = 66666000;
296 pci_32 = 1;
297 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
298 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
299
300 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
301 set_next_law(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M,
302 LAW_TRGT_IF_PCI);
303 set_next_law(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K,
304 LAW_TRGT_IF_PCI);
305 SET_STD_PCI_INFO(pci_info[num], 1);
306 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
307 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
308 (pci_32) ? 32 : 64,
309 (pci_speed == 33333000) ? "33" :
310 (pci_speed == 66666000) ? "66" : "unknown",
311 pci_clk_sel ? "sync" : "async",
312 pci_agent ? "agent" : "host",
313 pci_arb ? "arbiter" : "external-arbiter",
314 pci_info[num].regs);
315
316 first_free_busno = fsl_pci_init_port(&pci_info[num++],
317 &pci1_hose, first_free_busno);
318 } else {
319 printf("PCI: disabled\n");
320 }
321
322 puts("\n");
323#else
324 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
325#endif
326}
327#endif
328
329int board_early_init_r(void)
330{
331 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
332 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
333
334
335
336
337
338
339
340 flush_dcache();
341 invalidate_icache();
342
343
344 disable_tlb(flash_esel);
345
346 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
347 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
348 0, flash_esel, BOOKE_PAGESZ_256M, 1);
349
350 return 0;
351}
352
353int board_eth_init(bd_t *bis)
354{
355#ifdef CONFIG_TSEC_ENET
356 struct tsec_info_struct tsec_info[2];
357 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
358 int num = 0;
359 uint sdrs2_io_sel =
360 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
361
362#ifdef CONFIG_TSEC1
363 SET_STD_TSEC_INFO(tsec_info[num], 1);
364 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) {
365 tsec_info[num].phyaddr = 0;
366 tsec_info[num].flags |= TSEC_SGMII;
367 }
368 num++;
369#endif
370#ifdef CONFIG_TSEC3
371 SET_STD_TSEC_INFO(tsec_info[num], 3);
372 if (sdrs2_io_sel == 4) {
373 tsec_info[num].phyaddr = 1;
374 tsec_info[num].flags |= TSEC_SGMII;
375 }
376 num++;
377#endif
378
379 if (!num) {
380 printf("No TSECs initialized\n");
381 return 0;
382 }
383
384#ifdef CONFIG_FSL_SGMII_RISER
385 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6))
386 fsl_sgmii_riser_init(tsec_info, num);
387#endif
388
389 tsec_eth_init(bis, tsec_info, num);
390#endif
391 return pci_eth_init(bis);
392}
393
394#if defined(CONFIG_OF_BOARD_SETUP)
395void ft_board_setup(void *blob, bd_t *bd)
396{
397 ft_cpu_setup(blob, bd);
398
399 FT_FSL_PCI_SETUP;
400
401#ifdef CONFIG_FSL_SGMII_RISER
402 fsl_sgmii_riser_fdt_fixup(blob);
403#endif
404}
405#endif
406
