LXR uboot/board/icecube/icecube.c

   1/*
   2 * (C) Copyright 2003
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * (C) Copyright 2004
   6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
   7 *
   8 * See file CREDITS for list of people who contributed to this
   9 * project.
  10 *
  11 * This program is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU General Public License as
  13 * published by the Free Software Foundation; either version 2 of
  14 * the License, or (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 * MA 02111-1307 USA
  25 */
  26
  27#include <common.h>
  28#include <mpc5xxx.h>
  29#include <pci.h>
  30#include <asm/processor.h>
  31#include <libfdt.h>
  32#include <netdev.h>
  33
  34#if defined(CONFIG_LITE5200B)
  35#include "mt46v32m16.h"
  36#else
  37# if defined(CONFIG_MPC5200_DDR)
  38#  include "mt46v16m16-75.h"
  39# else
  40#include "mt48lc16m16a2-75.h"
  41# endif
  42#endif
  43
  44#ifdef CONFIG_LITE5200B_PM
  45/* u-boot part of low-power mode implementation */
  46#define SAVED_ADDR (*(void **)0x00000000)
  47#define PSC2_4 0x02
  48
  49void lite5200b_wakeup(void)
  50{
  51        unsigned char wakeup_pin;
  52        void (*linux_wakeup)(void);
  53
  54        /* check PSC2_4, if it's down "QT" is signaling we have a wakeup
  55         * from low power mode */
  56        *(vu_char *)MPC5XXX_WU_GPIO_ENABLE = PSC2_4;
  57        __asm__ volatile ("sync");
  58
  59        wakeup_pin = *(vu_char *)MPC5XXX_WU_GPIO_DATA_I;
  60        if (wakeup_pin & PSC2_4)
  61                return;
  62
  63        /* acknowledge to "QT"
  64         * by holding pin at 1 for 10 uS */
  65        *(vu_char *)MPC5XXX_WU_GPIO_DIR = PSC2_4;
  66        __asm__ volatile ("sync");
  67        *(vu_char *)MPC5XXX_WU_GPIO_DATA_O = PSC2_4;
  68        __asm__ volatile ("sync");
  69        udelay(10);
  70
  71        /* put ram out of self-refresh */
  72        *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x80000000;   /* mode_en */
  73        __asm__ volatile ("sync");
  74        *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x50000000;   /* cke ref_en */
  75        __asm__ volatile ("sync");
  76        *(vu_long *)MPC5XXX_SDRAM_CTRL &= ~0x80000000;  /* !mode_en */
  77        __asm__ volatile ("sync");
  78        udelay(10); /* wait a bit */
  79
  80        /* jump back to linux kernel code */
  81        linux_wakeup = SAVED_ADDR;
  82        printf("\n\nLooks like we just woke, transferring control to 0x%08lx\n",
  83                        (unsigned long)linux_wakeup);
  84        linux_wakeup();
  85}
  86#else
  87#define lite5200b_wakeup()
  88#endif
  89
  90#ifndef CONFIG_SYS_RAMBOOT
  91static void sdram_start (int hi_addr)
  92{
  93        long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  94
  95        /* unlock mode register */
  96        *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
  97        __asm__ volatile ("sync");
  98
  99        /* precharge all banks */
 100        *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
 101        __asm__ volatile ("sync");
 102
 103#if SDRAM_DDR
 104        /* set mode register: extended mode */
 105        *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
 106        __asm__ volatile ("sync");
 107
 108        /* set mode register: reset DLL */
 109        *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
 110        __asm__ volatile ("sync");
 111#endif
 112
 113        /* precharge all banks */
 114        *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
 115        __asm__ volatile ("sync");
 116
 117        /* auto refresh */
 118        *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
 119        __asm__ volatile ("sync");
 120
 121        /* set mode register */
 122        *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
 123        __asm__ volatile ("sync");
 124
 125        /* normal operation */
 126        *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
 127        __asm__ volatile ("sync");
 128}
 129#endif
 130
 131/*
 132 * ATTENTION: Although partially referenced initdram does NOT make real use
 133 *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
 134 *            is something else than 0x00000000.
 135 */
 136
 137phys_size_t initdram (int board_type)
 138{
 139        ulong dramsize = 0;
 140        ulong dramsize2 = 0;
 141        uint svr, pvr;
 142
 143#ifndef CONFIG_SYS_RAMBOOT
 144        ulong test1, test2;
 145
 146        /* setup SDRAM chip selects */
 147        *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
 148        *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
 149        __asm__ volatile ("sync");
 150
 151        /* setup config registers */
 152        *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
 153        *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
 154        __asm__ volatile ("sync");
 155
 156#if SDRAM_DDR
 157        /* set tap delay */
 158        *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
 159        __asm__ volatile ("sync");
 160#endif
 161
 162        /* find RAM size using SDRAM CS0 only */
 163        sdram_start(0);
 164        test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 165        sdram_start(1);
 166        test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 167        if (test1 > test2) {
 168                sdram_start(0);
 169                dramsize = test1;
 170        } else {
 171                dramsize = test2;
 172        }
 173
 174        /* memory smaller than 1MB is impossible */
 175        if (dramsize < (1 << 20)) {
 176                dramsize = 0;
 177        }
 178
 179        /* set SDRAM CS0 size according to the amount of RAM found */
 180        if (dramsize > 0) {
 181                *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
 182        } else {
 183                *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
 184        }
 185
 186        /* let SDRAM CS1 start right after CS0 */
 187        *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
 188
 189        /* find RAM size using SDRAM CS1 only */
 190        if (!dramsize)
 191                sdram_start(0);
 192        test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 193        if (!dramsize) {
 194                sdram_start(1);
 195                test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 196        }
 197        if (test1 > test2) {
 198                sdram_start(0);
 199                dramsize2 = test1;
 200        } else {
 201                dramsize2 = test2;
 202        }
 203
 204        /* memory smaller than 1MB is impossible */
 205        if (dramsize2 < (1 << 20)) {
 206                dramsize2 = 0;
 207        }
 208
 209        /* set SDRAM CS1 size according to the amount of RAM found */
 210        if (dramsize2 > 0) {
 211                *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
 212                        | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
 213        } else {
 214                *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 215        }
 216
 217#else /* CONFIG_SYS_RAMBOOT */
 218
 219        /* retrieve size of memory connected to SDRAM CS0 */
 220        dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
 221        if (dramsize >= 0x13) {
 222                dramsize = (1 << (dramsize - 0x13)) << 20;
 223        } else {
 224                dramsize = 0;
 225        }
 226
 227        /* retrieve size of memory connected to SDRAM CS1 */
 228        dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
 229        if (dramsize2 >= 0x13) {
 230                dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
 231        } else {
 232                dramsize2 = 0;
 233        }
 234
 235#endif /* CONFIG_SYS_RAMBOOT */
 236
 237        /*
 238         * On MPC5200B we need to set the special configuration delay in the
 239         * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
 240         * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
 241         *
 242         * "The SDelay should be written to a value of 0x00000004. It is
 243         * required to account for changes caused by normal wafer processing
 244         * parameters."
 245         */
 246        svr = get_svr();
 247        pvr = get_pvr();
 248        if ((SVR_MJREV(svr) >= 2) &&
 249            (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
 250
 251                *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
 252                __asm__ volatile ("sync");
 253        }
 254
 255        lite5200b_wakeup();
 256
 257        return dramsize + dramsize2;
 258}
 259
 260int checkboard (void)
 261{
 262#if defined (CONFIG_LITE5200B)
 263        puts ("Board: Freescale Lite5200B\n");
 264#else
 265        puts ("Board: Motorola MPC5200 (IceCube)\n");
 266#endif
 267        return 0;
 268}
 269
 270void flash_preinit(void)
 271{
 272        /*
 273         * Now, when we are in RAM, enable flash write
 274         * access for detection process.
 275         * Note that CS_BOOT cannot be cleared when
 276         * executing in flash.
 277         */
 278        *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 279}
 280
 281void flash_afterinit(ulong size)
 282{
 283        if (size == 0x800000) { /* adjust mapping */
 284                *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
 285                        START_REG(CONFIG_SYS_BOOTCS_START | size);
 286                *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
 287                        STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
 288        }
 289}
 290
 291#ifdef  CONFIG_PCI
 292static struct pci_controller hose;
 293
 294extern void pci_mpc5xxx_init(struct pci_controller *);
 295
 296void pci_init_board(void)
 297{
 298        pci_mpc5xxx_init(&hose);
 299}
 300#endif
 301
 302#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
 303
 304void init_ide_reset (void)
 305{
 306        debug ("init_ide_reset\n");
 307
 308        /* Configure PSC1_4 as GPIO output for ATA reset */
 309        *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
 310        *(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
 311        /* Deassert reset */
 312        *(vu_long *) MPC5XXX_WU_GPIO_DATA_O   |= GPIO_PSC1_4;
 313}
 314
 315void ide_set_reset (int idereset)
 316{
 317        debug ("ide_reset(%d)\n", idereset);
 318
 319        if (idereset) {
 320                *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
 321                /* Make a delay. MPC5200 spec says 25 usec min */
 322                udelay(500000);
 323        } else {
 324                *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
 325        }
 326}
 327#endif
 328
 329#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 330void
 331ft_board_setup(void *blob, bd_t *bd)
 332{
 333        ft_cpu_setup(blob, bd);
 334}
 335#endif
 336
 337int board_eth_init(bd_t *bis)
 338{
 339        cpu_eth_init(bis); /* Built in FEC comes first */
 340        return pci_eth_init(bis);
 341}
 342