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31#include <common.h>
32#include <i2c.h>
33#include <nand.h>
34#include <netdev.h>
35#include <miiphy.h>
36#include <asm/io.h>
37#include <asm/arch/kirkwood.h>
38#include <asm/arch/mpp.h>
39
40#include "../common/common.h"
41
42DECLARE_GLOBAL_DATA_PTR;
43
44static int io_dev;
45extern I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf);
46
47
48u32 kwmpp_config[] = {
49 MPP0_NF_IO2,
50 MPP1_NF_IO3,
51 MPP2_NF_IO4,
52 MPP3_NF_IO5,
53 MPP4_NF_IO6,
54 MPP5_NF_IO7,
55 MPP6_SYSRST_OUTn,
56 MPP7_PEX_RST_OUTn,
57#if defined(CONFIG_SOFT_I2C)
58 MPP8_GPIO,
59 MPP9_GPIO,
60#endif
61#if defined(CONFIG_HARD_I2C)
62 MPP8_TW_SDA,
63 MPP9_TW_SCK,
64#endif
65 MPP10_UART0_TXD,
66 MPP11_UART0_RXD,
67 MPP12_GPO,
68 MPP13_UART1_TXD,
69 MPP14_UART1_RXD,
70 MPP15_GPIO,
71 MPP16_GPIO,
72 MPP17_GPIO,
73 MPP18_NF_IO0,
74 MPP19_NF_IO1,
75 MPP20_GPIO,
76 MPP21_GPIO,
77 MPP22_GPIO,
78 MPP23_GPIO,
79 MPP24_GPIO,
80 MPP25_GPIO,
81 MPP26_GPIO,
82 MPP27_GPIO,
83 MPP28_GPIO,
84 MPP29_GPIO,
85 MPP30_GPIO,
86 MPP31_GPIO,
87 MPP32_GPIO,
88 MPP33_GPIO,
89 MPP34_GPIO,
90 MPP35_GPIO,
91 MPP36_GPIO,
92 MPP37_GPIO,
93 MPP38_GPIO,
94 MPP39_GPIO,
95 MPP40_GPIO,
96 MPP41_GPIO,
97 MPP42_GPIO,
98 MPP43_GPIO,
99 MPP44_GPIO,
100 MPP45_GPIO,
101 MPP46_GPIO,
102 MPP47_GPIO,
103 MPP48_GPIO,
104 MPP49_GPIO,
105 0
106};
107
108int ethernet_present(void)
109{
110 uchar buf;
111 int ret = 0;
112
113 if (i2c_read(0x10, 2, 1, &buf, 1) != 0) {
114 printf ("%s: Error reading Boco\n", __FUNCTION__);
115 return -1;
116 }
117 if ((buf & 0x40) == 0x40) {
118 ret = 1;
119 }
120 return ret;
121}
122
123int misc_init_r(void)
124{
125 I2C_MUX_DEVICE *i2cdev;
126 char *str;
127 int mach_type;
128
129
130 i2cdev = i2c_mux_ident_muxstring((uchar *)"pca9554a:70:a");
131 io_dev = i2cdev->busid;
132 puts("Piggy:");
133 if (ethernet_present() == 0)
134 puts (" not");
135 puts(" present\n");
136
137 str = getenv("mach_type");
138 if (str != NULL) {
139 mach_type = simple_strtoul(str, NULL, 10);
140 printf("Overwriting MACH_TYPE with %d!!!\n", mach_type);
141 gd->bd->bi_arch_number = mach_type;
142 }
143 return 0;
144}
145
146int board_early_init_f(void)
147{
148 u32 tmp;
149
150 kirkwood_mpp_conf(kwmpp_config);
151
152
153
154
155
156
157 tmp = readl(KW_GPIO0_BASE);
158 writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
159 tmp = readl(KW_GPIO0_BASE + 4);
160 writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
161 printf("KM: setting NAND mode\n");
162
163#if defined(CONFIG_SOFT_I2C)
164
165 kw_gpio_set_valid(SUEN3_SDA_PIN, 1);
166 kw_gpio_set_valid(SUEN3_SCL_PIN, 1);
167 kw_gpio_direction_output(SUEN3_SDA_PIN, 0);
168 kw_gpio_direction_output(SUEN3_SCL_PIN, 0);
169#endif
170#if defined(CONFIG_SYS_EEPROM_WREN)
171 kw_gpio_set_valid(SUEN3_ENV_WP, 38);
172 kw_gpio_direction_output(SUEN3_ENV_WP, 1);
173#endif
174
175 return 0;
176}
177
178int board_init(void)
179{
180
181
182
183 gd->bd->bi_arch_number = MACH_TYPE_SUEN3;
184
185
186 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
187
188 return 0;
189}
190
191#if defined(CONFIG_CMD_SF)
192int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
193{
194 u32 tmp;
195 if (argc < 2)
196 return cmd_usage(cmdtp);
197
198 if ((strcmp(argv[1], "off") == 0)) {
199 printf("SPI FLASH disabled, NAND enabled\n");
200
201 kwmpp_config[0] = MPP0_NF_IO2;
202 kwmpp_config[1] = MPP1_NF_IO3;
203 kwmpp_config[2] = MPP2_NF_IO4;
204 kwmpp_config[3] = MPP3_NF_IO5;
205
206 kirkwood_mpp_conf(kwmpp_config);
207 tmp = readl(KW_GPIO0_BASE);
208 writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
209 } else if ((strcmp(argv[1], "on") == 0)) {
210 printf("SPI FLASH enabled, NAND disabled\n");
211
212 kwmpp_config[0] = MPP0_SPI_SCn;
213 kwmpp_config[1] = MPP1_SPI_MOSI;
214 kwmpp_config[2] = MPP2_SPI_SCK;
215 kwmpp_config[3] = MPP3_SPI_MISO;
216
217 kirkwood_mpp_conf(kwmpp_config);
218 tmp = readl(KW_GPIO0_BASE);
219 writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE);
220 } else {
221 return cmd_usage(cmdtp);
222 }
223
224 return 0;
225}
226
227U_BOOT_CMD(
228 spitoggle, 2, 0, do_spi_toggle,
229 "En-/disable SPI FLASH access",
230 "<on|off> - Enable (on) or disable (off) SPI FLASH access\n"
231 );
232#endif
233
234int dram_init(void)
235{
236
237
238 gd->ram_size = get_ram_size((volatile void *)kw_sdram_bar(0),
239 kw_sdram_bs(0));
240 return 0;
241}
242
243void dram_init_banksize(void)
244{
245 int i;
246
247 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
248 gd->bd->bi_dram[i].start = kw_sdram_bar(i);
249 gd->bd->bi_dram[i].size = kw_sdram_bs(i);
250 gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i),
251 kw_sdram_bs(i));
252 }
253}
254
255
256void reset_phy(void)
257{
258 char *name = "egiga0";
259
260 if (miiphy_set_current_dev(name))
261 return;
262
263
264 miiphy_reset(name, CONFIG_PHY_BASE_ADR);
265}
266
267#if defined(CONFIG_HUSH_INIT_VAR)
268int hush_init_var (void)
269{
270 ivm_read_eeprom ();
271 return 0;
272}
273#endif
274
275#if defined(CONFIG_BOOTCOUNT_LIMIT)
276void bootcount_store (ulong a)
277{
278 volatile ulong *save_addr;
279 volatile ulong size = 0;
280 int i;
281 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
282 size += gd->bd->bi_dram[i].size;
283 }
284 save_addr = (ulong*)(size - BOOTCOUNT_ADDR);
285 writel(a, save_addr);
286 writel(BOOTCOUNT_MAGIC, &save_addr[1]);
287}
288
289ulong bootcount_load (void)
290{
291 volatile ulong *save_addr;
292 volatile ulong size = 0;
293 int i;
294 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
295 size += gd->bd->bi_dram[i].size;
296 }
297 save_addr = (ulong*)(size - BOOTCOUNT_ADDR);
298 if (readl(&save_addr[1]) != BOOTCOUNT_MAGIC)
299 return 0;
300 else
301 return readl(save_addr);
302}
303#endif
304
305#if defined(CONFIG_SOFT_I2C)
306void set_sda (int state)
307{
308 I2C_ACTIVE;
309 I2C_SDA(state);
310}
311
312void set_scl (int state)
313{
314 I2C_SCL(state);
315}
316
317int get_sda (void)
318{
319 I2C_TRISTATE;
320 return I2C_READ;
321}
322
323int get_scl (void)
324{
325 return (kw_gpio_get_value(SUEN3_SCL_PIN) ? 1 : 0);
326}
327#endif
328
329#if defined(CONFIG_SYS_EEPROM_WREN)
330int eeprom_write_enable (unsigned dev_addr, int state)
331{
332 kw_gpio_set_value(SUEN3_ENV_WP, !state);
333
334 return !kw_gpio_get_value(SUEN3_ENV_WP);
335}
336#endif
337
