LXR uboot/board/ti/omap2420h4/omap2420h4.c

   1/*
   2 * (C) Copyright 2004
   3 * Texas Instruments, <www.ti.com>
   4 * Richard Woodruff <r-woodruff2@ti.com>
   5 *
   6 * See file CREDITS for list of people who contributed to this
   7 * project.
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License as
  11 * published by the Free Software Foundation; either version 2 of
  12 * the License, or (at your option) any later version.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 * MA 02111-1307 USA
  23 */
  24#include <common.h>
  25#include <netdev.h>
  26#include <asm/arch/omap2420.h>
  27#include <asm/io.h>
  28#include <asm/arch/bits.h>
  29#include <asm/arch/mux.h>
  30#include <asm/arch/sys_proto.h>
  31#include <asm/arch/sys_info.h>
  32#include <asm/arch/mem.h>
  33#include <i2c.h>
  34#include <asm/mach-types.h>
  35
  36DECLARE_GLOBAL_DATA_PTR;
  37
  38void wait_for_command_complete(unsigned int wd_base);
  39
  40/*******************************************************
  41 * Routine: delay
  42 * Description: spinning delay to use before udelay works
  43 ******************************************************/
  44static inline void delay (unsigned long loops)
  45{
  46        __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
  47                "bne 1b":"=r" (loops):"0" (loops));
  48}
  49
  50/*****************************************
  51 * Routine: board_init
  52 * Description: Early hardware init.
  53 *****************************************/
  54int board_init (void)
  55{
  56        gpmc_init(); /* in SRAM or SDRM, finish GPMC */
  57
  58        gd->bd->bi_arch_number = MACH_TYPE_OMAP_H4;             /* board id for linux */
  59        gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0+0x100);     /* adress of boot parameters */
  60
  61        return 0;
  62}
  63
  64/**********************************************************
  65 * Routine: try_unlock_sram()
  66 * Description: If chip is GP type, unlock the SRAM for
  67 *  general use.
  68 ***********************************************************/
  69void try_unlock_sram(void)
  70{
  71        /* if GP device unlock device SRAM for general use */
  72        if (get_device_type() == GP_DEVICE) {
  73                __raw_writel(0xFF, A_REQINFOPERM0);
  74                __raw_writel(0xCFDE, A_READPERM0);
  75                __raw_writel(0xCFDE, A_WRITEPERM0);
  76        }
  77}
  78
  79/**********************************************************
  80 * Routine: s_init
  81 * Description: Does early system init of muxing and clocks.
  82 * - Called path is with sram stack.
  83 **********************************************************/
  84void s_init(void)
  85{
  86        int in_sdram = running_in_sdram();
  87
  88        watchdog_init();
  89        set_muxconf_regs();
  90        delay(100);
  91        try_unlock_sram();
  92
  93        if(!in_sdram)
  94                prcm_init();
  95
  96        peripheral_enable();
  97        icache_enable();
  98        if (!in_sdram)
  99                sdrc_init();
 100}
 101
 102/*******************************************************
 103 * Routine: misc_init_r
 104 * Description: Init ethernet (done here so udelay works)
 105 ********************************************************/
 106int misc_init_r (void)
 107{
 108        ether_init(); /* better done here so timers are init'ed */
 109        return(0);
 110}
 111
 112/****************************************
 113 * Routine: watchdog_init
 114 * Description: Shut down watch dogs
 115 *****************************************/
 116void watchdog_init(void)
 117{
 118        /* There are 4 watch dogs.  1 secure, and 3 general purpose.
 119        * The ROM takes care of the secure one. Of the 3 GP ones,
 120        * 1 can reset us directly, the other 2 only generate MPU interrupts.
 121        */
 122        __raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR);
 123        wait_for_command_complete(WD2_BASE);
 124        __raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR);
 125
 126#if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite*/
 127        __raw_writel(WD_UNLOCK1 ,WD3_BASE+WSPR);
 128        wait_for_command_complete(WD3_BASE);
 129        __raw_writel(WD_UNLOCK2 ,WD3_BASE+WSPR);
 130
 131        __raw_writel(WD_UNLOCK1 ,WD4_BASE+WSPR);
 132        wait_for_command_complete(WD4_BASE);
 133        __raw_writel(WD_UNLOCK2 ,WD4_BASE+WSPR);
 134#endif
 135}
 136
 137/******************************************************
 138 * Routine: wait_for_command_complete
 139 * Description: Wait for posting to finish on watchdog
 140 ******************************************************/
 141void wait_for_command_complete(unsigned int wd_base)
 142{
 143        int pending = 1;
 144        do {
 145                pending = __raw_readl(wd_base+WWPS);
 146        } while (pending);
 147}
 148
 149/*******************************************************************
 150 * Routine:ether_init
 151 * Description: take the Ethernet controller out of reset and wait
 152 *                 for the EEPROM load to complete.
 153 ******************************************************************/
 154void ether_init (void)
 155{
 156#ifdef CONFIG_DRIVER_LAN91C96
 157        int cnt = 20;
 158
 159        __raw_writeb(0x3,OMAP2420_CTRL_BASE+0x10a); /*protect->gpio95 */
 160
 161        __raw_writew(0x0, LAN_RESET_REGISTER);
 162        do {
 163                __raw_writew(0x1, LAN_RESET_REGISTER);
 164                udelay (100);
 165                if (cnt == 0)
 166                        goto h4reset_err_out;
 167                --cnt;
 168        } while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
 169
 170        cnt = 20;
 171
 172        do {
 173                __raw_writew(0x0, LAN_RESET_REGISTER);
 174                udelay (100);
 175                if (cnt == 0)
 176                        goto h4reset_err_out;
 177                --cnt;
 178        } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
 179        udelay (1000);
 180
 181        *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
 182        udelay (1000);
 183
 184        h4reset_err_out:
 185        return;
 186#endif
 187}
 188
 189/**********************************************
 190 * Routine: dram_init
 191 * Description: sets uboots idea of sdram size
 192 **********************************************/
 193int dram_init (void)
 194{
 195        unsigned int size0=0,size1=0;
 196        u32 mtype, btype, rev, cpu;
 197        u8 chg_on = 0x5; /* enable charge of back up battery */
 198        u8 vmode_on = 0x8C;
 199        #define NOT_EARLY 0
 200
 201        i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); /* need this a bit early */
 202
 203        btype = get_board_type();
 204        mtype = get_mem_type();
 205        rev = get_cpu_rev();
 206        cpu = get_cpu_type();
 207
 208        display_board_info(btype);
 209        if (btype == BOARD_H4_MENELAUS){
 210                update_mux(btype,mtype); /* combo part on menelaus */
 211                i2c_write(I2C_MENELAUS, 0x20, 1, &chg_on, 1); /*fix POR reset bug */
 212                i2c_write(I2C_MENELAUS, 0x2, 1, &vmode_on, 1); /* VCORE change on VMODE */
 213        }
 214
 215        if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
 216                do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); /* init other chip select */
 217        }
 218        size0 = get_sdr_cs_size(SDRC_CS0_OSET);
 219        size1 = get_sdr_cs_size(SDRC_CS1_OSET);
 220
 221        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 222        gd->bd->bi_dram[0].size = size0;
 223        if(rev == CPU_2420_2422_ES1) /* ES1's 128MB remap granularity isn't worth doing */
 224                gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 225        else /* ES2 and above can remap at 32MB granularity */
 226                gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0;
 227        gd->bd->bi_dram[1].size = size1;
 228
 229        return 0;
 230}
 231
 232/**********************************************************
 233 * Routine: set_muxconf_regs
 234 * Description: Setting up the configuration Mux registers
 235 *              specific to the hardware
 236 *********************************************************/
 237void set_muxconf_regs (void)
 238{
 239        muxSetupSDRC();
 240        muxSetupGPMC();
 241        muxSetupUsb0();
 242        muxSetupUart3();
 243        muxSetupI2C1();
 244        muxSetupUART1();
 245        muxSetupLCD();
 246        muxSetupCamera();
 247        muxSetupMMCSD();
 248        muxSetupTouchScreen();
 249        muxSetupHDQ();
 250}
 251
 252/*****************************************************************
 253 * Routine: peripheral_enable
 254 * Description: Enable the clks & power for perifs (GPT2, UART1,...)
 255 ******************************************************************/
 256void peripheral_enable(void)
 257{
 258        unsigned int v, if_clks=0, func_clks=0;
 259
 260        /* Enable GP2 timer.*/
 261        if_clks |= BIT4;
 262        func_clks |= BIT4;
 263        v = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* Sys_clk input OMAP2420_GPT2 */
 264        __raw_writel(v, CM_CLKSEL2_CORE);
 265        __raw_writel(0x1, CM_CLKSEL_WKUP);
 266
 267#ifdef CONFIG_SYS_NS16550
 268        /* Enable UART1 clock */
 269        func_clks |= BIT21;
 270        if_clks |= BIT21;
 271#endif
 272        v = __raw_readl(CM_ICLKEN1_CORE) | if_clks;     /* Interface clocks on */
 273        __raw_writel(v,CM_ICLKEN1_CORE );
 274        v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */
 275        __raw_writel(v, CM_FCLKEN1_CORE);
 276        delay(1000);
 277
 278#ifndef KERNEL_UPDATED
 279        {
 280#define V1 0xffffffff
 281#define V2 0x00000007
 282
 283                __raw_writel(V1, CM_FCLKEN1_CORE);
 284                __raw_writel(V2, CM_FCLKEN2_CORE);
 285                __raw_writel(V1, CM_ICLKEN1_CORE);
 286                __raw_writel(V1, CM_ICLKEN2_CORE);
 287        }
 288#endif
 289}
 290
 291/****************************************
 292 * Routine: muxSetupUsb0   (ostboot)
 293 * Description: Setup usb muxing
 294 *****************************************/
 295void muxSetupUsb0(void)
 296{
 297        volatile uint8   *MuxConfigReg;
 298        volatile uint32  *otgCtrlReg;
 299
 300        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_PUEN;
 301        *MuxConfigReg &= (uint8)(~0x1F);
 302
 303        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VP;
 304        *MuxConfigReg &= (uint8)(~0x1F);
 305
 306        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VM;
 307        *MuxConfigReg &= (uint8)(~0x1F);
 308
 309        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_RCV;
 310        *MuxConfigReg &= (uint8)(~0x1F);
 311
 312        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_TXEN;
 313        *MuxConfigReg &= (uint8)(~0x1F);
 314
 315        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_SE0;
 316        *MuxConfigReg &= (uint8)(~0x1F);
 317
 318        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_DAT;
 319        *MuxConfigReg &= (uint8)(~0x1F);
 320
 321        /* setup for USB VBus detection */
 322        otgCtrlReg = (volatile uint32 *)USB_OTG_CTRL;
 323        *otgCtrlReg |= 0x00040000; /* bit 18 */
 324}
 325
 326/****************************************
 327 * Routine: muxSetupUart3   (ostboot)
 328 * Description: Setup uart3 muxing
 329 *****************************************/
 330void muxSetupUart3(void)
 331{
 332        volatile uint8 *MuxConfigReg;
 333
 334        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_TX_IRTX;
 335        *MuxConfigReg &= (uint8)(~0x1F);
 336
 337        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_RX_IRRX;
 338        *MuxConfigReg &= (uint8)(~0x1F);
 339}
 340
 341/****************************************
 342 * Routine: muxSetupI2C1   (ostboot)
 343 * Description: Setup i2c muxing
 344 *****************************************/
 345void muxSetupI2C1(void)
 346{
 347        volatile unsigned char  *MuxConfigReg;
 348
 349        /* I2C1 Clock pin configuration, PIN = M19 */
 350        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SCL;
 351        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 352
 353        /* I2C1 Data pin configuration, PIN = L15 */
 354        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SDA;
 355        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 356
 357        /* Pull-up required on data line */
 358        /* external pull-up already present. */
 359        /* *MuxConfigReg |= 0x18 ;*/ /* Mode = 0, PullTypeSel=PU, PullUDEnable=Enabled */
 360}
 361
 362/****************************************
 363 * Routine: muxSetupUART1  (ostboot)
 364 * Description: Set up uart1 muxing
 365 *****************************************/
 366void muxSetupUART1(void)
 367{
 368        volatile unsigned char  *MuxConfigReg;
 369
 370        /* UART1_CTS pin configuration, PIN = D21 */
 371        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS;
 372        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 373
 374        /* UART1_RTS pin configuration, PIN = H21 */
 375        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS;
 376        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 377
 378        /* UART1_TX pin configuration, PIN = L20 */
 379        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX;
 380        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 381
 382        /* UART1_RX pin configuration, PIN = T21 */
 383        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX;
 384        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 385}
 386
 387/****************************************
 388 * Routine: muxSetupLCD   (ostboot)
 389 * Description: Setup lcd muxing
 390 *****************************************/
 391void muxSetupLCD(void)
 392{
 393        volatile unsigned char  *MuxConfigReg;
 394
 395        /* LCD_D0 pin configuration, PIN = Y7  */
 396        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D0;
 397        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 398
 399        /* LCD_D1 pin configuration, PIN = P10 */
 400        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D1;
 401        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 402
 403        /* LCD_D2 pin configuration, PIN = V8  */
 404        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D2;
 405        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 406
 407        /* LCD_D3 pin configuration, PIN = Y8  */
 408        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D3;
 409        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 410
 411        /* LCD_D4 pin configuration, PIN = W8  */
 412        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D4;
 413        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 414
 415        /* LCD_D5 pin configuration, PIN = R10 */
 416        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D5;
 417        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 418
 419        /* LCD_D6 pin configuration, PIN = Y9  */
 420        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D6;
 421        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 422
 423        /* LCD_D7 pin configuration, PIN = V9  */
 424        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D7;
 425        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 426
 427        /* LCD_D8 pin configuration, PIN = W9  */
 428        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D8;
 429        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 430
 431        /* LCD_D9 pin configuration, PIN = P11 */
 432        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D9;
 433        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 434
 435        /* LCD_D10 pin configuration, PIN = V10 */
 436        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D10;
 437        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 438
 439        /* LCD_D11 pin configuration, PIN = Y10 */
 440        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D11;
 441        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 442
 443        /* LCD_D12 pin configuration, PIN = W10 */
 444        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D12;
 445        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 446
 447        /* LCD_D13 pin configuration, PIN = R11 */
 448        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D13;
 449        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 450
 451        /* LCD_D14 pin configuration, PIN = V11 */
 452        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D14;
 453        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 454
 455        /* LCD_D15 pin configuration, PIN = W11 */
 456        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D15;
 457        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 458
 459        /* LCD_D16 pin configuration, PIN = P12 */
 460        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D16;
 461        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 462
 463        /* LCD_D17 pin configuration, PIN = R12 */
 464        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D17;
 465        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 466
 467        /* LCD_PCLK pin configuration,   PIN = W6   */
 468        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_PCLK;
 469        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 470
 471        /* LCD_VSYNC pin configuration,  PIN = V7  */
 472        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_VSYNC;
 473        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 474
 475        /* LCD_HSYNC pin configuration,  PIN = Y6  */
 476        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_HSYNC;
 477        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 478
 479        /* LCD_ACBIAS pin configuration, PIN = W7 */
 480        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_ACBIAS;
 481        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 482}
 483
 484/****************************************
 485 * Routine: muxSetupCamera  (ostboot)
 486 * Description: Setup camera muxing
 487 *****************************************/
 488void muxSetupCamera(void)
 489{
 490        volatile unsigned char  *MuxConfigReg;
 491
 492        /* CAMERA_RSTZ  pin configuration, PIN = Y16 */
 493        /* CAM_RST is connected through the I2C IO expander.*/
 494        /* MuxConfigReg = (volatile unsigned char *), CONTROL_PADCONF_SYS_NRESWARM*/
 495        /* *MuxConfigReg = 0x00 ; / * Mode = 0, PUPD=Disabled   */
 496
 497        /* CAMERA_XCLK  pin configuration, PIN = U3 */
 498        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_XCLK;
 499        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 500
 501        /* CAMERA_LCLK  pin configuration, PIN = V5 */
 502        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_LCLK;
 503        *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 504
 505        /* CAMERA_VSYNC pin configuration, PIN = U2 */
 506        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_VS,
 507                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 508
 509        /* CAMERA_HSYNC pin configuration, PIN = T3 */
 510        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_HS,
 511                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 512
 513        /* CAMERA_DAT0 pin configuration, PIN = T4 */
 514        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D0,
 515                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 516
 517        /* CAMERA_DAT1 pin configuration, PIN = V2 */
 518        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D1,
 519                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 520
 521        /* CAMERA_DAT2 pin configuration, PIN = V3 */
 522        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D2,
 523                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 524
 525        /* CAMERA_DAT3 pin configuration, PIN = U4 */
 526        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D3,
 527                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 528
 529        /* CAMERA_DAT4 pin configuration, PIN = W2 */
 530        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D4,
 531                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 532
 533        /* CAMERA_DAT5 pin configuration, PIN = V4 */
 534        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D5,
 535                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 536
 537        /* CAMERA_DAT6 pin configuration, PIN = W3 */
 538        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D6,
 539                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 540
 541        /* CAMERA_DAT7 pin configuration, PIN = Y2 */
 542        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D7,
 543                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 544
 545        /* CAMERA_DAT8 pin configuration, PIN = Y4 */
 546        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D8,
 547                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 548
 549        /* CAMERA_DAT9 pin configuration, PIN = V6 */
 550        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D9,
 551                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 552}
 553
 554/****************************************
 555 * Routine: muxSetupMMCSD (ostboot)
 556 * Description: set up MMC muxing
 557 *****************************************/
 558void muxSetupMMCSD(void)
 559{
 560        volatile unsigned char  *MuxConfigReg;
 561
 562        /* SDMMC_CLKI pin configuration,  PIN = H15 */
 563        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKI,
 564                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 565
 566        /* SDMMC_CLKO pin configuration,  PIN = G19 */
 567        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKO,
 568                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 569
 570        /* SDMMC_CMD pin configuration,   PIN = H18 */
 571        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD,
 572                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 573        /* External pull-ups are present. */
 574        /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
 575
 576        /* SDMMC_DAT0 pin configuration,  PIN = F20 */
 577        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT0,
 578                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 579        /* External pull-ups are present. */
 580        /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
 581
 582        /* SDMMC_DAT1 pin configuration,  PIN = H14 */
 583        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT1,
 584                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 585        /* External pull-ups are present. */
 586        /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
 587
 588        /* SDMMC_DAT2 pin configuration,  PIN = E19 */
 589        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT2,
 590                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 591        /* External pull-ups are present. */
 592        /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
 593
 594        /* SDMMC_DAT3 pin configuration,  PIN = D19 */
 595        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT3,
 596                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 597        /* External pull-ups are present. */
 598        /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
 599
 600        /* SDMMC_DDIR0 pin configuration, PIN = F19 */
 601        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR0,
 602                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 603
 604        /* SDMMC_DDIR1 pin configuration, PIN = E20 */
 605        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR1,
 606                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 607
 608        /* SDMMC_DDIR2 pin configuration, PIN = F18 */
 609        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR2,
 610                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 611
 612        /* SDMMC_DDIR3 pin configuration, PIN = E18 */
 613        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR3,
 614                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 615
 616        /* SDMMC_CDIR pin configuration,  PIN = G18 */
 617        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD_DIR,
 618                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 619
 620        /* MMC_CD pin configuration,      PIN = B3  ---2420IP ONLY---*/
 621        /* MMC_CD for 2422IP=K1 */
 622        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A14,
 623                                   *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
 624
 625        /* MMC_WP pin configuration,      PIN = B4  */
 626        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A13,
 627                                   *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
 628}
 629
 630/******************************************
 631 * Routine: muxSetupTouchScreen (ostboot)
 632 * Description:  Set up touch screen muxing
 633 *******************************************/
 634void muxSetupTouchScreen(void)
 635{
 636        volatile unsigned char  *MuxConfigReg;
 637
 638        /* SPI1_CLK pin configuration,  PIN = U18 */
 639        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_CLK,
 640                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 641
 642        /* SPI1_MOSI pin configuration, PIN = V20 */
 643        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SIMO,
 644                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 645
 646        /* SPI1_MISO pin configuration, PIN = T18 */
 647        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SOMI,
 648                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 649
 650        /* SPI1_nCS0 pin configuration, PIN = U19 */
 651        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_NCS0,
 652                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 653
 654        /* PEN_IRQ pin configuration,   PIN = P20 */
 655        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MCBSP1_FSR,
 656                                   *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
 657}
 658
 659/****************************************
 660 * Routine: muxSetupHDQ (ostboot)
 661 * Description: setup 1wire mux
 662 *****************************************/
 663void muxSetupHDQ(void)
 664{
 665        volatile unsigned char  *MuxConfigReg;
 666
 667        /* HDQ_SIO pin configuration,  PIN = N18 */
 668        MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_HDQ_SIO,
 669                                   *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 670}
 671
 672/***************************************************************
 673 * Routine: muxSetupGPMC (ostboot)
 674 * Description: Configures balls which cam up in protected mode
 675 ***************************************************************/
 676void muxSetupGPMC(void)
 677{
 678        volatile uint8 *MuxConfigReg;
 679        volatile unsigned int *MCR = (volatile unsigned int *)0x4800008C;
 680
 681        /* gpmc_io_dir */
 682        *MCR = 0x19000000;
 683
 684        /* NOR FLASH CS0 */
 685        /* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode - 0; Byte-3       Pull/up - N/A */
 686        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_D2_BYTE3,
 687                                   *MuxConfigReg = 0x00 ;
 688
 689        /* signal - Gpmc_iodir; pin - n2; offset - 0x008C; mode - 1; Byte-3     Pull/up - N/A */
 690        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE3,
 691                                   *MuxConfigReg = 0x01 ;
 692
 693        /* MPDB(Multi Port Debug Port) CS1 */
 694        /* signal - gpmc_ncs1; pin - N8; offset - 0x008C; mode - 0; Byte-1      Pull/up - N/A */
 695        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE1,
 696                                   *MuxConfigReg = 0x00 ;
 697
 698        /* signal - Gpmc_ncs2; pin - E2; offset - 0x008C; mode - 0; Byte-2      Pull/up - N/A */
 699        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE2,
 700                                   *MuxConfigReg = 0x00 ;
 701}
 702
 703/****************************************************************
 704 * Routine: muxSetupSDRC  (ostboot)
 705 * Description: Configures balls which come up in protected mode
 706 ****************************************************************/
 707void muxSetupSDRC(void)
 708{
 709        volatile uint8 *MuxConfigReg;
 710
 711        /* signal - sdrc_ncs1; pin - C12; offset - 0x00A0; mode - 0; Byte-1     Pull/up - N/A */
 712        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE1,
 713                                   *MuxConfigReg = 0x00 ;
 714
 715        /* signal - sdrc_a12; pin - D11; offset - 0x0030; mode - 0; Byte-2      Pull/up - N/A */
 716        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE2,
 717                                   *MuxConfigReg = 0x00 ;
 718
 719        /* signal - sdrc_cke1; pin - B13; offset - 0x00A0; mode - 0; Byte-3     Pull/up - N/A */
 720        MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE3,
 721                                   *MuxConfigReg = 0x00;
 722
 723        if (get_cpu_type() == CPU_2422) {
 724                MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE0,
 725                                           *MuxConfigReg = 0x1b;
 726        }
 727}
 728
 729/*****************************************************************************
 730 * Routine: update_mux()
 731 * Description: Update balls which are different beween boards.  All should be
 732 *              updated to match functionaly.  However, I'm only updating ones
 733 *              which I'll be using for now.  When power comes into play they
 734 *              all need updating.
 735 *****************************************************************************/
 736void update_mux(u32 btype,u32 mtype)
 737{
 738        u32 cpu, base = OMAP2420_CTRL_BASE;
 739        cpu = get_cpu_type();
 740
 741        if (btype == BOARD_H4_MENELAUS) {
 742                if (cpu == CPU_2420) {
 743                        /* PIN = B3,  GPIO.0->KBR5,      mode 3,  (pun?),-DO-*/
 744                        __raw_writeb(0x3, base+0x30);
 745                        /* PIN = B13, GPIO.38->KBC6,     mode 3,  (pun?)-DO-*/
 746                        __raw_writeb(0x3, base+0xa3);
 747                        /* PIN = F1, GPIO.25->HSUSBxx    mode 3,  (for external HS USB)*/
 748                        /* PIN = H1, GPIO.26->HSUSBxx    mode 3,  (for external HS USB)*/
 749                        /* PIN = K1, GPMC_ncs6           mode 0,  (on board nand access)*/
 750                        /* PIN = L2, GPMC_ncs67          mode 0,  (for external HS USB)*/
 751                        /* PIN = M1 (HSUSBOTG) */
 752                        /* PIN = P1, GPIO.35->MEN_POK    mode 3,  (menelaus powerok)-DO-*/
 753                        __raw_writeb(0x3, base+0x9d);
 754                        /* PIN = U32, (WLAN_CLKREQ) */
 755                        /* PIN = Y11, WLAN */
 756                        /* PIN = AA4, GPIO.15->KBC2,     mode 3,  -DO- */
 757                        __raw_writeb(0x3, base+0xe7);
 758                        /* PIN = AA8, mDOC */
 759                        /* PIN = AA10, BT */
 760                        /* PIN = AA13, WLAN */
 761                        /* PIN = M18 GPIO.96->MMC2_WP    mode 3   -DO- */
 762                        __raw_writeb(0x3, base+0x10e);
 763                        /* PIN = N19 GPIO.98->WLAN_INT   mode 3   -DO- */
 764                        __raw_writeb(0x3, base+0x110);
 765                        /* PIN = J15 HHUSB */
 766                        /* PIN = H19 HSUSB */
 767                        /* PIN = W13, P13, R13, W16 ... */
 768                        /* PIN = V12 GPIO.25->I2C_CAMEN  mode 3   -DO- */
 769                        __raw_writeb(0x3, base+0xde);
 770                        /* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */
 771                        __raw_writeb(0x0, base+0x12c);
 772                        /* PIN = AA17->sys_clkreq        mode 0   -DO- */
 773                        __raw_writeb(0x0, base+0x136);
 774                } else if (cpu == CPU_2422) {
 775                        /* PIN = B3,  GPIO.0->nc,        mode 3,  set above (pun?)*/
 776                        /* PIN = B13, GPIO.cke1->nc,     mode 0,  set above, (pun?)*/
 777                        /* PIN = F1, GPIO.25->HSUSBxx    mode 3,  (for external HS USB)*/
 778                        /* PIN = H1, GPIO.26->HSUSBxx    mode 3,  (for external HS USB)*/
 779                        /* PIN = K1, GPMC_ncs6           mode 0,  (on board nand access)*/
 780                        __raw_writeb(0x0, base+0x92);
 781                        /* PIN = L2, GPMC_ncs67          mode 0,  (for external HS USB)*/
 782                        /* PIN = M1 (HSUSBOTG) */
 783                        /* PIN = P1, GPIO.35->MEN_POK    mode 3,  (menelaus powerok)-DO-*/
 784                        __raw_writeb(0x3, base+0x10c);
 785                        /* PIN = U32, (WLAN_CLKREQ) */
 786                        /* PIN = AA4, GPIO.15->KBC2,     mode 3,  -DO- */
 787                        __raw_writeb(0x3, base+0x30);
 788                        /* PIN = AA8, mDOC */
 789                        /* PIN = AA10, BT */
 790                        /* PIN = AA12, WLAN */
 791                        /* PIN = M18 GPIO.96->MMC2_WP    mode 3   -DO- */
 792                        __raw_writeb(0x3, base+0x10e);
 793                        /* PIN = N19 GPIO.98->WLAN_INT   mode 3   -DO- */
 794                        __raw_writeb(0x3, base+0x110);
 795                        /* PIN = J15 HHUSB */
 796                        /* PIN = H19 HSUSB */
 797                        /* PIN = W13, P13, R13, W16 ... */
 798                        /* PIN = V12 GPIO.25->I2C_CAMEN  mode 3   -DO- */
 799                        __raw_writeb(0x3, base+0xde);
 800                        /* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */
 801                        __raw_writeb(0x0, base+0x12c);
 802                        /* PIN = AA17->sys_clkreq        mode 0   -DO- */
 803                        __raw_writeb(0x0, base+0x136);
 804                }
 805
 806        } else if (btype == BOARD_H4_SDP) {
 807                if (cpu == CPU_2420) {
 808                        /* PIN = B3,  GPIO.0->nc         mode 3,  set above (pun?)*/
 809                        /* PIN = B13, GPIO.cke1->nc,     mode 0,  set above, (pun?)*/
 810                        /* Pin = Y11 VLNQ */
 811                        /* Pin = AA4 VLNQ */
 812                        /* Pin = AA6 VLNQ */
 813                        /* Pin = AA8 VLNQ */
 814                        /* Pin = AA10 VLNQ */
 815                        /* Pin = AA12 VLNQ */
 816                        /* PIN = M18 GPIO.96->KBR5       mode 3   -DO- */
 817                        __raw_writeb(0x3, base+0x10e);
 818                        /* PIN = N19 GPIO.98->KBC6       mode 3   -DO- */
 819                        __raw_writeb(0x3, base+0x110);
 820                        /* PIN = J15 MDOC_nDMAREQ */
 821                        /* PIN = H19 GPIO.100->KBC2      mode 3   -DO- */
 822                        __raw_writeb(0x3, base+0x114);
 823                        /* PIN = W13, V12, P13, R13, W19, W16 ... */
 824                        /* PIN = AA17 sys_clkreq->bt_clk_req  mode 0  */
 825                } else if (cpu == CPU_2422) {
 826                        /* PIN = B3,  GPIO.0->MMC_CD,    mode 3,  set above */
 827                        /* PIN = B13, GPIO.38->wlan_int, mode 3,  (pun?)*/
 828                        /* Pin = Y11 VLNQ */
 829                        /* Pin = AA4 VLNQ */
 830                        /* Pin = AA6 VLNQ */
 831                        /* Pin = AA8 VLNQ */
 832                        /* Pin = AA10 VLNQ */
 833                        /* Pin = AA12 VLNQ */
 834                        /* PIN = M18 GPIO.96->KBR5       mode 3   -DO- */
 835                        __raw_writeb(0x3, base+0x10e);
 836                        /* PIN = N19 GPIO.98->KBC6       mode 3   -DO- */
 837                        __raw_writeb(0x3, base+0x110);
 838                        /* PIN = J15 MDOC_nDMAREQ */
 839                        /* PIN = H19 GPIO.100->KBC2      mode 3   -DO- */
 840                        __raw_writeb(0x3, base+0x114);
 841                        /* PIN = W13, V12, P13, R13, W19, W16 ... */
 842                        /* PIN = AA17 sys_clkreq->bt_clk_req  mode 0 */
 843                }
 844        }
 845}
 846
 847#ifdef CONFIG_CMD_NET
 848int board_eth_init(bd_t *bis)
 849{
 850        int rc = 0;
 851#ifdef CONFIG_LAN91C96
 852        rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
 853#endif
 854        return rc;
 855}
 856#endif
 857