uboot/board/tqc/tqm5200/tqm5200.c
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   1/*
   2 * (C) Copyright 2003-2006
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * (C) Copyright 2004
   6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
   7 *
   8 * (C) Copyright 2004-2006
   9 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
  10 *
  11 * See file CREDITS for list of people who contributed to this
  12 * project.
  13 *
  14 * This program is free software; you can redistribute it and/or
  15 * modify it under the terms of the GNU General Public License as
  16 * published by the Free Software Foundation; either version 2 of
  17 * the License, or (at your option) any later version.
  18 *
  19 * This program is distributed in the hope that it will be useful,
  20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22 * GNU General Public License for more details.
  23 *
  24 * You should have received a copy of the GNU General Public License
  25 * along with this program; if not, write to the Free Software
  26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27 * MA 02111-1307 USA
  28 */
  29
  30#include <common.h>
  31#include <mpc5xxx.h>
  32#include <pci.h>
  33#include <asm/processor.h>
  34#include <libfdt.h>
  35#include <netdev.h>
  36
  37#ifdef CONFIG_VIDEO_SM501
  38#include <sm501.h>
  39#endif
  40
  41#if defined(CONFIG_MPC5200_DDR)
  42#include "mt46v16m16-75.h"
  43#else
  44#include "mt48lc16m16a2-75.h"
  45#endif
  46
  47#ifdef CONFIG_OF_LIBFDT
  48#include <fdt_support.h>
  49#endif /* CONFIG_OF_LIBFDT */
  50
  51DECLARE_GLOBAL_DATA_PTR;
  52
  53#ifdef CONFIG_PS2MULT
  54void ps2mult_early_init(void);
  55#endif
  56
  57#ifndef CONFIG_SYS_RAMBOOT
  58static void sdram_start (int hi_addr)
  59{
  60        long hi_addr_bit = hi_addr ? 0x01000000 : 0;
  61
  62        /* unlock mode register */
  63        *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
  64                hi_addr_bit;
  65        __asm__ volatile ("sync");
  66
  67        /* precharge all banks */
  68        *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
  69                hi_addr_bit;
  70        __asm__ volatile ("sync");
  71
  72#if SDRAM_DDR
  73        /* set mode register: extended mode */
  74        *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
  75        __asm__ volatile ("sync");
  76
  77        /* set mode register: reset DLL */
  78        *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
  79        __asm__ volatile ("sync");
  80#endif
  81
  82        /* precharge all banks */
  83        *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
  84                hi_addr_bit;
  85        __asm__ volatile ("sync");
  86
  87        /* auto refresh */
  88        *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
  89                hi_addr_bit;
  90        __asm__ volatile ("sync");
  91
  92        /* set mode register */
  93        *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
  94        __asm__ volatile ("sync");
  95
  96        /* normal operation */
  97        *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
  98        __asm__ volatile ("sync");
  99}
 100#endif
 101
 102/*
 103 * ATTENTION: Although partially referenced initdram does NOT make real use
 104 *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
 105 *            is something else than 0x00000000.
 106 */
 107
 108phys_size_t initdram (int board_type)
 109{
 110        ulong dramsize = 0;
 111        ulong dramsize2 = 0;
 112        uint svr, pvr;
 113
 114#ifndef CONFIG_SYS_RAMBOOT
 115        ulong test1, test2;
 116
 117        /* setup SDRAM chip selects */
 118        *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
 119        *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
 120        __asm__ volatile ("sync");
 121
 122        /* setup config registers */
 123        *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
 124        *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
 125        __asm__ volatile ("sync");
 126
 127#if SDRAM_DDR
 128        /* set tap delay */
 129        *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
 130        __asm__ volatile ("sync");
 131#endif
 132
 133        /* find RAM size using SDRAM CS0 only */
 134        sdram_start(0);
 135        test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
 136        sdram_start(1);
 137        test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
 138        if (test1 > test2) {
 139                sdram_start(0);
 140                dramsize = test1;
 141        } else {
 142                dramsize = test2;
 143        }
 144
 145        /* memory smaller than 1MB is impossible */
 146        if (dramsize < (1 << 20)) {
 147                dramsize = 0;
 148        }
 149
 150        /* set SDRAM CS0 size according to the amount of RAM found */
 151        if (dramsize > 0) {
 152                *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
 153                        __builtin_ffs(dramsize >> 20) - 1;
 154        } else {
 155                *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
 156        }
 157
 158        /* let SDRAM CS1 start right after CS0 */
 159        *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c; /* 512MB */
 160
 161        /* find RAM size using SDRAM CS1 only */
 162        if (!dramsize)
 163                sdram_start(0);
 164        test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
 165        if (!dramsize) {
 166                sdram_start(1);
 167                test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
 168        }
 169        if (test1 > test2) {
 170                sdram_start(0);
 171                dramsize2 = test1;
 172        } else {
 173                dramsize2 = test2;
 174        }
 175
 176        /* memory smaller than 1MB is impossible */
 177        if (dramsize2 < (1 << 20)) {
 178                dramsize2 = 0;
 179        }
 180
 181        /* set SDRAM CS1 size according to the amount of RAM found */
 182        if (dramsize2 > 0) {
 183                *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
 184                        | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
 185        } else {
 186                *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 187        }
 188
 189#else /* CONFIG_SYS_RAMBOOT */
 190
 191        /* retrieve size of memory connected to SDRAM CS0 */
 192        dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
 193        if (dramsize >= 0x13) {
 194                dramsize = (1 << (dramsize - 0x13)) << 20;
 195        } else {
 196                dramsize = 0;
 197        }
 198
 199        /* retrieve size of memory connected to SDRAM CS1 */
 200        dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
 201        if (dramsize2 >= 0x13) {
 202                dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
 203        } else {
 204                dramsize2 = 0;
 205        }
 206#endif /* CONFIG_SYS_RAMBOOT */
 207
 208        /*
 209         * On MPC5200B we need to set the special configuration delay in the
 210         * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
 211         * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
 212         *
 213         * "The SDelay should be written to a value of 0x00000004. It is
 214         * required to account for changes caused by normal wafer processing
 215         * parameters."
 216         */
 217        svr = get_svr();
 218        pvr = get_pvr();
 219        if ((SVR_MJREV(svr) >= 2) &&
 220            (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
 221
 222                *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
 223                __asm__ volatile ("sync");
 224        }
 225
 226#if defined(CONFIG_TQM5200_B)
 227        return dramsize + dramsize2;
 228#else
 229        return dramsize;
 230#endif /* CONFIG_TQM5200_B */
 231}
 232
 233int checkboard (void)
 234{
 235#if defined(CONFIG_AEVFIFO)
 236        puts ("Board: AEVFIFO\n");
 237        return 0;
 238#endif
 239
 240#if defined(CONFIG_TQM5200S)
 241# define MODULE_NAME    "TQM5200S"
 242#else
 243# define MODULE_NAME    "TQM5200"
 244#endif
 245
 246#if defined(CONFIG_STK52XX)
 247# define CARRIER_NAME   "STK52xx"
 248#elif defined(CONFIG_TB5200)
 249# define CARRIER_NAME   "TB5200"
 250#elif defined(CONFIG_CAM5200)
 251# define CARRIER_NAME   "CAM5200"
 252#elif defined(CONFIG_FO300)
 253# define CARRIER_NAME   "FO300"
 254#else
 255# error "UNKNOWN"
 256#endif
 257
 258        puts (  "Board: " MODULE_NAME " (TQ-Components GmbH)\n"
 259                "       on a " CARRIER_NAME " carrier board\n");
 260
 261        return 0;
 262}
 263
 264#undef MODULE_NAME
 265#undef CARRIER_NAME
 266
 267void flash_preinit(void)
 268{
 269        /*
 270         * Now, when we are in RAM, enable flash write
 271         * access for detection process.
 272         * Note that CS_BOOT cannot be cleared when
 273         * executing in flash.
 274         */
 275        *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 276}
 277
 278
 279#ifdef  CONFIG_PCI
 280static struct pci_controller hose;
 281
 282extern void pci_mpc5xxx_init(struct pci_controller *);
 283
 284void pci_init_board(void)
 285{
 286        pci_mpc5xxx_init(&hose);
 287}
 288#endif
 289
 290#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
 291
 292#if defined (CONFIG_MINIFAP)
 293#define SM501_POWER_MODE0_GATE          0x00000040UL
 294#define SM501_POWER_MODE1_GATE          0x00000048UL
 295#define POWER_MODE_GATE_GPIO_PWM_I2C    0x00000040UL
 296#define SM501_GPIO_DATA_DIR_HIGH        0x0001000CUL
 297#define SM501_GPIO_DATA_HIGH            0x00010004UL
 298#define SM501_GPIO_51                   0x00080000UL
 299#endif /* CONFIG MINIFAP */
 300
 301void init_ide_reset (void)
 302{
 303        debug ("init_ide_reset\n");
 304
 305#if defined (CONFIG_MINIFAP)
 306        /* Configure GPIO_51 of the SM501 grafic controller as ATA reset */
 307
 308        /* enable GPIO control (in both power modes) */
 309        *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
 310                POWER_MODE_GATE_GPIO_PWM_I2C;
 311        *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
 312                POWER_MODE_GATE_GPIO_PWM_I2C;
 313        /* configure GPIO51 as output */
 314        *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |=
 315                SM501_GPIO_51;
 316#else
 317        /* Configure PSC1_4 as GPIO output for ATA reset */
 318        *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
 319        *(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
 320
 321        /* by default the ATA reset is de-asserted */
 322        *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
 323#endif
 324}
 325
 326void ide_set_reset (int idereset)
 327{
 328        debug ("ide_reset(%d)\n", idereset);
 329
 330#if defined (CONFIG_MINIFAP)
 331        if (idereset) {
 332                *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
 333                        ~SM501_GPIO_51;
 334        } else {
 335                *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
 336                        SM501_GPIO_51;
 337        }
 338#else
 339        if (idereset) {
 340                *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
 341        } else {
 342                *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |=  GPIO_PSC1_4;
 343        }
 344#endif
 345}
 346#endif
 347
 348#ifdef CONFIG_POST
 349/*
 350 * Reads GPIO pin PSC6_3. A keypress is reported, if PSC6_3 is low. If PSC6_3
 351 * is left open, no keypress is detected.
 352 */
 353int post_hotkeys_pressed(void)
 354{
 355#ifdef CONFIG_STK52XX
 356        struct mpc5xxx_gpio *gpio;
 357
 358        gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
 359
 360        /*
 361         * Configure PSC6_0 through PSC6_3 as GPIO.
 362         */
 363        gpio->port_config &= ~(0x00700000);
 364
 365        /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */
 366        gpio->simple_gpioe |= 0x20000000;
 367
 368        /* Configure GPIO_IRDA_1 as input */
 369        gpio->simple_ddr &= ~(0x20000000);
 370
 371        return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
 372#else
 373        return 0;
 374#endif
 375}
 376#endif
 377
 378#ifdef CONFIG_BOARD_EARLY_INIT_R
 379int board_early_init_r (void)
 380{
 381
 382        extern int usb_cpu_init(void);
 383
 384#ifdef CONFIG_PS2MULT
 385        ps2mult_early_init();
 386#endif /* CONFIG_PS2MULT */
 387
 388#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
 389        /* Low level USB init, required for proper kernel operation */
 390        usb_cpu_init();
 391#endif
 392
 393        return (0);
 394}
 395#endif
 396
 397#ifdef CONFIG_FO300
 398int silent_boot (void)
 399{
 400        vu_long timer3_status;
 401
 402        /* Configure GPT3 as GPIO input */
 403        *(vu_long *)MPC5XXX_GPT3_ENABLE = 0x00000004;
 404
 405        /* Read in TIMER_3 pin status */
 406        timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS;
 407
 408#ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED
 409        /* Force silent console mode if S1 switch
 410         * is in closed position (TIMER_3 pin status is LOW). */
 411        if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0)
 412                return 1;
 413#else
 414        /* Force silent console mode if S1 switch
 415         * is in open position (TIMER_3 pin status is HIGH). */
 416        if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1)
 417                return 1;
 418#endif
 419
 420        return 0;
 421}
 422
 423int board_early_init_f (void)
 424{
 425        if (silent_boot())
 426                gd->flags |= GD_FLG_SILENT;
 427
 428        return 0;
 429}
 430#endif  /* CONFIG_FO300 */
 431
 432int last_stage_init (void)
 433{
 434        /*
 435         * auto scan for really existing devices and re-set chip select
 436         * configuration.
 437         */
 438        u16 save, tmp;
 439        int restore;
 440
 441        /*
 442         * Check for SRAM and SRAM size
 443         */
 444
 445        /* save original SRAM content  */
 446        save = *(volatile u16 *)CONFIG_SYS_CS2_START;
 447        restore = 1;
 448
 449        /* write test pattern to SRAM */
 450        *(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5;
 451        __asm__ volatile ("sync");
 452        /*
 453         * Put a different pattern on the data lines: otherwise they may float
 454         * long enough to read back what we wrote.
 455         */
 456        tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
 457        if (tmp == 0xA5A5)
 458                puts ("!! possible error in SRAM detection\n");
 459
 460        if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) {
 461                /* no SRAM at all, disable cs */
 462                *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
 463                *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
 464                *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
 465                restore = 0;
 466                __asm__ volatile ("sync");
 467        } else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) {
 468                /* make sure that we access a mirrored address */
 469                *(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111;
 470                __asm__ volatile ("sync");
 471                if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) {
 472                        /* SRAM size = 512 kByte */
 473                        *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START,
 474                                                                0x80000);
 475                        __asm__ volatile ("sync");
 476                        puts ("SRAM:  512 kB\n");
 477                }
 478                else
 479                        puts ("!! possible error in SRAM detection\n");
 480        } else {
 481                puts ("SRAM:  1 MB\n");
 482        }
 483        /* restore origianl SRAM content  */
 484        if (restore) {
 485                *(volatile u16 *)CONFIG_SYS_CS2_START = save;
 486                __asm__ volatile ("sync");
 487        }
 488
 489#ifndef CONFIG_TQM5200S /* The TQM5200S has no SM501 grafic controller */
 490        /*
 491         * Check for Grafic Controller
 492         */
 493
 494        /* save origianl FB content  */
 495        save = *(volatile u16 *)CONFIG_SYS_CS1_START;
 496        restore = 1;
 497
 498        /* write test pattern to FB memory */
 499        *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
 500        __asm__ volatile ("sync");
 501        /*
 502         * Put a different pattern on the data lines: otherwise they may float
 503         * long enough to read back what we wrote.
 504         */
 505        tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
 506        if (tmp == 0xA5A5)
 507                puts ("!! possible error in grafic controller detection\n");
 508
 509        if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
 510                /* no grafic controller at all, disable cs */
 511                *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
 512                *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
 513                *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
 514                restore = 0;
 515                __asm__ volatile ("sync");
 516        } else {
 517                puts ("VGA:   SMI501 (Voyager) with 8 MB\n");
 518        }
 519        /* restore origianl FB content  */
 520        if (restore) {
 521                *(volatile u16 *)CONFIG_SYS_CS1_START = save;
 522                __asm__ volatile ("sync");
 523        }
 524
 525#ifdef CONFIG_FO300
 526        if (silent_boot()) {
 527                setenv("bootdelay", "0");
 528                disable_ctrlc(1);
 529        }
 530#endif
 531#endif /* !CONFIG_TQM5200S */
 532
 533        return 0;
 534}
 535
 536#ifdef CONFIG_VIDEO_SM501
 537
 538#ifdef CONFIG_FO300
 539#define DISPLAY_WIDTH   800
 540#else
 541#define DISPLAY_WIDTH   640
 542#endif
 543#define DISPLAY_HEIGHT  480
 544
 545#ifdef CONFIG_VIDEO_SM501_8BPP
 546#error CONFIG_VIDEO_SM501_8BPP not supported.
 547#endif /* CONFIG_VIDEO_SM501_8BPP */
 548
 549#ifdef CONFIG_VIDEO_SM501_16BPP
 550#error CONFIG_VIDEO_SM501_16BPP not supported.
 551#endif /* CONFIG_VIDEO_SM501_16BPP */
 552#ifdef CONFIG_VIDEO_SM501_32BPP
 553static const SMI_REGS init_regs [] =
 554{
 555#if 0 /* CRT only */
 556        {0x00004, 0x0},
 557        {0x00048, 0x00021807},
 558        {0x0004C, 0x10090a01},
 559        {0x00054, 0x1},
 560        {0x00040, 0x00021807},
 561        {0x00044, 0x10090a01},
 562        {0x00054, 0x0},
 563        {0x80200, 0x00010000},
 564        {0x80204, 0x0},
 565        {0x80208, 0x0A000A00},
 566        {0x8020C, 0x02fa027f},
 567        {0x80210, 0x004a028b},
 568        {0x80214, 0x020c01df},
 569        {0x80218, 0x000201e9},
 570        {0x80200, 0x00013306},
 571#else  /* panel + CRT */
 572#ifdef CONFIG_FO300
 573        {0x00004, 0x0},
 574        {0x00048, 0x00021807},
 575        {0x0004C, 0x301a0a01},
 576        {0x00054, 0x1},
 577        {0x00040, 0x00021807},
 578        {0x00044, 0x091a0a01},
 579        {0x00054, 0x0},
 580        {0x80000, 0x0f013106},
 581        {0x80004, 0xc428bb17},
 582        {0x8000C, 0x00000000},
 583        {0x80010, 0x0C800C80},
 584        {0x80014, 0x03200000},
 585        {0x80018, 0x01e00000},
 586        {0x8001C, 0x00000000},
 587        {0x80020, 0x01e00320},
 588        {0x80024, 0x042a031f},
 589        {0x80028, 0x0086034a},
 590        {0x8002C, 0x020c01df},
 591        {0x80030, 0x000201ea},
 592        {0x80200, 0x00010000},
 593#else
 594        {0x00004, 0x0},
 595        {0x00048, 0x00021807},
 596        {0x0004C, 0x091a0a01},
 597        {0x00054, 0x1},
 598        {0x00040, 0x00021807},
 599        {0x00044, 0x091a0a01},
 600        {0x00054, 0x0},
 601        {0x80000, 0x0f013106},
 602        {0x80004, 0xc428bb17},
 603        {0x8000C, 0x00000000},
 604        {0x80010, 0x0a000a00},
 605        {0x80014, 0x02800000},
 606        {0x80018, 0x01e00000},
 607        {0x8001C, 0x00000000},
 608        {0x80020, 0x01e00280},
 609        {0x80024, 0x02fa027f},
 610        {0x80028, 0x004a028b},
 611        {0x8002C, 0x020c01df},
 612        {0x80030, 0x000201e9},
 613        {0x80200, 0x00010000},
 614#endif /* #ifdef CONFIG_FO300 */
 615#endif
 616        {0, 0}
 617};
 618#endif /* CONFIG_VIDEO_SM501_32BPP */
 619
 620#ifdef CONFIG_CONSOLE_EXTRA_INFO
 621/*
 622 * Return text to be printed besides the logo.
 623 */
 624void video_get_info_str (int line_number, char *info)
 625{
 626        if (line_number == 1) {
 627        strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
 628#if defined (CONFIG_STK52XX) || defined (CONFIG_TB5200) || defined(CONFIG_FO300)
 629        } else if (line_number == 2) {
 630#if defined (CONFIG_STK52XX)
 631                strcpy (info, "        on a STK52xx carrier board");
 632#endif
 633#if defined (CONFIG_TB5200)
 634                strcpy (info, "        on a TB5200 carrier board");
 635#endif
 636#if defined (CONFIG_FO300)
 637                strcpy (info, "        on a FO300 carrier board");
 638#endif
 639#endif
 640        }
 641        else {
 642                info [0] = '\0';
 643        }
 644}
 645#endif
 646
 647/*
 648 * Returns SM501 register base address. First thing called in the
 649 * driver. Checks if SM501 is physically present.
 650 */
 651unsigned int board_video_init (void)
 652{
 653        u16 save, tmp;
 654        int restore, ret;
 655
 656        /*
 657         * Check for Grafic Controller
 658         */
 659
 660        /* save origianl FB content  */
 661        save = *(volatile u16 *)CONFIG_SYS_CS1_START;
 662        restore = 1;
 663
 664        /* write test pattern to FB memory */
 665        *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
 666        __asm__ volatile ("sync");
 667        /*
 668         * Put a different pattern on the data lines: otherwise they may float
 669         * long enough to read back what we wrote.
 670         */
 671        tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
 672        if (tmp == 0xA5A5)
 673                puts ("!! possible error in grafic controller detection\n");
 674
 675        if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
 676                /* no grafic controller found */
 677                restore = 0;
 678                ret = 0;
 679        } else {
 680                ret = SM501_MMIO_BASE;
 681        }
 682
 683        if (restore) {
 684                *(volatile u16 *)CONFIG_SYS_CS1_START = save;
 685                __asm__ volatile ("sync");
 686        }
 687        return ret;
 688}
 689
 690/*
 691 * Returns SM501 framebuffer address
 692 */
 693unsigned int board_video_get_fb (void)
 694{
 695        return SM501_FB_BASE;
 696}
 697
 698/*
 699 * Called after initializing the SM501 and before clearing the screen.
 700 */
 701void board_validate_screen (unsigned int base)
 702{
 703}
 704
 705/*
 706 * Return a pointer to the initialization sequence.
 707 */
 708const SMI_REGS *board_get_regs (void)
 709{
 710        return init_regs;
 711}
 712
 713int board_get_width (void)
 714{
 715        return DISPLAY_WIDTH;
 716}
 717
 718int board_get_height (void)
 719{
 720        return DISPLAY_HEIGHT;
 721}
 722
 723#endif /* CONFIG_VIDEO_SM501 */
 724
 725#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 726void ft_board_setup(void *blob, bd_t *bd)
 727{
 728        ft_cpu_setup(blob, bd);
 729}
 730#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
 731
 732int board_eth_init(bd_t *bis)
 733{
 734        cpu_eth_init(bis); /* Built in FEC comes first */
 735        return pci_eth_init(bis);
 736}
 737