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9#include <common.h>
10#include <malloc.h>
11#include <part.h>
12#include <mmc.h>
13
14#include <asm/io.h>
15#include <asm/errno.h>
16#include <asm/byteorder.h>
17#include <asm/blackfin.h>
18#include <asm/portmux.h>
19#include <asm/mach-common/bits/sdh.h>
20#include <asm/mach-common/bits/dma.h>
21
22#if defined(__ADSPBF51x__)
23# define bfin_read_SDH_PWR_CTL bfin_read_RSI_PWR_CONTROL
24# define bfin_write_SDH_PWR_CTL bfin_write_RSI_PWR_CONTROL
25# define bfin_read_SDH_CLK_CTL bfin_read_RSI_CLK_CONTROL
26# define bfin_write_SDH_CLK_CTL bfin_write_RSI_CLK_CONTROL
27# define bfin_write_SDH_ARGUMENT bfin_write_RSI_ARGUMENT
28# define bfin_write_SDH_COMMAND bfin_write_RSI_COMMAND
29# define bfin_read_SDH_RESPONSE0 bfin_read_RSI_RESPONSE0
30# define bfin_read_SDH_RESPONSE1 bfin_read_RSI_RESPONSE1
31# define bfin_read_SDH_RESPONSE2 bfin_read_RSI_RESPONSE2
32# define bfin_read_SDH_RESPONSE3 bfin_read_RSI_RESPONSE3
33# define bfin_write_SDH_DATA_TIMER bfin_write_RSI_DATA_TIMER
34# define bfin_write_SDH_DATA_LGTH bfin_write_RSI_DATA_LGTH
35# define bfin_read_SDH_DATA_CTL bfin_read_RSI_DATA_CONTROL
36# define bfin_write_SDH_DATA_CTL bfin_write_RSI_DATA_CONTROL
37# define bfin_read_SDH_STATUS bfin_read_RSI_STATUS
38# define bfin_write_SDH_STATUS_CLR bfin_write_RSI_STATUSCL
39# define bfin_read_SDH_CFG bfin_read_RSI_CONFIG
40# define bfin_write_SDH_CFG bfin_write_RSI_CONFIG
41# define bfin_write_DMA_START_ADDR bfin_write_DMA4_START_ADDR
42# define bfin_write_DMA_X_COUNT bfin_write_DMA4_X_COUNT
43# define bfin_write_DMA_X_MODIFY bfin_write_DMA4_X_MODIFY
44# define bfin_write_DMA_CONFIG bfin_write_DMA4_CONFIG
45# define PORTMUX_PINS \
46 { P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0 }
47#elif defined(__ADSPBF54x__)
48# define bfin_write_DMA_START_ADDR bfin_write_DMA22_START_ADDR
49# define bfin_write_DMA_X_COUNT bfin_write_DMA22_X_COUNT
50# define bfin_write_DMA_X_MODIFY bfin_write_DMA22_X_MODIFY
51# define bfin_write_DMA_CONFIG bfin_write_DMA22_CONFIG
52# define PORTMUX_PINS \
53 { P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0 }
54#else
55# error no support for this proc yet
56#endif
57
58static int
59sdh_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
60{
61 unsigned int status, timeout;
62 int cmd = mmc_cmd->cmdidx;
63 int flags = mmc_cmd->resp_type;
64 int arg = mmc_cmd->cmdarg;
65 int ret;
66 u16 sdh_cmd;
67
68 sdh_cmd = cmd | CMD_E;
69 if (flags & MMC_RSP_PRESENT)
70 sdh_cmd |= CMD_RSP;
71 if (flags & MMC_RSP_136)
72 sdh_cmd |= CMD_L_RSP;
73
74 bfin_write_SDH_ARGUMENT(arg);
75 bfin_write_SDH_COMMAND(sdh_cmd);
76
77
78 timeout = 0;
79 do {
80 if (++timeout > 1000000) {
81 status = CMD_TIME_OUT;
82 break;
83 }
84 udelay(1);
85 status = bfin_read_SDH_STATUS();
86 } while (!(status & (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT |
87 CMD_CRC_FAIL)));
88
89 if (flags & MMC_RSP_PRESENT) {
90 mmc_cmd->response[0] = bfin_read_SDH_RESPONSE0();
91 if (flags & MMC_RSP_136) {
92 mmc_cmd->response[1] = bfin_read_SDH_RESPONSE1();
93 mmc_cmd->response[2] = bfin_read_SDH_RESPONSE2();
94 mmc_cmd->response[3] = bfin_read_SDH_RESPONSE3();
95 }
96 }
97
98 if (status & CMD_TIME_OUT)
99 ret = TIMEOUT;
100 else if (status & CMD_CRC_FAIL && flags & MMC_RSP_CRC)
101 ret = COMM_ERR;
102 else
103 ret = 0;
104
105 bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT |
106 CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT);
107
108 return ret;
109}
110
111
112static int sdh_setup_data(struct mmc *mmc, struct mmc_data *data)
113{
114 u16 data_ctl = 0;
115 u16 dma_cfg = 0;
116 int ret = 0;
117
118
119 if (data->flags & MMC_DATA_WRITE)
120 return UNUSABLE_ERR;
121 data_ctl |= ((ffs(data->blocksize) - 1) << 4);
122 data_ctl |= DTX_DIR;
123 bfin_write_SDH_DATA_CTL(data_ctl);
124 dma_cfg = WDSIZE_32 | RESTART | WNR | DMAEN;
125
126 bfin_write_SDH_DATA_TIMER(0xFFFF);
127
128 blackfin_dcache_flush_invalidate_range(data->dest,
129 data->dest + data->blocksize);
130
131 bfin_write_DMA_START_ADDR(data->dest);
132 bfin_write_DMA_X_COUNT(data->blocksize / 4);
133 bfin_write_DMA_X_MODIFY(4);
134 bfin_write_DMA_CONFIG(dma_cfg);
135 bfin_write_SDH_DATA_LGTH(data->blocksize);
136
137 bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);
138
139 return ret;
140}
141
142
143static int bfin_sdh_request(struct mmc *mmc, struct mmc_cmd *cmd,
144 struct mmc_data *data)
145{
146 u32 status;
147 int ret = 0;
148
149 ret = sdh_send_cmd(mmc, cmd);
150 if (ret) {
151 printf("sending CMD%d failed\n", cmd->cmdidx);
152 return ret;
153 }
154 if (data) {
155 ret = sdh_setup_data(mmc, data);
156 do {
157 udelay(1);
158 status = bfin_read_SDH_STATUS();
159 } while (!(status & (DAT_BLK_END | DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN)));
160
161 if (status & DAT_TIME_OUT) {
162 bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT);
163 ret |= TIMEOUT;
164 } else if (status & (DAT_CRC_FAIL | RX_OVERRUN)) {
165 bfin_write_SDH_STATUS_CLR(DAT_CRC_FAIL_STAT | RX_OVERRUN_STAT);
166 ret |= COMM_ERR;
167 } else
168 bfin_write_SDH_STATUS_CLR(DAT_BLK_END_STAT | DAT_END_STAT);
169
170 if (ret) {
171 printf("tranfering data failed\n");
172 return ret;
173 }
174 }
175 return 0;
176}
177
178static void sdh_set_clk(unsigned long clk)
179{
180 unsigned long sys_clk;
181 unsigned long clk_div;
182 u16 clk_ctl = 0;
183
184 clk_ctl = bfin_read_SDH_CLK_CTL();
185 if (clk) {
186
187 sys_clk = get_sclk();
188 bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E);
189 if (sys_clk % (2 * clk) == 0)
190 clk_div = sys_clk / (2 * clk) - 1;
191 else
192 clk_div = sys_clk / (2 * clk);
193
194 if (clk_div > 0xff)
195 clk_div = 0xff;
196 clk_ctl |= (clk_div & 0xff);
197 clk_ctl |= CLK_E;
198 bfin_write_SDH_CLK_CTL(clk_ctl);
199 } else
200 bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E);
201}
202
203static void bfin_sdh_set_ios(struct mmc *mmc)
204{
205 u16 cfg = 0;
206 u16 clk_ctl = 0;
207
208 if (mmc->bus_width == 4) {
209 cfg = bfin_read_SDH_CFG();
210 cfg &= ~0x80;
211 cfg |= 0x40;
212 bfin_write_SDH_CFG(cfg);
213 clk_ctl |= WIDE_BUS;
214 }
215 bfin_write_SDH_CLK_CTL(clk_ctl);
216 sdh_set_clk(mmc->clock);
217}
218
219static int bfin_sdh_init(struct mmc *mmc)
220{
221 const unsigned short pins[] = PORTMUX_PINS;
222 u16 pwr_ctl = 0;
223
224
225 peripheral_request_list(pins, "bfin_sdh");
226#if defined(__ADSPBF54x__)
227 bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
228#endif
229 bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
230
231 bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | 0x60);
232
233 pwr_ctl |= ROD_CTL;
234 pwr_ctl |= PWR_ON;
235 bfin_write_SDH_PWR_CTL(pwr_ctl);
236 return 0;
237}
238
239
240int bfin_mmc_init(bd_t *bis)
241{
242 struct mmc *mmc = NULL;
243
244 mmc = malloc(sizeof(struct mmc));
245
246 if (!mmc)
247 return -ENOMEM;
248 sprintf(mmc->name, "Blackfin SDH");
249 mmc->send_cmd = bfin_sdh_request;
250 mmc->set_ios = bfin_sdh_set_ios;
251 mmc->init = bfin_sdh_init;
252 mmc->host_caps = MMC_MODE_4BIT;
253
254 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
255 mmc->f_max = get_sclk();
256 mmc->f_min = mmc->f_max >> 9;
257 mmc->block_dev.part_type = PART_TYPE_DOS;
258
259 mmc_register(mmc);
260
261 return 0;
262}
263
