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11#include <common.h>
12#include <malloc.h>
13#include <spi.h>
14
15#include <asm/blackfin.h>
16#include <asm/dma.h>
17#include <asm/gpio.h>
18#include <asm/portmux.h>
19#include <asm/mach-common/bits/spi.h>
20
21struct bfin_spi_slave {
22 struct spi_slave slave;
23 void *mmr_base;
24 u16 ctl, baud, flg;
25};
26
27#define MAKE_SPI_FUNC(mmr, off) \
28static inline void write_##mmr(struct bfin_spi_slave *bss, u16 val) { bfin_write16(bss->mmr_base + off, val); } \
29static inline u16 read_##mmr(struct bfin_spi_slave *bss) { return bfin_read16(bss->mmr_base + off); }
30MAKE_SPI_FUNC(SPI_CTL, 0x00)
31MAKE_SPI_FUNC(SPI_FLG, 0x04)
32MAKE_SPI_FUNC(SPI_STAT, 0x08)
33MAKE_SPI_FUNC(SPI_TDBR, 0x0c)
34MAKE_SPI_FUNC(SPI_RDBR, 0x10)
35MAKE_SPI_FUNC(SPI_BAUD, 0x14)
36
37#define to_bfin_spi_slave(s) container_of(s, struct bfin_spi_slave, slave)
38
39#define gpio_cs(cs) ((cs) - MAX_CTRL_CS)
40#ifdef CONFIG_BFIN_SPI_GPIO_CS
41# define is_gpio_cs(cs) ((cs) > MAX_CTRL_CS)
42#else
43# define is_gpio_cs(cs) 0
44#endif
45
46int spi_cs_is_valid(unsigned int bus, unsigned int cs)
47{
48 if (is_gpio_cs(cs))
49 return gpio_is_valid(gpio_cs(cs));
50 else
51 return (cs >= 1 && cs <= MAX_CTRL_CS);
52}
53
54void spi_cs_activate(struct spi_slave *slave)
55{
56 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
57
58 if (is_gpio_cs(slave->cs)) {
59 unsigned int cs = gpio_cs(slave->cs);
60 gpio_set_value(cs, bss->flg);
61 debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
62 } else {
63 write_SPI_FLG(bss,
64 (read_SPI_FLG(bss) &
65 ~((!bss->flg << 8) << slave->cs)) |
66 (1 << slave->cs));
67 debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
68 }
69
70 SSYNC();
71}
72
73void spi_cs_deactivate(struct spi_slave *slave)
74{
75 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
76
77 if (is_gpio_cs(slave->cs)) {
78 unsigned int cs = gpio_cs(slave->cs);
79 gpio_set_value(cs, !bss->flg);
80 debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
81 } else {
82 u16 flg;
83
84
85
86
87
88 flg = read_SPI_FLG(bss) | ((!bss->flg << 8) << slave->cs);
89 write_SPI_FLG(bss, flg);
90 SSYNC();
91 debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
92
93 flg &= ~(1 << slave->cs);
94 write_SPI_FLG(bss, flg);
95 debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
96 }
97
98 SSYNC();
99}
100
101void spi_init()
102{
103}
104
105#ifdef SPI_CTL
106# define SPI0_CTL SPI_CTL
107#endif
108
109#define SPI_PINS(n) \
110 [n] = { 0, P_SPI##n##_SCK, P_SPI##n##_MISO, P_SPI##n##_MOSI, 0 }
111static unsigned short pins[][5] = {
112#ifdef SPI0_CTL
113 SPI_PINS(0),
114#endif
115#ifdef SPI1_CTL
116 SPI_PINS(1),
117#endif
118#ifdef SPI2_CTL
119 SPI_PINS(2),
120#endif
121};
122
123#define SPI_CS_PINS(n) \
124 [n] = { \
125 P_SPI##n##_SSEL1, P_SPI##n##_SSEL2, P_SPI##n##_SSEL3, \
126 P_SPI##n##_SSEL4, P_SPI##n##_SSEL5, P_SPI##n##_SSEL6, \
127 P_SPI##n##_SSEL7, \
128 }
129static const unsigned short cs_pins[][7] = {
130#ifdef SPI0_CTL
131 SPI_CS_PINS(0),
132#endif
133#ifdef SPI1_CTL
134 SPI_CS_PINS(1),
135#endif
136#ifdef SPI2_CTL
137 SPI_CS_PINS(2),
138#endif
139};
140
141struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
142 unsigned int max_hz, unsigned int mode)
143{
144 struct bfin_spi_slave *bss;
145 ulong sclk;
146 u32 mmr_base;
147 u32 baud;
148
149 if (!spi_cs_is_valid(bus, cs))
150 return NULL;
151
152 if (bus >= ARRAY_SIZE(pins) || pins[bus] == NULL) {
153 debug("%s: invalid bus %u\n", __func__, bus);
154 return NULL;
155 }
156 switch (bus) {
157#ifdef SPI0_CTL
158 case 0: mmr_base = SPI0_CTL; break;
159#endif
160#ifdef SPI1_CTL
161 case 1: mmr_base = SPI1_CTL; break;
162#endif
163#ifdef SPI2_CTL
164 case 2: mmr_base = SPI2_CTL; break;
165#endif
166 default: return NULL;
167 }
168
169 sclk = get_sclk();
170 baud = sclk / (2 * max_hz);
171
172 if (sclk % (2 * max_hz))
173 baud += 1;
174 if (baud < 2)
175 baud = 2;
176 else if (baud > (u16)-1)
177 baud = -1;
178
179 bss = malloc(sizeof(*bss));
180 if (!bss)
181 return NULL;
182
183 bss->slave.bus = bus;
184 bss->slave.cs = cs;
185 bss->mmr_base = (void *)mmr_base;
186 bss->ctl = SPE | MSTR | TDBR_CORE;
187 if (mode & SPI_CPHA) bss->ctl |= CPHA;
188 if (mode & SPI_CPOL) bss->ctl |= CPOL;
189 if (mode & SPI_LSB_FIRST) bss->ctl |= LSBF;
190 bss->baud = baud;
191 bss->flg = mode & SPI_CS_HIGH ? 1 : 0;
192
193 debug("%s: bus:%i cs:%i mmr:%x ctl:%x baud:%i flg:%i\n", __func__,
194 bus, cs, mmr_base, bss->ctl, baud, bss->flg);
195
196 return &bss->slave;
197}
198
199void spi_free_slave(struct spi_slave *slave)
200{
201 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
202 free(bss);
203}
204
205int spi_claim_bus(struct spi_slave *slave)
206{
207 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
208
209 debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
210
211 if (is_gpio_cs(slave->cs)) {
212 unsigned int cs = gpio_cs(slave->cs);
213 gpio_request(cs, "bfin-spi");
214 gpio_direction_output(cs, !bss->flg);
215 pins[slave->bus][0] = P_DONTCARE;
216 } else
217 pins[slave->bus][0] = cs_pins[slave->bus][slave->cs - 1];
218 peripheral_request_list(pins[slave->bus], "bfin-spi");
219
220 write_SPI_CTL(bss, bss->ctl);
221 write_SPI_BAUD(bss, bss->baud);
222 SSYNC();
223
224 return 0;
225}
226
227void spi_release_bus(struct spi_slave *slave)
228{
229 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
230
231 debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
232
233 peripheral_free_list(pins[slave->bus]);
234 if (is_gpio_cs(slave->cs))
235 gpio_free(gpio_cs(slave->cs));
236
237 write_SPI_CTL(bss, 0);
238 SSYNC();
239}
240
241#ifdef __ADSPBF54x__
242# define SPI_DMA_BASE DMA4_NEXT_DESC_PTR
243#elif defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__) || \
244 defined(__ADSPBF538__) || defined(__ADSPBF539__)
245# define SPI_DMA_BASE DMA5_NEXT_DESC_PTR
246#elif defined(__ADSPBF561__)
247# define SPI_DMA_BASE DMA2_4_NEXT_DESC_PTR
248#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) || \
249 defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
250# define SPI_DMA_BASE DMA7_NEXT_DESC_PTR
251#else
252# error "Please provide SPI DMA channel defines"
253#endif
254static volatile struct dma_register *dma = (void *)SPI_DMA_BASE;
255
256#ifndef CONFIG_BFIN_SPI_IDLE_VAL
257# define CONFIG_BFIN_SPI_IDLE_VAL 0xff
258#endif
259
260#ifdef CONFIG_BFIN_SPI_NO_DMA
261# define SPI_DMA 0
262#else
263# define SPI_DMA 1
264#endif
265
266static int spi_dma_xfer(struct bfin_spi_slave *bss, const u8 *tx, u8 *rx,
267 uint bytes)
268{
269 int ret = -1;
270 u16 ndsize, spi_config, dma_config;
271 struct dmasg dmasg[2];
272 const u8 *buf;
273
274 if (tx) {
275 debug("%s: doing half duplex TX\n", __func__);
276 buf = tx;
277 spi_config = TDBR_DMA;
278 dma_config = 0;
279 } else {
280 debug("%s: doing half duplex RX\n", __func__);
281 buf = rx;
282 spi_config = RDBR_DMA;
283 dma_config = WNR;
284 }
285
286 dmasg[0].start_addr = (unsigned long)buf;
287 dmasg[0].x_modify = 1;
288 dma_config |= WDSIZE_8 | DMAEN;
289 if (bytes <= 65536) {
290 blackfin_dcache_flush_invalidate_range(buf, buf + bytes);
291 ndsize = NDSIZE_5;
292 dmasg[0].cfg = NDSIZE_0 | dma_config | FLOW_STOP | DI_EN;
293 dmasg[0].x_count = bytes;
294 } else {
295 blackfin_dcache_flush_invalidate_range(buf, buf + 65536 - 1);
296 ndsize = NDSIZE_7;
297 dmasg[0].cfg = NDSIZE_5 | dma_config | FLOW_ARRAY | DMA2D;
298 dmasg[0].x_count = 0;
299 dmasg[0].y_count = bytes >> 16;
300 dmasg[0].y_modify = 1;
301 dmasg[1].start_addr = (unsigned long)(buf + (bytes & ~0xFFFF));
302 dmasg[1].cfg = NDSIZE_0 | dma_config | FLOW_STOP | DI_EN;
303 dmasg[1].x_count = bytes & 0xFFFF;
304 dmasg[1].x_modify = 1;
305 }
306
307 dma->cfg = 0;
308 dma->irq_status = DMA_DONE | DMA_ERR;
309 dma->curr_desc_ptr = dmasg;
310 write_SPI_CTL(bss, (bss->ctl & ~TDBR_CORE));
311 write_SPI_STAT(bss, -1);
312 SSYNC();
313
314 write_SPI_TDBR(bss, CONFIG_BFIN_SPI_IDLE_VAL);
315 dma->cfg = ndsize | FLOW_ARRAY | DMAEN;
316 write_SPI_CTL(bss, (bss->ctl & ~TDBR_CORE) | spi_config);
317 SSYNC();
318
319
320
321
322
323
324 if (bytes > 65536)
325 blackfin_dcache_flush_invalidate_range(buf + 65536, buf + bytes);
326
327 while (!(dma->irq_status & DMA_DONE))
328 if (ctrlc())
329 goto done;
330
331 dma->cfg = 0;
332
333 ret = 0;
334 done:
335 write_SPI_CTL(bss, bss->ctl);
336 return ret;
337}
338
339static int spi_pio_xfer(struct bfin_spi_slave *bss, const u8 *tx, u8 *rx,
340 uint bytes)
341{
342
343 while (bytes--) {
344 u8 value = (tx ? *tx++ : CONFIG_BFIN_SPI_IDLE_VAL);
345 debug("%s: tx:%x ", __func__, value);
346 write_SPI_TDBR(bss, value);
347 SSYNC();
348 while ((read_SPI_STAT(bss) & TXS))
349 if (ctrlc())
350 return -1;
351 while (!(read_SPI_STAT(bss) & SPIF))
352 if (ctrlc())
353 return -1;
354 while (!(read_SPI_STAT(bss) & RXS))
355 if (ctrlc())
356 return -1;
357 value = read_SPI_RDBR(bss);
358 if (rx)
359 *rx++ = value;
360 debug("rx:%x\n", value);
361 }
362
363 return 0;
364}
365
366int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
367 void *din, unsigned long flags)
368{
369 struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
370 const u8 *tx = dout;
371 u8 *rx = din;
372 uint bytes = bitlen / 8;
373 int ret = 0;
374
375 debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
376 slave->bus, slave->cs, bitlen, bytes, flags);
377
378 if (bitlen == 0)
379 goto done;
380
381
382 if (bitlen % 8) {
383 flags |= SPI_XFER_END;
384 goto done;
385 }
386
387 if (flags & SPI_XFER_BEGIN)
388 spi_cs_activate(slave);
389
390
391 if (SPI_DMA && bytes > 6 && (!tx ))
392 ret = spi_dma_xfer(bss, tx, rx, bytes);
393 else
394 ret = spi_pio_xfer(bss, tx, rx, bytes);
395
396 done:
397 if (flags & SPI_XFER_END)
398 spi_cs_deactivate(slave);
399
400 return ret;
401}
402
