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34
35#ifndef __CONFIG_H
36#define __CONFIG_H
37
38#define CONFIG_PPCHAMELEON_MODULE_BA 0
39#define CONFIG_PPCHAMELEON_MODULE_ME 1
40#define CONFIG_PPCHAMELEON_MODULE_HI 2
41#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
42#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
43#endif
44
45
46
47
48
49#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
50#define CONFIG_PPCHAMELEON_CLK_25
51#endif
52
53#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
54#error "* Two external frequencies (SysClk) are defined! *"
55#endif
56
57#undef CONFIG_PPCHAMELEON_SMI712
58
59
60
61
62#undef __DEBUG_START_FROM_SRAM__
63#define __DISABLE_MACHINE_EXCEPTION__
64
65#ifdef __DEBUG_START_FROM_SRAM__
66#define CONFIG_SYS_DUMMY_FLASH_SIZE 1024*1024*4
67#endif
68
69
70
71
72
73
74#define CONFIG_405EP 1
75#define CONFIG_4xx 1
76#define CONFIG_PPCHAMELEONEVB 1
77
78#define CONFIG_SYS_TEXT_BASE 0xFFFB0000
79#define CONFIG_SYS_LDSCRIPT "board/dave/PPChameleonEVB/u-boot.lds"
80
81#define CONFIG_BOARD_EARLY_INIT_F 1
82#define CONFIG_MISC_INIT_R 1
83
84#ifdef CONFIG_PPCHAMELEON_CLK_25
85# define CONFIG_SYS_CLK_FREQ 25000000
86#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
87#define CONFIG_SYS_CLK_FREQ 33333333
88#else
89# error "* External frequency (SysClk) not defined! *"
90#endif
91
92#define CONFIG_CONS_INDEX 2
93#define CONFIG_SYS_NS16550
94#define CONFIG_SYS_NS16550_SERIAL
95#define CONFIG_SYS_NS16550_REG_SIZE 1
96#define CONFIG_SYS_NS16550_CLK get_serial_clock()
97#define CONFIG_BAUDRATE 115200
98#define CONFIG_BOOTDELAY 5
99
100#define CONFIG_VERSION_VARIABLE 1
101#define CONFIG_IDENT_STRING "1"
102
103#undef CONFIG_BOOTARGS
104
105
106#define CONFIG_ENV_OVERWRITE
107#define CONFIG_ETHADDR 00:50:C2:1E:AF:FE
108#define CONFIG_HAS_ETH1
109#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD
110
111#define CONFIG_LOADS_ECHO 1
112#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
113
114
115#define CONFIG_PPC4xx_EMAC
116#undef CONFIG_EXT_PHY
117#define CONFIG_NET_MULTI 1
118
119#define CONFIG_MII 1
120#ifndef CONFIG_EXT_PHY
121#define CONFIG_PHY_ADDR 1
122#define CONFIG_PHY1_ADDR 16
123#else
124#define CONFIG_PHY_ADDR 2
125#endif
126#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
127
128#define CONFIG_TIMESTAMP
129
130
131
132
133
134#define CONFIG_BOOTP_BOOTFILESIZE
135#define CONFIG_BOOTP_BOOTPATH
136#define CONFIG_BOOTP_GATEWAY
137#define CONFIG_BOOTP_HOSTNAME
138
139
140
141
142
143#include <config_cmd_default.h>
144
145#define CONFIG_CMD_DHCP
146#define CONFIG_CMD_ELF
147#define CONFIG_CMD_EEPROM
148#define CONFIG_CMD_I2C
149#define CONFIG_CMD_IRQ
150#define CONFIG_CMD_JFFS2
151#define CONFIG_CMD_MII
152#define CONFIG_CMD_NAND
153#define CONFIG_CMD_NFS
154#define CONFIG_CMD_SNTP
155
156
157#define CONFIG_MAC_PARTITION
158#define CONFIG_DOS_PARTITION
159
160#undef CONFIG_WATCHDOG
161
162#define CONFIG_RTC_MC146818
163#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500
164
165#define CONFIG_SDRAM_BANK0 1
166
167
168
169
170#define CONFIG_SYS_LONGHELP
171#define CONFIG_SYS_PROMPT "=> "
172
173#define CONFIG_SYS_HUSH_PARSER
174#ifdef CONFIG_SYS_HUSH_PARSER
175#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
176#endif
177
178#if defined(CONFIG_CMD_KGDB)
179#define CONFIG_SYS_CBSIZE 1024
180#else
181#define CONFIG_SYS_CBSIZE 256
182#endif
183#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
184#define CONFIG_SYS_MAXARGS 16
185#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
186
187#define CONFIG_SYS_DEVICE_NULLDEV 1
188
189#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
190
191#define CONFIG_SYS_MEMTEST_START 0x0400000
192#define CONFIG_SYS_MEMTEST_END 0x0C00000
193
194#undef CONFIG_SYS_EXT_SERIAL_CLOCK
195#define CONFIG_SYS_BASE_BAUD 691200
196
197
198#define CONFIG_SYS_BAUDRATE_TABLE \
199 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
200 57600, 115200, 230400, 460800, 921600 }
201
202#define CONFIG_SYS_LOAD_ADDR 0x100000
203#define CONFIG_SYS_EXTBDINFO 1
204
205#define CONFIG_SYS_HZ 1000
206
207#define CONFIG_ZERO_BOOTDELAY_CHECK
208
209
210
211
212
213#define CONFIG_SYS_NAND0_BASE 0xFF400000
214#define CONFIG_SYS_NAND1_BASE 0xFF000000
215#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }
216#define NAND_BIG_DELAY_US 25
217
218
219#define CONFIG_SYS_MAX_NAND_DEVICE 1
220#define NAND_NO_RB
221
222#define CONFIG_SYS_NAND0_CE (0x80000000 >> 1)
223#define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2)
224#define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3)
225#define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4)
226
227#define CONFIG_SYS_NAND1_CE (0x80000000 >> 14)
228#define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15)
229#define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16)
230#define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31)
231
232
233#define MACRO_NAND_DISABLE_CE(nandptr) do \
234{ \
235 switch((unsigned long)nandptr) \
236 { \
237 case CONFIG_SYS_NAND0_BASE: \
238 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \
239 break; \
240 case CONFIG_SYS_NAND1_BASE: \
241 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \
242 break; \
243 } \
244} while(0)
245
246#define MACRO_NAND_ENABLE_CE(nandptr) do \
247{ \
248 switch((unsigned long)nandptr) \
249 { \
250 case CONFIG_SYS_NAND0_BASE: \
251 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \
252 break; \
253 case CONFIG_SYS_NAND1_BASE: \
254 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \
255 break; \
256 } \
257} while(0)
258
259#define MACRO_NAND_CTL_CLRALE(nandptr) do \
260{ \
261 switch((unsigned long)nandptr) \
262 { \
263 case CONFIG_SYS_NAND0_BASE: \
264 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \
265 break; \
266 case CONFIG_SYS_NAND1_BASE: \
267 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \
268 break; \
269 } \
270} while(0)
271
272#define MACRO_NAND_CTL_SETALE(nandptr) do \
273{ \
274 switch((unsigned long)nandptr) \
275 { \
276 case CONFIG_SYS_NAND0_BASE: \
277 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \
278 break; \
279 case CONFIG_SYS_NAND1_BASE: \
280 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \
281 break; \
282 } \
283} while(0)
284
285#define MACRO_NAND_CTL_CLRCLE(nandptr) do \
286{ \
287 switch((unsigned long)nandptr) \
288 { \
289 case CONFIG_SYS_NAND0_BASE: \
290 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \
291 break; \
292 case CONFIG_SYS_NAND1_BASE: \
293 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \
294 break; \
295 } \
296} while(0)
297
298#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
299 switch((unsigned long)nandptr) { \
300 case CONFIG_SYS_NAND0_BASE: \
301 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \
302 break; \
303 case CONFIG_SYS_NAND1_BASE: \
304 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \
305 break; \
306 } \
307} while(0)
308
309#ifdef NAND_NO_RB
310
311#define NAND_WAIT_READY(nand) do { \
312 udelay(12); \
313} while (0)
314#else
315
316
317#endif
318
319#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
320#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
321#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
322#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
323
324
325
326
327
328#if 0
329#define PCI_HOST_ADAPTER 0
330#define PCI_HOST_FORCE 1
331#define PCI_HOST_AUTO 2
332
333#define CONFIG_PCI
334#define CONFIG_PCI_HOST PCI_HOST_FORCE
335#undef CONFIG_PCI_PNP
336
337
338#define CONFIG_PCI_SCAN_SHOW
339
340#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014
341#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000
342#define CONFIG_SYS_PCI_CLASSCODE 0x0b20
343
344#define CONFIG_SYS_PCI_PTM1LA 0x00000000
345#define CONFIG_SYS_PCI_PTM1MS 0xfc000001
346#define CONFIG_SYS_PCI_PTM1PCI 0x00000000
347#define CONFIG_SYS_PCI_PTM2LA 0xffc00000
348#define CONFIG_SYS_PCI_PTM2MS 0xffc00001
349#define CONFIG_SYS_PCI_PTM2PCI 0x04000000
350#endif
351
352
353
354
355
356
357#define CONFIG_SYS_SDRAM_BASE 0x00000000
358#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
359#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
360#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
361#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
362
363
364
365
366
367
368#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
369
370
371
372#define CONFIG_SYS_MAX_FLASH_BANKS 1
373#define CONFIG_SYS_MAX_FLASH_SECT 256
374
375#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
376#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
377
378#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
379#define CONFIG_SYS_FLASH_ADDR0 0x5555
380#define CONFIG_SYS_FLASH_ADDR1 0x2AAA
381
382
383
384
385#define CONFIG_SYS_FLASH_READ0 0x0000
386#define CONFIG_SYS_FLASH_READ1 0x0001
387#define CONFIG_SYS_FLASH_READ2 0x0002
388
389#define CONFIG_SYS_FLASH_EMPTY_INFO
390
391
392
393
394#define CONFIG_ENV_IS_IN_FLASH 1
395#define CONFIG_ENV_ADDR 0xFFFF8000
396#define CONFIG_ENV_SECT_SIZE 0x2000
397#define CONFIG_ENV_ADDR_REDUND 0xFFFFA000
398#define CONFIG_ENV_SIZE_REDUND 0x2000
399
400#define CONFIG_SYS_USE_PPCENV
401
402#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500
403#define CONFIG_SYS_NVRAM_SIZE 242
404
405
406
407
408#define CONFIG_HARD_I2C
409#define CONFIG_PPC4XX_I2C
410#define CONFIG_SYS_I2C_SPEED 400000
411#define CONFIG_SYS_I2C_SLAVE 0x7F
412
413#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
414#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
415
416
417#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
418
419
420#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
421
422
423
424
425
426
427
428#define FLASH_BASE0_PRELIM 0xFFC00000
429
430
431
432
433
434
435#define CONFIG_SYS_EBC_PB0AP 0x92015480
436#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
437
438
439
440#define CONFIG_SYS_EBC_PB1AP 0x92015480
441#define CONFIG_SYS_EBC_PB1CR 0xFF85A000
442
443
444#define CONFIG_SYS_EBC_PB2AP 0x92015480
445#define CONFIG_SYS_EBC_PB2CR 0xFF458000
446
447
448#define CONFIG_SYS_EBC_PB3AP 0x92015480
449#define CONFIG_SYS_EBC_PB3CR 0xFF058000
450
451#ifdef CONFIG_PPCHAMELEON_SMI712
452
453
454
455#define CONFIG_VIDEO
456#define CONFIG_CFB_CONSOLE
457#define CONFIG_VIDEO_SMI_LYNXEM
458#define CONFIG_VIDEO_LOGO
459
460#define CONFIG_CONSOLE_EXTRA_INFO
461#define CONFIG_VGA_AS_SINGLE_DEVICE
462
463#define CONFIG_SYS_ISA_IO 0xE8000000
464
465#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x303
466#endif
467
468
469
470
471
472#define CONFIG_SYS_FPGA_MODE 0x00
473#define CONFIG_SYS_FPGA_STATUS 0x02
474#define CONFIG_SYS_FPGA_TS 0x04
475#define CONFIG_SYS_FPGA_TS_LOW 0x06
476#define CONFIG_SYS_FPGA_TS_CAP0 0x10
477#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
478#define CONFIG_SYS_FPGA_TS_CAP1 0x14
479#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
480#define CONFIG_SYS_FPGA_TS_CAP2 0x18
481#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
482#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
483#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
484
485
486#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
487#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
488#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
489#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
490
491
492#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
493#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
494#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
495#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
496#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
497
498#define CONFIG_SYS_FPGA_SPARTAN2 1
499#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024
500
501
502#define CONFIG_SYS_FPGA_PRG 0x04000000
503#define CONFIG_SYS_FPGA_CLK 0x02000000
504#define CONFIG_SYS_FPGA_DATA 0x01000000
505#define CONFIG_SYS_FPGA_INIT 0x00010000
506#define CONFIG_SYS_FPGA_DONE 0x00008000
507
508
509
510
511
512#define CONFIG_SYS_TEMP_STACK_OCM 1
513
514
515#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
516#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
517#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
518#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
519
520#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
521#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536#define CONFIG_SYS_GPIO0_OSRL 0x40000550
537#define CONFIG_SYS_GPIO0_OSRH 0x00000110
538#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
539
540#define CONFIG_SYS_GPIO0_ISR1H 0x15555444
541#define CONFIG_SYS_GPIO0_TSRL 0x00000000
542#define CONFIG_SYS_GPIO0_TSRH 0x00000000
543#define CONFIG_SYS_GPIO0_TCR 0xF7FF8014
544
545#define CONFIG_NO_SERIAL_EEPROM
546
547
548
549#ifdef CONFIG_NO_SERIAL_EEPROM
550
551
552
553
554
555
556
557
558#undef AUTO_MEMORY_CONFIG
559#define DIMM_READ_ADDR 0xAB
560#define DIMM_WRITE_ADDR 0xAA
561
562
563#define PLL_ACTIVE 0x80000000
564#define CPC0_PLLMR1_SSCS 0x80000000
565#define PLL_RESET 0x40000000
566#define CPC0_PLLMR1_PLLR 0x40000000
567
568#define PLL_FBKDIV 0x00F00000
569#define CPC0_PLLMR1_FBDV 0x00F00000
570#define PLL_FBKDIV_16 0x00000000
571#define PLL_FBKDIV_1 0x00100000
572#define PLL_FBKDIV_2 0x00200000
573#define PLL_FBKDIV_3 0x00300000
574#define PLL_FBKDIV_4 0x00400000
575#define PLL_FBKDIV_5 0x00500000
576#define PLL_FBKDIV_6 0x00600000
577#define PLL_FBKDIV_7 0x00700000
578#define PLL_FBKDIV_8 0x00800000
579#define PLL_FBKDIV_9 0x00900000
580#define PLL_FBKDIV_10 0x00A00000
581#define PLL_FBKDIV_11 0x00B00000
582#define PLL_FBKDIV_12 0x00C00000
583#define PLL_FBKDIV_13 0x00D00000
584#define PLL_FBKDIV_14 0x00E00000
585#define PLL_FBKDIV_15 0x00F00000
586
587#define PLL_FWDDIVA 0x00070000
588#define CPC0_PLLMR1_FWDVA 0x00070000
589#define PLL_FWDDIVA_8 0x00000000
590#define PLL_FWDDIVA_7 0x00010000
591#define PLL_FWDDIVA_6 0x00020000
592#define PLL_FWDDIVA_5 0x00030000
593#define PLL_FWDDIVA_4 0x00040000
594#define PLL_FWDDIVA_3 0x00050000
595#define PLL_FWDDIVA_2 0x00060000
596#define PLL_FWDDIVA_1 0x00070000
597
598#define PLL_FWDDIVB 0x00007000
599#define CPC0_PLLMR1_FWDVB 0x00007000
600#define PLL_FWDDIVB_8 0x00000000
601#define PLL_FWDDIVB_7 0x00001000
602#define PLL_FWDDIVB_6 0x00002000
603#define PLL_FWDDIVB_5 0x00003000
604#define PLL_FWDDIVB_4 0x00004000
605#define PLL_FWDDIVB_3 0x00005000
606#define PLL_FWDDIVB_2 0x00006000
607#define PLL_FWDDIVB_1 0x00007000
608
609#define PLL_TUNE_MASK 0x000003FF
610#define PLL_TUNE_2_M_3 0x00000133
611#define PLL_TUNE_4_M_6 0x00000134
612#define PLL_TUNE_7_M_10 0x00000138
613#define PLL_TUNE_11_M_14 0x0000013C
614#define PLL_TUNE_15_M_40 0x0000023E
615#define PLL_TUNE_VCO_LOW 0x00000000
616#define PLL_TUNE_VCO_HI 0x00000080
617
618
619
620#define PLL_CPUDIV 0x00300000
621#define CPC0_PLLMR0_CCDV 0x00300000
622#define PLL_CPUDIV_1 0x00000000
623#define PLL_CPUDIV_2 0x00100000
624#define PLL_CPUDIV_3 0x00200000
625#define PLL_CPUDIV_4 0x00300000
626
627#define PLL_PLBDIV 0x00030000
628#define CPC0_PLLMR0_CBDV 0x00030000
629#define PLL_PLBDIV_1 0x00000000
630#define PLL_PLBDIV_2 0x00010000
631#define PLL_PLBDIV_3 0x00020000
632#define PLL_PLBDIV_4 0x00030000
633
634#define PLL_OPBDIV 0x00003000
635#define CPC0_PLLMR0_OPDV 0x00003000
636#define PLL_OPBDIV_1 0x00000000
637#define PLL_OPBDIV_2 0x00001000
638#define PLL_OPBDIV_3 0x00002000
639#define PLL_OPBDIV_4 0x00003000
640
641#define PLL_EXTBUSDIV 0x00000300
642#define CPC0_PLLMR0_EPDV 0x00000300
643#define PLL_EXTBUSDIV_2 0x00000000
644#define PLL_EXTBUSDIV_3 0x00000100
645#define PLL_EXTBUSDIV_4 0x00000200
646#define PLL_EXTBUSDIV_5 0x00000300
647
648#define PLL_MALDIV 0x00000030
649#define CPC0_PLLMR0_MPDV 0x00000030
650#define PLL_MALDIV_1 0x00000000
651#define PLL_MALDIV_2 0x00000010
652#define PLL_MALDIV_3 0x00000020
653#define PLL_MALDIV_4 0x00000030
654
655#define PLL_PCIDIV 0x00000003
656#define CPC0_PLLMR0_PPFD 0x00000003
657#define PLL_PCIDIV_1 0x00000000
658#define PLL_PCIDIV_2 0x00000001
659#define PLL_PCIDIV_3 0x00000002
660#define PLL_PCIDIV_4 0x00000003
661
662#ifdef CONFIG_PPCHAMELEON_CLK_25
663
664#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
665 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
666 PLL_MALDIV_1 | PLL_PCIDIV_4)
667#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \
668 PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \
669 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
670
671#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
672 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
673 PLL_MALDIV_1 | PLL_PCIDIV_4)
674#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \
675 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
676 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
677
678#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
679 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
680 PLL_MALDIV_1 | PLL_PCIDIV_4)
681#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
682 PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
683 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
684
685#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
686 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
687 PLL_MALDIV_1 | PLL_PCIDIV_2)
688#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
689 PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
690 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
691
692#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
693
694
695#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
696 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
697 PLL_MALDIV_1 | PLL_PCIDIV_4)
698#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \
699 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
700 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
701
702#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
703 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
704 PLL_MALDIV_1 | PLL_PCIDIV_4)
705#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
706 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
707 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
708
709#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
710 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
711 PLL_MALDIV_1 | PLL_PCIDIV_4)
712#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
713 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
714 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
715
716#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
717 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
718 PLL_MALDIV_1 | PLL_PCIDIV_2)
719#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
720 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
721 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
722
723#else
724#error "* External frequency (SysClk) not defined! *"
725#endif
726
727#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
728
729#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55
730#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55
731#define CONFIG_SYS_OPB_FREQ 55555555
732
733#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
734#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33
735#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33
736#define CONFIG_SYS_OPB_FREQ 66666666
737#else
738
739#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33
740#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33
741#define CONFIG_SYS_OPB_FREQ 66666666
742#endif
743
744#endif
745
746#define CONFIG_JFFS2_NAND 1
747#define NAND_CACHE_PAGES 16
748
749
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753
754#undef CONFIG_CMD_MTDPARTS
755#define CONFIG_JFFS2_DEV "nand"
756#define CONFIG_JFFS2_PART_SIZE 0x00200000
757#define CONFIG_JFFS2_PART_OFFSET 0x00000000
758
759
760
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764
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768
769#endif
770