1/* 2 * (C) Copyright 2001, 2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31#include <mpc8xx_irq.h> 32 33 34# ifdef DEBUG 35# warning DEBUG Defined 36# endif /* DEBUG */ 37 38/* 39 * High Level Configuration Options 40 * (easy to change) 41 */ 42#define CONFIG_MPC860 1 43#define CONFIG_IAD210 1 /* ...on a IAD210 module */ 44#define CONFIG_MPC860T 1 45#define CONFIG_MPC862 1 46 47#define CONFIG_SYS_TEXT_BASE 0x08000000 48 49#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 50 51#undef CONFIG_8xx_CONS_SMC1 52#undef CONFIG_8xx_CONS_SMC2 53#define CONFIG_8xx_CONS_SCC2 /* V24 on SCC2 */ 54#undef CONFIG_8xx_CONS_NONE 55#define CONFIG_BAUDRATE 9600 56 57 58# define MPC8XX_FACT 16 59# define CONFIG_8xx_GCLK_FREQ (64000000L) /* define if can't use get_gclk_freq */ 60# define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ 61 62#if 0 63# define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 64#else 65# define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 66#endif 67 68#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" 69 70/* using this define saves us updating another source file */ 71#define CONFIG_BOARD_EARLY_INIT_F 1 72#define CONFIG_MISC_INIT_R 73 74#undef CONFIG_BOOTARGS 75/* #define CONFIG_BOOTCOMMAND \ 76 "bootp;" \ 77 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ 78 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ 79 "bootm" 80*/ 81 82#define CONFIG_BOOTCOMMAND \ 83 "setenv bootargs root=/dev/nfs" \ 84 "ip=192.168.28.129:139.10.137.138:192.168.28.1:255.255.255.0:iadlinux002::off; " \ 85 86#undef CONFIG_WATCHDOG /* watchdog disabled */ 87 88/* #define CONFIG_STATUS_LED 1*/ /* Status LED enabled */ 89 90/* 91 * BOOTP options 92 */ 93#define CONFIG_BOOTP_SUBNETMASK 94#define CONFIG_BOOTP_GATEWAY 95#define CONFIG_BOOTP_HOSTNAME 96#define CONFIG_BOOTP_BOOTPATH 97#define CONFIG_BOOTP_BOOTFILESIZE 98 99 100# undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */ 101# define CONFIG_FEC_ENET 1 /* use FEC ethernet */ 102# define CONFIG_MII 1 103# define CONFIG_SYS_DISCOVER_PHY 1 104# define CONFIG_FEC_UTOPIA 1 105# define CONFIG_ETHADDR 08:00:06:26:A2:6D 106# define CONFIG_IPADDR 192.168.28.128 107# define CONFIG_SERVERIP 139.10.137.138 108# define CONFIG_SYS_DISCOVER_PHY 1 109 110#define CONFIG_MAC_PARTITION 111#define CONFIG_DOS_PARTITION 112 113/* enable I2C and select the hardware/software driver */ 114#undef CONFIG_HARD_I2C /* I2C with hardware support */ 115#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ 116# define CONFIG_SYS_I2C_SPEED 50000 117# define CONFIG_SYS_I2C_SLAVE 0xDD 118# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 119/* 120 * Software (bit-bang) I2C driver configuration 121 */ 122#define PB_SCL 0x00000020 /* PB 26 */ 123#define PB_SDA 0x00000010 /* PB 27 */ 124 125#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) 126#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) 127#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) 128#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) 129#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ 130 else immr->im_cpm.cp_pbdat &= ~PB_SDA 131#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ 132 else immr->im_cpm.cp_pbdat &= ~PB_SCL 133#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ 134 135#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 136 137 138/* 139 * Command line configuration. 140 */ 141#include <config_cmd_default.h> 142 143#define CONFIG_CMD_ASKENV 144#define CONFIG_CMD_DHCP 145#define CONFIG_CMD_DATE 146 147 148/* 149 * Miscellaneous configurable options 150 */ 151#define CONFIG_SYS_LONGHELP /* undef to save memory */ 152#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 153#if defined(CONFIG_CMD_KGDB) 154#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 155#else 156#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 157#endif 158#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 159#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 160#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 161 162#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ 163#define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ 164 165#define CONFIG_SYS_LOAD_ADDR 0x00100000 166 167#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 168 169#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 170 171/* 172 * Low Level Configuration Settings 173 * (address mappings, register initial values, etc.) 174 * You should know what you are doing if you make changes here. 175 */ 176/*----------------------------------------------------------------------- 177 * Internal Memory Mapped Register 178 */ 179#define CONFIG_SYS_IMMR 0xFFF00000 180#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024)) 181 182/*----------------------------------------------------------------------- 183 * Definitions for initial stack pointer and data area (in DPRAM) 184 */ 185#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 186#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 187#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 188#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 189 190/*----------------------------------------------------------------------- 191 * Start addresses for the final memory configuration 192 * (Set up by the startup code) 193 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 194 */ 195#define CONFIG_SYS_SDRAM_BASE 0x00000000 196#define CONFIG_SYS_FLASH_BASE 0x08000000 197#define CONFIG_SYS_FLASH_SIZE ((uint)(4 * 1024 * 1024)) /* max 16Mbyte */ 198 199#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 200 201#if defined(DEBUG) 202# define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 203#else 204# define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ 205#endif 206 207# define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 208# define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 209 210/* 211 * For booting Linux, the board info and command line data 212 * have to be in the first 8 MB of memory, since this is 213 * the maximum mapped by the Linux kernel during initialization. 214 */ 215#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 216/*----------------------------------------------------------------------- 217 * FLASH organization 218 */ 219#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 220#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ 221 222#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 223#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 224 225#define CONFIG_ENV_IS_IN_FLASH 1 226#define CONFIG_ENV_OFFSET 0x8000 227#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 228 229/*----------------------------------------------------------------------- 230 * Cache Configuration 231 */ 232#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 233#if defined(CONFIG_CMD_KGDB) 234#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 235#endif 236 237/*----------------------------------------------------------------------- 238 * SYPCR - System Protection Control 11-9 239 * SYPCR can only be written once after reset! 240 *----------------------------------------------------------------------- 241 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 242 */ 243#if defined(CONFIG_WATCHDOG) 244#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 245 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 246#else 247#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 248#endif 249 250/*----------------------------------------------------------------------- 251 * SIUMCR - SIU Module Configuration 11-6 252 *----------------------------------------------------------------------- 253 * PCMCIA config., multi-function pin tri-state 254 */ 255#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 256 257/*----------------------------------------------------------------------- 258 * TBSCR - Time Base Status and Control 11-26 259 *----------------------------------------------------------------------- 260 * Clear Reference Interrupt Status, Timebase freezing enabled 261 */ 262#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 263 264/*----------------------------------------------------------------------- 265 * PISCR - Periodic Interrupt Status and Control 11-31 266 *----------------------------------------------------------------------- 267 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 268 */ 269#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 270 271/*----------------------------------------------------------------------- 272 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 273 *----------------------------------------------------------------------- 274 * set the PLL, the low-power modes and the reset control (15-29) 275 */ 276#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ 277 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 278 279/*----------------------------------------------------------------------- 280 * SCCR - System Clock and reset Control Register 15-27 281 *----------------------------------------------------------------------- 282 * Set clock output, timebase and RTC source and divider, 283 * power management and some other internal clocks 284 */ 285#define SCCR_MASK SCCR_EBDF11 286 287#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \ 288 SCCR_DFBRG00 | SCCR_DFNL000 | SCCR_DFNH000 | \ 289 SCCR_DFLCD000 |SCCR_DFALCD00 ) 290 291/*----------------------------------------------------------------------- 292 * RCCR - RISC Controller Configuration Register 19-4 293 *----------------------------------------------------------------------- 294 */ 295/* +0x09C4 => DRQP = 10 (IDMA requests have lowest priority) */ 296#define CONFIG_SYS_RCCR 0x0020 297 298/*----------------------------------------------------------------------- 299 * PCMCIA stuff 300 *----------------------------------------------------------------------- 301 */ 302#define PCMCIA_MEM_ADDR ((uint)0xff020000) 303#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) 304 305/*----------------------------------------------------------------------- 306 * 307 *----------------------------------------------------------------------- 308 * 309 */ 310#define CONFIG_SYS_DER 0 311 312/* Because of the way the 860 starts up and assigns CS0 the 313* entire address space, we have to set the memory controller 314* differently. Normally, you write the option register 315* first, and then enable the chip select by writing the 316* base register. For CS0, you must write the base register 317* first, followed by the option register. 318*/ 319 320/* 321 * Init Memory Controller: 322 * 323 * BR0 and OR0 (FLASH) 324 */ 325 326#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ 327 328/* used to re-map FLASH both when starting from SRAM or FLASH: 329 * restrict access enough to keep SRAM working (if any) 330 * but not too much to meddle with FLASH accesses 331 */ 332#define CONFIG_SYS_REMAP_OR_AM 0xF8000000 /* OR addr mask */ 333#define CONFIG_SYS_PRELIM_OR_AM 0xF8000000 /* OR addr mask */ 334 335/* FLASH timing: 336 TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */ 337#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | \ 338 OR_SCY_3_CLK | OR_EHTR) 339 340#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 341#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 342 343/* 344 * BR2/3 and OR2/3 (SDRAM) 345 * 346 */ 347#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM bank #0 */ 348#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 349 350/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 351 352#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | OR_CSNT_SAM | OR_BI | OR_ACS_DIV4) 353#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 354#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V) 355 356/* 357 * Memory Periodic Timer Prescaler 358 */ 359 360/* periodic timer for refresh */ 361#define CONFIG_SYS_MAMR_PTA 124 /* start with divider for 64 MHz */ 362 363/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ 364#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 /* setting for 1 bank */ 365 366/* 367 * MAMR settings for SDRAM 368 */ 369 370#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 371 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 372 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_8X) 373 374#ifdef CONFIG_MPC860T 375 376/* Interrupt level assignments. 377*/ 378#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ 379 380#endif /* CONFIG_MPC860T */ 381 382 383#endif /* __CONFIG_H */ 384