1/* 2 * (C) Copyright 2003 Picture Elements, Inc. 3 * Stephen Williams <steve@icarus.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31/* 32 * High Level Configuration Options for the JSE board 33 * (Theoretically easy to change, but the board is fixed.) 34 */ 35 36#define CONFIG_JSE 1 37 /* JSE has a PPC405GPr */ 38#define CONFIG_405GP 1 39 /* ... which is a 4xxx series */ 40#define CONFIG_4x 1 41 /* ... with a 33MHz OSC. connected to the SysCLK input */ 42#define CONFIG_SYS_CLK_FREQ 33333333 43 /* ... with on-chip memory here (4KBytes) */ 44#define CONFIG_SYS_OCM_DATA_ADDR 0xF4000000 45#define CONFIG_SYS_OCM_DATA_SIZE 0x00001000 46 /* Do not set up locked dcache as init ram. */ 47#undef CONFIG_SYS_INIT_DCACHE_CS 48 49#define CONFIG_SYS_TEXT_BASE 0xFFF80000 50 51 /* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */ 52#define CONFIG_SYSTEMACE 1 53#define CONFIG_SYS_SYSTEMACE_BASE 0xf0000000 54#define CONFIG_SYS_SYSTEMACE_WIDTH 8 55#define CONFIG_DOS_PARTITION 1 56 57 /* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */ 58#define CONFIG_SYS_TEMP_STACK_OCM 1 59 /* ... place INIT RAM in the OCM address */ 60# define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR 61 /* ... give it the whole init ram */ 62# define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE 63 /* ... Shave a bit off the end for global data */ 64# define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 65 /* ... and place the stack pointer at the top of what's left. */ 66# define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 67 68 /* Enable board_pre_init function */ 69#define CONFIG_BOARD_PRE_INIT 1 70#define CONFIG_BOARD_EARLY_INIT_F 1 71 /* Disable post-clk setup init function */ 72#undef CONFIG_BOARD_POSTCLK_INIT 73 /* Disable call to post_init_f: late init function. */ 74#undef CONFIG_POST 75 /* Enable DRAM test. */ 76#define CONFIG_SYS_DRAM_TEST 1 77 /* Enable misc_init_r function. */ 78#define CONFIG_MISC_INIT_R 1 79 80 /* JSE has EEPROM chips that are good for environment. */ 81#undef CONFIG_ENV_IS_IN_NVRAM 82#undef CONFIG_ENV_IS_IN_FLASH 83#define CONFIG_ENV_IS_IN_EEPROM 1 84#undef CONFIG_ENV_IS_NOWHERE 85 86 /* This is the 7bit address of the device, not including P. */ 87#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 88 /* After the device address, need one more address byte. */ 89#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 90 /* The EEPROM is 512 bytes. */ 91#define CONFIG_SYS_EEPROM_SIZE 512 92 /* The EEPROM can do 16byte ( 1 << 4 ) page writes. */ 93#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 94#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 95 /* Put the environment in the second half. */ 96#define CONFIG_ENV_OFFSET 0x00 97#define CONFIG_ENV_SIZE 512 98 99 /* The JSE connects UART1 to the console tap connector. */ 100#define CONFIG_CONS_INDEX 2 101#define CONFIG_SYS_NS16550 102#define CONFIG_SYS_NS16550_SERIAL 103#define CONFIG_SYS_NS16550_REG_SIZE 1 104#define CONFIG_SYS_NS16550_CLK get_serial_clock() 105 106 /* Set console baudrate to 9600 */ 107#define CONFIG_BAUDRATE 9600 108 109/* 110 * Configuration related to auto-boot. 111 * 112 * CONFIG_BOOTDELAY sets the delay (in seconds) that U-Boot will wait 113 * before resorting to autoboot. This value can be overridden by the 114 * bootdelay environment variable. 115 * 116 * CONFIG_AUTOBOOT_PROMPT is the string that U-Boot emits to warn the 117 * user that an autoboot will happen. 118 * 119 * CONFIG_BOOTCOMMAND is the sequence of commands that U-Boot will 120 * execute to boot the JSE. This loads the uimage and initrd.img files 121 * from CompactFlash into memory, then boots them from memory. 122 * 123 * CONFIG_BOOTARGS is the arguments passed to the Linux kernel to get 124 * it going on the JSE. 125 */ 126#define CONFIG_BOOTDELAY 5 127#define CONFIG_BOOTARGS "root=/dev/ram0 init=/linuxrc rw" 128#define CONFIG_BOOTCOMMAND "fatload ace 0 2000000 uimage; fatload ace 0 2100000 initrd.img; bootm 2000000 2100000" 129 130 131#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 132#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 133 134#define CONFIG_PPC4xx_EMAC 135#define CONFIG_MII 1 /* MII PHY management */ 136#define CONFIG_PHY_ADDR 1 /* PHY address */ 137#define CONFIG_NET_MULTI 138 139 140/* 141 * BOOTP options 142 */ 143#define CONFIG_BOOTP_BOOTFILESIZE 144#define CONFIG_BOOTP_BOOTPATH 145#define CONFIG_BOOTP_GATEWAY 146#define CONFIG_BOOTP_HOSTNAME 147 148 149/* 150 * Command line configuration. 151 */ 152#include <config_cmd_default.h> 153 154#define CONFIG_CMD_DHCP 155#define CONFIG_CMD_EEPROM 156#define CONFIG_CMD_ELF 157#define CONFIG_CMD_FAT 158#define CONFIG_CMD_FLASH 159#define CONFIG_CMD_IRQ 160#define CONFIG_CMD_MII 161#define CONFIG_CMD_NET 162#define CONFIG_CMD_PCI 163#define CONFIG_CMD_PING 164 165 166 /* watchdog disabled */ 167#undef CONFIG_WATCHDOG 168 /* SPD EEPROM (sdram speed config) disabled */ 169#undef CONFIG_SPD_EEPROM 170#undef SPD_EEPROM_ADDRESS 171 172/* 173 * Miscellaneous configurable options 174 */ 175#define CONFIG_SYS_LONGHELP /* undef to save memory */ 176#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 177 178#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 179#ifdef CONFIG_SYS_HUSH_PARSER 180#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 181#endif 182 183#if defined(CONFIG_CMD_KGDB) 184#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 185#else 186#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 187#endif 188#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 189#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 190#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 191 192#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 193#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 194 195/* 196 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1. 197 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31. 198 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value. 199 * The Linux BASE_BAUD define should match this configuration. 200 * baseBaud = cpuClock/(uartDivisor*16) 201 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, 202 * set Linux BASE_BAUD to 403200. 203 */ 204#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ 205#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ 206#define CONFIG_SYS_BASE_BAUD 691200 207 208/* The following table includes the supported baudrates */ 209#define CONFIG_SYS_BAUDRATE_TABLE \ 210 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} 211 212#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 213#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ 214 215#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 216 217#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ 218#undef CONFIG_SOFT_I2C /* I2C bit-banged */ 219#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */ 220#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 221#define CONFIG_SYS_I2C_SLAVE 0x7F 222 223 224/*----------------------------------------------------------------------- 225 * PCI stuff 226 *----------------------------------------------------------------------- 227 */ 228#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ 229#define PCI_HOST_FORCE 1 /* configure as pci host */ 230#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ 231 232#define CONFIG_PCI /* include pci support */ 233#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ 234#undef CONFIG_PCI_PNP /* do pci plug-and-play */ 235 /* resource configuration */ 236 237#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ 238#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ 239#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ 240#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ 241#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ 242#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ 243#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ 244#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ 245 246/*----------------------------------------------------------------------- 247 * External peripheral base address 248 *----------------------------------------------------------------------- 249 */ 250#undef CONFIG_IDE_LED /* no led for ide supported */ 251#undef CONFIG_IDE_RESET /* no reset for ide supported */ 252 253#define CONFIG_SYS_KEY_REG_BASE_ADDR 0xF0100000 254#define CONFIG_SYS_IR_REG_BASE_ADDR 0xF0200000 255#define CONFIG_SYS_FPGA_REG_BASE_ADDR 0xF0300000 256 257/*----------------------------------------------------------------------- 258 * Start addresses for the final memory configuration 259 * (Set up by the startup code) 260 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 261 */ 262#define CONFIG_SYS_SDRAM_BASE 0x00000000 263#define CONFIG_SYS_FLASH_BASE 0xFFF80000 264#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 265#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ 266#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ 267 268/* 269 * For booting Linux, the board info and command line data 270 * have to be in the first 8 MB of memory, since this is 271 * the maximum mapped by the Linux kernel during initialization. 272 */ 273#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 274 275/*----------------------------------------------------------------------- 276 * FLASH organization 277 */ 278#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 279#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 280 281#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 282#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 283 284/* 285 * Init Memory Controller: 286 * 287 * BR0/1 and OR0/1 (FLASH) 288 */ 289 290#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ 291#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ 292 293 294/* Configuration Port location */ 295#define CONFIG_PORT_ADDR 0xF0000500 296 297#if defined(CONFIG_CMD_KGDB) 298#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 299#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 300#endif 301#endif /* __CONFIG_H */ 302