1/* 2 * (C) Copyright 2001 3 * Frank Gottschling, ELTEC Elektronik AG, fgottschling@eltec.de 4 * 5 * (C) Copyright 2001 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7 * 8 * Configuation settings for the miniHiPerCam. 9 * 10 * ----------------------------------------------------------------- 11 * See file CREDITS for list of people who contributed to this 12 * project. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27 * MA 02111-1307 USA 28 */ 29 30/* 31 * board/config.h - configuration options, board specific 32 */ 33 34#ifndef __CONFIG_H 35#define __CONFIG_H 36 37/* 38 * High Level Configuration Options 39 * (easy to change) 40 */ 41#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ 42#define CONFIG_MHPC 1 /* on a miniHiPerCam */ 43#define CONFIG_BOARD_EARLY_INIT_F 1 /* do special hardware init. */ 44#define CONFIG_MISC_INIT_R 1 45 46#define CONFIG_SYS_TEXT_BASE 0xfe000000 47 48#define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED 49#undef CONFIG_8xx_CONS_SMC1 50#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ 51#undef CONFIG_8xx_CONS_NONE 52#define CONFIG_BAUDRATE 9600 53#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 54 55#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ 56 57#define CONFIG_ENV_OVERWRITE 1 58#define CONFIG_ETHADDR 00:00:5b:ee:de:ad 59 60#undef CONFIG_BOOTARGS 61#define CONFIG_BOOTCOMMAND \ 62 "bootp;" \ 63 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ 64 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ 65 "bootm" 66 67#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 68#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 69 70#undef CONFIG_WATCHDOG /* watchdog disabled */ 71#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 72 73#undef CONFIG_UCODE_PATCH 74 75/* enable I2C and select the hardware/software driver */ 76#undef CONFIG_HARD_I2C /* I2C with hardware support */ 77#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ 78/* 79 * Software (bit-bang) I2C driver configuration 80 */ 81#define PB_SCL 0x00000020 /* PB 26 */ 82#define PB_SDA 0x00000010 /* PB 27 */ 83 84#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) 85#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) 86#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) 87#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) 88#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ 89 else immr->im_cpm.cp_pbdat &= ~PB_SDA 90#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ 91 else immr->im_cpm.cp_pbdat &= ~PB_SCL 92#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ 93 94#define CONFIG_SYS_I2C_SPEED 50000 95#define CONFIG_SYS_I2C_SLAVE 0xFE 96#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C04 */ 97#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ 98/* mask of address bits that overflow into the "EEPROM chip address" */ 99#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 100#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 101#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 102 103#define LCD_VIDEO_ADDR (SDRAM_MAX_SIZE-SDRAM_RES_SIZE) 104#define LCD_VIDEO_SIZE SDRAM_RES_SIZE /* 2MB */ 105#define LCD_VIDEO_COLS 640 106#define LCD_VIDEO_ROWS 480 107#define LCD_VIDEO_FG 255 108#define LCD_VIDEO_BG 0 109 110#undef CONFIG_VIDEO /* test only ! s.a devices.c and 8xx */ 111#define CONFIG_CFB_CONSOLE /* framebuffer console with std input */ 112#define CONFIG_VIDEO_LOGO 113 114#define VIDEO_KBD_INIT_FCT 0 /* no KBD dev on MHPC - use serial */ 115#define VIDEO_TSTC_FCT serial_tstc 116#define VIDEO_GETC_FCT serial_getc 117 118#define CONFIG_BR0_WORKAROUND 1 119 120 121/* 122 * Command line configuration. 123 */ 124#include <config_cmd_default.h> 125 126#define CONFIG_CMD_DATE 127#define CONFIG_CMD_EEPROM 128#define CONFIG_CMD_ELF 129#define CONFIG_CMD_I2C 130#define CONFIG_CMD_JFFS2 131#define CONFIG_CMD_REGINFO 132 133 134/* 135 * BOOTP options 136 */ 137#define CONFIG_BOOTP_SUBNETMASK 138#define CONFIG_BOOTP_GATEWAY 139#define CONFIG_BOOTP_HOSTNAME 140#define CONFIG_BOOTP_BOOTPATH 141#define CONFIG_BOOTP_BOOTFILESIZE 142 143 144/* 145 * Miscellaneous configurable options 146 */ 147#define CONFIG_SYS_LONGHELP /* undef to save memory */ 148#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 149#if defined(CONFIG_CMD_KGDB) 150#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 151#else 152#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 153#endif 154#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 155#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 156#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 157 158#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 159#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 160 161#define CONFIG_SYS_LOAD_ADDR 0x300000 /* default load address */ 162 163#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 164 165#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 166 167/* 168 * Low Level Configuration Settings 169 * (address mappings, register initial values, etc.) 170 * You should know what you are doing if you make changes here. 171 */ 172 173/*----------------------------------------------------------------------- 174 * Physical memory map 175 */ 176#define CONFIG_SYS_IMMR 0xFFF00000 /* Internal Memory Mapped Register*/ 177 178/*----------------------------------------------------------------------- 179 * Definitions for initial stack pointer and data area (in DPRAM) 180 */ 181#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 182#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 183#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 184#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 185 186/*----------------------------------------------------------------------- 187 * Start addresses for the final memory configuration 188 * (Set up by the startup code) 189 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 190 */ 191#define CONFIG_SYS_SDRAM_BASE 0x00000000 192#define CONFIG_SYS_FLASH_BASE 0xfe000000 193 194#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */ 195#undef CONFIG_SYS_MONITOR_BASE /* to run U-Boot from RAM */ 196#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 197#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 198 199/* 200 * JFFS2 partitions 201 * 202 */ 203/* No command line, one static partition, whole device */ 204#undef CONFIG_CMD_MTDPARTS 205#define CONFIG_JFFS2_DEV "nor0" 206#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF 207#define CONFIG_JFFS2_PART_OFFSET 0x00000000 208 209/* mtdparts command line support */ 210/* Note: fake mtd_id used, no linux mtd map file */ 211/* 212#define CONFIG_CMD_MTDPARTS 213#define MTDIDS_DEFAULT "nor0=mhpc-0" 214#define MTDPARTS_DEFAULT "mtdparts=mhpc-0:-(jffs2)" 215*/ 216 217/* 218 * For booting Linux, the board info and command line data 219 * have to be in the first 8 MB of memory, since this is 220 * the maximum mapped by the Linux kernel during initialization. 221 */ 222#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map- for Linux */ 223 224/*----------------------------------------------------------------------- 225 * FLASH organization 226 */ 227#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 228#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ 229 230#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 231#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 232#define CONFIG_ENV_IS_IN_FLASH 1 233#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN /* Offset of Environment */ 234#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment */ 235 236/*----------------------------------------------------------------------- 237 * Cache Configuration 238 */ 239#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 240#if defined(CONFIG_CMD_KGDB) 241#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 242#endif 243 244/*----------------------------------------------------------------------- 245 * SYPCR - System Protection Control 11-9 246 * SYPCR can only be written once after reset! 247 *----------------------------------------------------------------------- 248 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 249 */ 250#if defined(CONFIG_WATCHDOG) 251#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 252 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 253#else 254#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 255 SYPCR_SWP) 256#endif 257 258/*----------------------------------------------------------------------- 259 * SIUMCR - SIU Module Configuration 11-6 260 *----------------------------------------------------------------------- 261 * PCMCIA config., multi-function pin tri-state 262 */ 263#define CONFIG_SYS_SIUMCR (SIUMCR_SEME) 264 265/*----------------------------------------------------------------------- 266 * TBSCR - Time Base Status and Control 11-26 267 *----------------------------------------------------------------------- 268 * Clear Reference Interrupt Status, Timebase freezing enabled 269 */ 270#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) 271 272/*----------------------------------------------------------------------- 273 * PISCR - Periodic Interrupt Status and Control 11-31 274 *----------------------------------------------------------------------- 275 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 276 */ 277#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE) 278 279/*----------------------------------------------------------------------- 280 * RTCSC - Real-Time Clock Status and Control Register 12-18 281 *----------------------------------------------------------------------- 282 */ 283#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 284 285/*----------------------------------------------------------------------- 286 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 287 *----------------------------------------------------------------------- 288 * Reset PLL lock status sticky bit, timer expired status bit and timer 289 * interrupt status bit - leave PLL multiplication factor unchanged ! 290 */ 291#define MPC8XX_SPEED 50000000L 292#define MPC8XX_XIN 5000000L /* ref clk */ 293#define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN) 294#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \ 295 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 296 297/*----------------------------------------------------------------------- 298 * SCCR - System Clock and reset Control Register 15-27 299 *----------------------------------------------------------------------- 300 * Set clock output, timebase and RTC source and divider, 301 * power management and some other internal clocks 302 */ 303 304#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) /* SCCR_EBDF11 */ 305#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_DFLCD001) 306 307 308/*----------------------------------------------------------------------- 309 * MAMR settings for SDRAM - 16-14 310 * => 0xC080200F 311 *----------------------------------------------------------------------- 312 * periodic timer for refresh 313 */ 314#define CONFIG_SYS_MAMR_PTA 0xC0 315#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_G0CLA_A11 | MAMR_TLFA_MSK) 316 317/* 318 * BR0 and OR0 (FLASH) used to re-map FLASH 319 */ 320 321/* allow for max 8 MB of Flash */ 322#define FLASH_BASE 0xFE000000 /* FLASH bank #0*/ 323#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0*/ 324#define CONFIG_SYS_REMAP_OR_AM 0xFF800000 /* OR addr mask */ 325#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ 326 327#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK) /* (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)*/ 328 329#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 330#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 331#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V ) 332 333/* 334 * BR1 and OR1 (SDRAM) 335 */ 336#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */ 337#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */ 338#define SDRAM_RES_SIZE 0x00200000 /* 2 MB for framebuffer */ 339 340/* SDRAM timing: drive GPL5 high on first cycle */ 341#define CONFIG_SYS_OR_TIMING_SDRAM (OR_G5LS) 342 343#define CONFIG_SYS_OR1_PRELIM ((~(SDRAM_MAX_SIZE)+1)| CONFIG_SYS_OR_TIMING_SDRAM ) 344#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 345 346/* 347 * BR2/OR2 - DIMM 348 */ 349#define CONFIG_SYS_OR2 (OR_ACS_DIV4) 350#define CONFIG_SYS_BR2 (BR_MS_UPMA) 351 352/* 353 * BR3/OR3 - DIMM 354 */ 355#define CONFIG_SYS_OR3 (OR_ACS_DIV4) 356#define CONFIG_SYS_BR3 (BR_MS_UPMA) 357 358/* 359 * BR4/OR4 360 */ 361#define CONFIG_SYS_OR4 0 362#define CONFIG_SYS_BR4 0 363 364/* 365 * BR5/OR5 366 */ 367#define CONFIG_SYS_OR5 0 368#define CONFIG_SYS_BR5 0 369 370/* 371 * BR6/OR6 372 */ 373#define CONFIG_SYS_OR6 0 374#define CONFIG_SYS_BR6 0 375 376/* 377 * BR7/OR7 378 */ 379#define CONFIG_SYS_OR7 0 380#define CONFIG_SYS_BR7 0 381 382 383/*----------------------------------------------------------------------- 384 * Debug Entry Mode 385 *----------------------------------------------------------------------- 386 * 387 */ 388#define CONFIG_SYS_DER 0 389 390#endif /* __CONFIG_H */ 391