1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22#ifndef __CONFIG_H
23#define __CONFIG_H
24
25
26
27
28#define CONFIG_E300 1
29#define CONFIG_MPC83xx 1
30#define CONFIG_MPC837x 1
31#define CONFIG_MPC837XERDB 1
32
33#define CONFIG_SYS_TEXT_BASE 0xFE000000
34
35#define CONFIG_PCI 1
36
37#define CONFIG_BOARD_EARLY_INIT_F
38#define CONFIG_MISC_INIT_R
39#define CONFIG_HWCONFIG
40
41
42
43
44#define CONFIG_TSEC_ENET
45#define CONFIG_VSC7385_ENET
46
47
48
49
50#ifdef CONFIG_PCISLAVE
51#define CONFIG_83XX_PCICLK 66666667
52#else
53#define CONFIG_83XX_CLKIN 66666667
54#define CONFIG_PCIE
55#endif
56
57#ifndef CONFIG_SYS_CLK_FREQ
58#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
59#endif
60
61
62
63
64#define CONFIG_SYS_HRCW_LOW (\
65 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
66 HRCWL_DDR_TO_SCB_CLK_1X1 |\
67 HRCWL_SVCOD_DIV_2 |\
68 HRCWL_CSB_TO_CLKIN_5X1 |\
69 HRCWL_CORE_TO_CSB_2X1)
70
71#ifdef CONFIG_PCISLAVE
72#define CONFIG_SYS_HRCW_HIGH (\
73 HRCWH_PCI_AGENT |\
74 HRCWH_PCI1_ARBITER_DISABLE |\
75 HRCWH_CORE_ENABLE |\
76 HRCWH_FROM_0XFFF00100 |\
77 HRCWH_BOOTSEQ_DISABLE |\
78 HRCWH_SW_WATCHDOG_DISABLE |\
79 HRCWH_ROM_LOC_LOCAL_16BIT |\
80 HRCWH_RL_EXT_LEGACY |\
81 HRCWH_TSEC1M_IN_RGMII |\
82 HRCWH_TSEC2M_IN_RGMII |\
83 HRCWH_BIG_ENDIAN |\
84 HRCWH_LDP_CLEAR)
85#else
86#define CONFIG_SYS_HRCW_HIGH (\
87 HRCWH_PCI_HOST |\
88 HRCWH_PCI1_ARBITER_ENABLE |\
89 HRCWH_CORE_ENABLE |\
90 HRCWH_FROM_0X00000100 |\
91 HRCWH_BOOTSEQ_DISABLE |\
92 HRCWH_SW_WATCHDOG_DISABLE |\
93 HRCWH_ROM_LOC_LOCAL_16BIT |\
94 HRCWH_RL_EXT_LEGACY |\
95 HRCWH_TSEC1M_IN_RGMII |\
96 HRCWH_TSEC2M_IN_RGMII |\
97 HRCWH_BIG_ENDIAN |\
98 HRCWH_LDP_CLEAR)
99#endif
100
101
102
103
104
105#define CONFIG_SYS_ACR_PIPE_DEP 3
106#define CONFIG_SYS_ACR_RPTCNT 3
107
108
109#define CONFIG_SYS_SPCR_TSECEP 3
110
111
112#define CONFIG_SYS_SCCR_TSEC1CM 1
113#define CONFIG_SYS_SCCR_TSEC2CM 1
114#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2
115
116
117
118
119#define CONFIG_SYS_SICRH 0x08200000
120#define CONFIG_SYS_SICRL 0x00000000
121
122
123
124
125#define CONFIG_SYS_OBIR 0x30100000
126
127
128
129
130#define CONFIG_SYS_IMMR 0xE0000000
131
132
133
134
135
136
137
138#ifdef CONFIG_VSC7385_ENET
139
140#define CONFIG_TSEC2
141
142
143#define CONFIG_VSC7385_IMAGE 0xFE7FE000
144#define CONFIG_VSC7385_IMAGE_SIZE 8192
145
146#endif
147
148
149
150
151#define CONFIG_SYS_DDR_BASE 0x00000000
152#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
153#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
154#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
155#define CONFIG_SYS_83XX_DDR_USES_CS0
156
157#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
158
159#undef CONFIG_DDR_ECC
160#undef CONFIG_DDR_ECC_CMD
161
162#undef CONFIG_NEVER_ASSERT_ODT_TO_CPU
163
164
165
166
167#define CONFIG_SYS_DDR_SIZE 256
168#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
169#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ODT_WR_ACS \
170 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
171
172#define CONFIG_SYS_DDR_TIMING_3 0x00000000
173#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
174 | (0 << TIMING_CFG0_WRT_SHIFT) \
175 | (0 << TIMING_CFG0_RRT_SHIFT) \
176 | (0 << TIMING_CFG0_WWT_SHIFT) \
177 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
178 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
179 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
180 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
181
182
183#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
184 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
185 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
186 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
187 | (13 << TIMING_CFG1_REFREC_SHIFT) \
188 | (3 << TIMING_CFG1_WRREC_SHIFT) \
189 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
190 | (2 << TIMING_CFG1_WRTORD_SHIFT))
191
192
193#define CONFIG_SYS_DDR_TIMING_2 0x02984cc8
194
195#define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
196 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
197
198
199#if defined(CONFIG_DDR_2T_TIMING)
200#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
201 | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
202 | SDRAM_CFG_2T_EN \
203 | SDRAM_CFG_DBW_32)
204#else
205#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
206 | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT)
207
208#endif
209#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000
210#define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
211 | (0x0442 << SDRAM_MODE_SD_SHIFT))
212
213#define CONFIG_SYS_DDR_MODE2 0x00000000
214
215
216
217
218#undef CONFIG_SYS_DRAM_TEST
219#define CONFIG_SYS_MEMTEST_START 0x00040000
220#define CONFIG_SYS_MEMTEST_END 0x0ef70010
221
222
223
224
225#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
226
227#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
228#define CONFIG_SYS_RAMBOOT
229#else
230#undef CONFIG_SYS_RAMBOOT
231#endif
232
233#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
234#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
235
236
237
238
239#define CONFIG_SYS_INIT_RAM_LOCK 1
240#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000
241#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
242#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
243
244
245
246
247#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
248#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
249#define CONFIG_SYS_LBC_LBCR 0x00000000
250#define CONFIG_FSL_ELBC 1
251
252
253
254
255#define CONFIG_SYS_FLASH_CFI
256#define CONFIG_FLASH_CFI_DRIVER
257#define CONFIG_SYS_FLASH_BASE 0xFE000000
258#define CONFIG_SYS_FLASH_SIZE 8
259
260#define CONFIG_SYS_FLASH_PROTECTION 1
261#define CONFIG_SYS_FLASH_EMPTY_INFO
262#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
263
264#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
265#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016
266
267#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
268 (2 << BR_PS_SHIFT) | \
269 BR_V)
270#define CONFIG_SYS_OR0_PRELIM (0xFF800000 \
271 | OR_GPCM_XACS \
272 | OR_GPCM_SCY_9 \
273 | OR_GPCM_EHTR \
274 | OR_GPCM_EAD)
275
276
277#define CONFIG_SYS_MAX_FLASH_BANKS 1
278#define CONFIG_SYS_MAX_FLASH_SECT 256
279
280#undef CONFIG_SYS_FLASH_CHECKSUM
281#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
282#define CONFIG_SYS_FLASH_WRITE_TOUT 500
283
284
285
286
287#define CONFIG_SYS_NAND_BASE 0xE0600000
288#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | \
289 (2 << BR_DECC_SHIFT) | \
290 BR_PS_8 | \
291 BR_MS_FCM | \
292 BR_V)
293#define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 | \
294 OR_FCM_CSCT | \
295 OR_FCM_CST | \
296 OR_FCM_CHT | \
297 OR_FCM_SCY_1 | \
298 OR_FCM_TRLX | \
299 OR_FCM_EHTR)
300#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
301#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E
302
303
304
305#define CONFIG_SYS_VSC7385_BASE 0xF0000000
306
307#ifdef CONFIG_VSC7385_ENET
308
309#define CONFIG_SYS_BR2_PRELIM 0xf0000801
310#define CONFIG_SYS_OR2_PRELIM 0xfffe09ff
311#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
312#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010
313
314#endif
315
316
317
318
319#define CONFIG_CONS_INDEX 1
320#define CONFIG_SYS_NS16550
321#define CONFIG_SYS_NS16550_SERIAL
322#define CONFIG_SYS_NS16550_REG_SIZE 1
323#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
324
325#define CONFIG_SYS_BAUDRATE_TABLE \
326 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
327
328#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
329#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
330
331
332#define CONFIG_FSL_SERDES
333#define CONFIG_FSL_SERDES1 0xe3000
334#define CONFIG_FSL_SERDES2 0xe3100
335
336
337#define CONFIG_SYS_HUSH_PARSER
338#ifdef CONFIG_SYS_HUSH_PARSER
339#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
340#endif
341
342
343#define CONFIG_OF_LIBFDT 1
344#define CONFIG_OF_BOARD_SETUP 1
345#define CONFIG_OF_STDOUT_VIA_ALIAS 1
346
347
348#define CONFIG_HARD_I2C
349#undef CONFIG_SOFT_I2C
350#define CONFIG_FSL_I2C
351#define CONFIG_SYS_I2C_SPEED 400000
352#define CONFIG_SYS_I2C_SLAVE 0x7F
353#define CONFIG_SYS_I2C_NOPROBES {0x51}
354#define CONFIG_SYS_I2C_OFFSET 0x3000
355#define CONFIG_SYS_I2C2_OFFSET 0x3100
356
357
358
359
360#define CONFIG_RTC_DS1374
361#define CONFIG_SYS_I2C_RTC_ADDR 0x68
362
363
364
365
366
367#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
368#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
369#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
370#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
371#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
372#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000
373#define CONFIG_SYS_PCI_IO_BASE 0x00000000
374#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
375#define CONFIG_SYS_PCI_IO_SIZE 0x100000
376
377#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
378#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
379#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
380
381#define CONFIG_SYS_PCIE1_BASE 0xA0000000
382#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
383#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
384#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
385#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
386#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
387#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
388#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
389#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
390
391#define CONFIG_SYS_PCIE2_BASE 0xC0000000
392#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
393#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
394#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
395#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
396#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
397#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
398#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
399#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
400
401#ifdef CONFIG_PCI
402#define CONFIG_NET_MULTI
403#define CONFIG_PCI_PNP
404
405#undef CONFIG_PCI_SCAN_SHOW
406#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957
407#endif
408
409
410
411
412#ifdef CONFIG_TSEC_ENET
413
414#define CONFIG_NET_MULTI
415#define CONFIG_GMII
416
417#define CONFIG_TSEC1
418
419#ifdef CONFIG_TSEC1
420#define CONFIG_HAS_ETH0
421#define CONFIG_TSEC1_NAME "TSEC0"
422#define CONFIG_SYS_TSEC1_OFFSET 0x24000
423#define TSEC1_PHY_ADDR 2
424#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
425#define TSEC1_PHYIDX 0
426#endif
427
428#ifdef CONFIG_TSEC2
429#define CONFIG_HAS_ETH1
430#define CONFIG_TSEC2_NAME "TSEC1"
431#define CONFIG_SYS_TSEC2_OFFSET 0x25000
432#define TSEC2_PHY_ADDR 0x1c
433#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
434#define TSEC2_PHYIDX 0
435#endif
436
437
438#define CONFIG_ETHPRIME "TSEC0"
439
440#endif
441
442
443
444
445#define CONFIG_LIBATA
446#define CONFIG_FSL_SATA
447
448#define CONFIG_SYS_SATA_MAX_DEVICE 2
449#define CONFIG_SATA1
450#define CONFIG_SYS_SATA1_OFFSET 0x18000
451#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
452#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
453#define CONFIG_SATA2
454#define CONFIG_SYS_SATA2_OFFSET 0x19000
455#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
456#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
457
458#ifdef CONFIG_FSL_SATA
459#define CONFIG_LBA48
460#define CONFIG_CMD_SATA
461#define CONFIG_DOS_PARTITION
462#define CONFIG_CMD_EXT2
463#endif
464
465
466
467
468#ifndef CONFIG_SYS_RAMBOOT
469 #define CONFIG_ENV_IS_IN_FLASH 1
470 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
471 #define CONFIG_ENV_SECT_SIZE 0x10000
472 #define CONFIG_ENV_SIZE 0x4000
473#else
474 #define CONFIG_SYS_NO_FLASH 1
475 #define CONFIG_ENV_IS_NOWHERE 1
476 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000)
477 #define CONFIG_ENV_SIZE 0x2000
478#endif
479
480#define CONFIG_LOADS_ECHO 1
481#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
482
483
484
485
486#define CONFIG_BOOTP_BOOTFILESIZE
487#define CONFIG_BOOTP_BOOTPATH
488#define CONFIG_BOOTP_GATEWAY
489#define CONFIG_BOOTP_HOSTNAME
490
491
492
493
494
495#include <config_cmd_default.h>
496
497#define CONFIG_CMD_PING
498#define CONFIG_CMD_I2C
499#define CONFIG_CMD_MII
500#define CONFIG_CMD_DATE
501
502#if defined(CONFIG_PCI)
503#define CONFIG_CMD_PCI
504#endif
505
506#if defined(CONFIG_SYS_RAMBOOT)
507#undef CONFIG_CMD_SAVEENV
508#undef CONFIG_CMD_LOADS
509#endif
510
511#define CONFIG_CMDLINE_EDITING 1
512#define CONFIG_AUTO_COMPLETE
513
514#undef CONFIG_WATCHDOG
515
516#define CONFIG_MMC 1
517
518#ifdef CONFIG_MMC
519#define CONFIG_FSL_ESDHC
520#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
521#define CONFIG_CMD_MMC
522#define CONFIG_GENERIC_MMC
523#define CONFIG_CMD_EXT2
524#define CONFIG_CMD_FAT
525#define CONFIG_DOS_PARTITION
526#endif
527
528
529
530
531#define CONFIG_SYS_LONGHELP
532#define CONFIG_SYS_LOAD_ADDR 0x2000000
533#define CONFIG_SYS_PROMPT "=> "
534
535#if defined(CONFIG_CMD_KGDB)
536 #define CONFIG_SYS_CBSIZE 1024
537#else
538 #define CONFIG_SYS_CBSIZE 256
539#endif
540
541#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
542#define CONFIG_SYS_MAXARGS 16
543#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
544#define CONFIG_SYS_HZ 1000
545
546
547
548
549
550
551#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
552
553
554
555
556#define CONFIG_SYS_HID0_INIT 0x000000000
557#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
558 HID0_ENABLE_INSTRUCTION_CACHE)
559#define CONFIG_SYS_HID2 HID2_HBE
560
561
562
563
564
565#define CONFIG_HIGH_BATS 1
566
567
568#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
569#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
570
571#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE)
572#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP)
573#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
574#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
575
576#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE)
577#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP)
578#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
579#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
580
581
582#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_10 | \
583 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
584#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
585#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
586#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
587
588
589#define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE | BATL_PP_10 | \
590 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
591#define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE | BATU_BL_128K | BATU_VS | BATU_VP)
592#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
593#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
594
595
596#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
597#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
598#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
599 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
600#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
601
602
603#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
604#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
605#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
606#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
607
608#ifdef CONFIG_PCI
609
610#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
611#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
612#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
613#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
614
615#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
616 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
617#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
618#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
619#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
620#else
621#define CONFIG_SYS_IBAT6L (0)
622#define CONFIG_SYS_IBAT6U (0)
623#define CONFIG_SYS_IBAT7L (0)
624#define CONFIG_SYS_IBAT7U (0)
625#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
626#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
627#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
628#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
629#endif
630
631#if defined(CONFIG_CMD_KGDB)
632#define CONFIG_KGDB_BAUDRATE 230400
633#define CONFIG_KGDB_SER_INDEX 2
634#endif
635
636
637
638
639#define CONFIG_ENV_OVERWRITE
640
641#define CONFIG_HAS_FSL_DR_USB
642
643#define CONFIG_NETDEV eth1
644
645#define CONFIG_HOSTNAME mpc837x_rdb
646#define CONFIG_ROOTPATH /nfsroot
647#define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot
648#define CONFIG_BOOTFILE uImage
649#define CONFIG_UBOOTPATH u-boot.bin
650#define CONFIG_FDTFILE mpc8379_rdb.dtb
651
652#define CONFIG_LOADADDR 800000
653#define CONFIG_BOOTDELAY 6
654#define CONFIG_BAUDRATE 115200
655
656#define XMK_STR(x) #x
657#define MK_STR(x) XMK_STR(x)
658
659#define CONFIG_EXTRA_ENV_SETTINGS \
660 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
661 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
662 "tftpflash=tftp $loadaddr $uboot;" \
663 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
664 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
665 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
666 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
667 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
668 "fdtaddr=780000\0" \
669 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
670 "ramdiskaddr=1000000\0" \
671 "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \
672 "console=ttyS0\0" \
673 "setbootargs=setenv bootargs " \
674 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
675 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
676 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
677 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
678
679#define CONFIG_NFSBOOTCOMMAND \
680 "setenv rootdev /dev/nfs;" \
681 "run setbootargs;" \
682 "run setipargs;" \
683 "tftp $loadaddr $bootfile;" \
684 "tftp $fdtaddr $fdtfile;" \
685 "bootm $loadaddr - $fdtaddr"
686
687#define CONFIG_RAMBOOTCOMMAND \
688 "setenv rootdev /dev/ram;" \
689 "run setbootargs;" \
690 "tftp $ramdiskaddr $ramdiskfile;" \
691 "tftp $loadaddr $bootfile;" \
692 "tftp $fdtaddr $fdtfile;" \
693 "bootm $loadaddr $ramdiskaddr $fdtaddr"
694
695#undef MK_STR
696#undef XMK_STR
697
698#endif
699