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33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37
38#define CONFIG_BOOKE 1
39#define CONFIG_E500 1
40#define CONFIG_MPC85xx 1
41#define CONFIG_MPC8540 1
42#define CONFIG_MPC8540ADS 1
43
44
45
46
47
48#define CONFIG_SYS_TEXT_BASE 0xfff80000
49
50#ifndef CONFIG_HAS_FEC
51#define CONFIG_HAS_FEC 1
52#endif
53
54#define CONFIG_PCI
55#define CONFIG_SYS_PCI_64BIT 1
56#define CONFIG_TSEC_ENET
57#define CONFIG_ENV_OVERWRITE
58#define CONFIG_FSL_LAW 1
59
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76
77
78#ifndef CONFIG_SYS_CLK_FREQ
79#define CONFIG_SYS_CLK_FREQ 33000000
80#endif
81
82
83
84
85
86#define CONFIG_L2_CACHE
87#define CONFIG_BTB
88
89#define CONFIG_SYS_MEMTEST_START 0x00200000
90#define CONFIG_SYS_MEMTEST_END 0x00400000
91
92
93
94
95
96
97#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
98#define CONFIG_SYS_CCSRBAR 0xe0000000
99#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
100#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
101
102
103#define CONFIG_FSL_DDR1
104#define CONFIG_SPD_EEPROM
105#define CONFIG_DDR_SPD
106#undef CONFIG_FSL_DDR_INTERACTIVE
107
108#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
109
110#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
111#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
112
113#define CONFIG_NUM_DDR_CONTROLLERS 1
114#define CONFIG_DIMM_SLOTS_PER_CTLR 1
115#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
116
117
118#define SPD_EEPROM_ADDRESS 0x51
119
120
121#define CONFIG_SYS_SDRAM_SIZE 128
122#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
123#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
124#define CONFIG_SYS_DDR_TIMING_1 0x37344321
125#define CONFIG_SYS_DDR_TIMING_2 0x00000800
126#define CONFIG_SYS_DDR_CONTROL 0xc2000000
127#define CONFIG_SYS_DDR_MODE 0x00000062
128#define CONFIG_SYS_DDR_INTERVAL 0x05200100
129
130
131
132
133#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000
134#define CONFIG_SYS_LBC_SDRAM_SIZE 64
135
136#define CONFIG_SYS_FLASH_BASE 0xff000000
137#define CONFIG_SYS_BR0_PRELIM 0xff001801
138
139#define CONFIG_SYS_OR0_PRELIM 0xff006ff7
140#define CONFIG_SYS_MAX_FLASH_BANKS 1
141#define CONFIG_SYS_MAX_FLASH_SECT 64
142#undef CONFIG_SYS_FLASH_CHECKSUM
143#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
144#define CONFIG_SYS_FLASH_WRITE_TOUT 500
145
146#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
147
148#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
149#define CONFIG_SYS_RAMBOOT
150#else
151#undef CONFIG_SYS_RAMBOOT
152#endif
153
154#define CONFIG_FLASH_CFI_DRIVER
155#define CONFIG_SYS_FLASH_CFI
156#define CONFIG_SYS_FLASH_EMPTY_INFO
157
158#undef CONFIG_CLOCKS_IN_MHZ
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182
183#define CONFIG_SYS_BR2_PRELIM 0xf0001861
184
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197
198
199#define CONFIG_SYS_OR2_PRELIM 0xfc006901
200
201#define CONFIG_SYS_LBC_LCRR 0x00030004
202#define CONFIG_SYS_LBC_LBCR 0x00000000
203#define CONFIG_SYS_LBC_LSRT 0x20000000
204#define CONFIG_SYS_LBC_MRTPR 0x20000000
205
206#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
207 | LSDMR_RFCR5 \
208 | LSDMR_PRETOACT3 \
209 | LSDMR_ACTTORW3 \
210 | LSDMR_BL8 \
211 | LSDMR_WRC2 \
212 | LSDMR_CL3 \
213 | LSDMR_RFEN \
214 )
215
216
217
218
219#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
220#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
221#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
222#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
223#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
224
225
226
227
228
229#define CONFIG_SYS_BR4_PRELIM 0xf8000801
230#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
231#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
232
233#define CONFIG_SYS_INIT_RAM_LOCK 1
234#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000
235#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
236
237#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
238#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
239
240#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
241#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
242
243
244#define CONFIG_CONS_INDEX 1
245#define CONFIG_SYS_NS16550
246#define CONFIG_SYS_NS16550_SERIAL
247#define CONFIG_SYS_NS16550_REG_SIZE 1
248#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
249
250#define CONFIG_SYS_BAUDRATE_TABLE \
251 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
252
253#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
254#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
255
256
257#define CONFIG_SYS_HUSH_PARSER
258#ifdef CONFIG_SYS_HUSH_PARSER
259#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
260#endif
261
262
263#define CONFIG_OF_LIBFDT 1
264#define CONFIG_OF_BOARD_SETUP 1
265#define CONFIG_OF_STDOUT_VIA_ALIAS 1
266
267
268
269
270#define CONFIG_FSL_I2C
271#define CONFIG_HARD_I2C
272#undef CONFIG_SOFT_I2C
273#define CONFIG_SYS_I2C_SPEED 400000
274#define CONFIG_SYS_I2C_SLAVE 0x7F
275#define CONFIG_SYS_I2C_NOPROBES {0x69}
276#define CONFIG_SYS_I2C_OFFSET 0x3000
277
278
279#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000
280#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000
281#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
282#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000
283
284
285
286
287
288#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
289#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
290#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
291#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000
292#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
293#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
294#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
295#define CONFIG_SYS_PCI1_IO_SIZE 0x100000
296
297#if defined(CONFIG_PCI)
298
299#define CONFIG_NET_MULTI
300#define CONFIG_PCI_PNP
301
302#undef CONFIG_EEPRO100
303#undef CONFIG_TULIP
304
305#if !defined(CONFIG_PCI_PNP)
306 #define PCI_ENET0_IOADDR 0xe0000000
307 #define PCI_ENET0_MEMADDR 0xe0000000
308 #define PCI_IDSEL_NUMBER 0x0c
309#endif
310
311#undef CONFIG_PCI_SCAN_SHOW
312#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057
313
314#endif
315
316
317#if defined(CONFIG_TSEC_ENET)
318
319#ifndef CONFIG_NET_MULTI
320#define CONFIG_NET_MULTI 1
321#endif
322
323#define CONFIG_MII 1
324#define CONFIG_TSEC1 1
325#define CONFIG_TSEC1_NAME "TSEC0"
326#define CONFIG_TSEC2 1
327#define CONFIG_TSEC2_NAME "TSEC1"
328#define TSEC1_PHY_ADDR 0
329#define TSEC2_PHY_ADDR 1
330#define TSEC1_PHYIDX 0
331#define TSEC2_PHYIDX 0
332#define TSEC1_FLAGS TSEC_GIGABIT
333#define TSEC2_FLAGS TSEC_GIGABIT
334
335
336#if CONFIG_HAS_FEC
337#define CONFIG_MPC85XX_FEC 1
338#define CONFIG_MPC85XX_FEC_NAME "FEC"
339#define FEC_PHY_ADDR 3
340#define FEC_PHYIDX 0
341#define FEC_FLAGS 0
342#endif
343
344
345#define CONFIG_ETHPRIME "TSEC0"
346
347#endif
348
349
350
351
352
353#ifndef CONFIG_SYS_RAMBOOT
354 #define CONFIG_ENV_IS_IN_FLASH 1
355 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
356 #define CONFIG_ENV_SECT_SIZE 0x40000
357 #define CONFIG_ENV_SIZE 0x2000
358#else
359 #define CONFIG_SYS_NO_FLASH 1
360 #define CONFIG_ENV_IS_NOWHERE 1
361 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
362 #define CONFIG_ENV_SIZE 0x2000
363#endif
364
365#define CONFIG_LOADS_ECHO 1
366#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
367
368
369
370
371
372#define CONFIG_BOOTP_BOOTFILESIZE
373#define CONFIG_BOOTP_BOOTPATH
374#define CONFIG_BOOTP_GATEWAY
375#define CONFIG_BOOTP_HOSTNAME
376
377
378
379
380
381#include <config_cmd_default.h>
382
383#define CONFIG_CMD_PING
384#define CONFIG_CMD_I2C
385#define CONFIG_CMD_ELF
386#define CONFIG_CMD_IRQ
387#define CONFIG_CMD_SETEXPR
388
389#if defined(CONFIG_PCI)
390 #define CONFIG_CMD_PCI
391#endif
392
393#if defined(CONFIG_SYS_RAMBOOT)
394 #undef CONFIG_CMD_SAVEENV
395 #undef CONFIG_CMD_LOADS
396#endif
397
398
399#undef CONFIG_WATCHDOG
400
401
402
403
404#define CONFIG_SYS_LONGHELP
405#define CONFIG_CMDLINE_EDITING
406#define CONFIG_AUTO_COMPLETE
407#define CONFIG_SYS_LOAD_ADDR 0x2000000
408#define CONFIG_SYS_PROMPT "=> "
409
410#if defined(CONFIG_CMD_KGDB)
411 #define CONFIG_SYS_CBSIZE 1024
412#else
413 #define CONFIG_SYS_CBSIZE 256
414#endif
415
416#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
417#define CONFIG_SYS_MAXARGS 16
418#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
419#define CONFIG_SYS_HZ 1000
420
421
422
423
424
425
426#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
427
428#if defined(CONFIG_CMD_KGDB)
429#define CONFIG_KGDB_BAUDRATE 230400
430#define CONFIG_KGDB_SER_INDEX 2
431#endif
432
433
434
435
436
437
438
439#if defined(CONFIG_TSEC_ENET)
440#define CONFIG_HAS_ETH0
441#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
442#define CONFIG_HAS_ETH1
443#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
444#define CONFIG_HAS_ETH2
445#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
446#endif
447
448#define CONFIG_IPADDR 192.168.1.253
449
450#define CONFIG_HOSTNAME unknown
451#define CONFIG_ROOTPATH /nfsroot
452#define CONFIG_BOOTFILE your.uImage
453
454#define CONFIG_SERVERIP 192.168.1.1
455#define CONFIG_GATEWAYIP 192.168.1.1
456#define CONFIG_NETMASK 255.255.255.0
457
458#define CONFIG_LOADADDR 200000
459
460#define CONFIG_BOOTDELAY 10
461#undef CONFIG_BOOTARGS
462
463#define CONFIG_BAUDRATE 115200
464
465#define CONFIG_EXTRA_ENV_SETTINGS \
466 "netdev=eth0\0" \
467 "consoledev=ttyS0\0" \
468 "ramdiskaddr=1000000\0" \
469 "ramdiskfile=your.ramdisk.u-boot\0" \
470 "fdtaddr=400000\0" \
471 "fdtfile=your.fdt.dtb\0"
472
473#define CONFIG_NFSBOOTCOMMAND \
474 "setenv bootargs root=/dev/nfs rw " \
475 "nfsroot=$serverip:$rootpath " \
476 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
477 "console=$consoledev,$baudrate $othbootargs;" \
478 "tftp $loadaddr $bootfile;" \
479 "tftp $fdtaddr $fdtfile;" \
480 "bootm $loadaddr - $fdtaddr"
481
482#define CONFIG_RAMBOOTCOMMAND \
483 "setenv bootargs root=/dev/ram rw " \
484 "console=$consoledev,$baudrate $othbootargs;" \
485 "tftp $ramdiskaddr $ramdiskfile;" \
486 "tftp $loadaddr $bootfile;" \
487 "tftp $fdtaddr $fdtfile;" \
488 "bootm $loadaddr $ramdiskaddr $fdtaddr"
489
490#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
491
492#endif
493