1/* 2 * (C) Copyright 2002-2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * 26 * Configuration settings for the PCIPPC-2 board. 27 * 28 */ 29 30/* ------------------------------------------------------------------------- */ 31 32/* 33 * board/config.h - configuration options, board specific 34 */ 35 36#ifndef __CONFIG_H 37#define __CONFIG_H 38 39/* 40 * High Level Configuration Options 41 * (easy to change) 42 */ 43 44#define CONFIG_PCIPPC2 1 /* this is a PCIPPC2 board */ 45 46#define CONFIG_SYS_TEXT_BASE 0xfff00000 47 48#define CONFIG_BOARD_EARLY_INIT_F 1 49#define CONFIG_MISC_INIT_R 1 50 51#define CONFIG_CONS_INDEX 1 52#define CONFIG_BAUDRATE 9600 53#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 54 55#define CONFIG_PREBOOT "" 56#define CONFIG_BOOTDELAY 5 57 58/* 59 * BOOTP options 60 */ 61#define CONFIG_BOOTP_SUBNETMASK 62#define CONFIG_BOOTP_GATEWAY 63#define CONFIG_BOOTP_HOSTNAME 64#define CONFIG_BOOTP_BOOTPATH 65#define CONFIG_BOOTP_BOOTFILESIZE 66 67#define CONFIG_MAC_PARTITION 68#define CONFIG_DOS_PARTITION 69 70 71/* 72 * Command line configuration. 73 */ 74#include <config_cmd_default.h> 75 76#define CONFIG_CMD_ASKENV 77#define CONFIG_CMD_BSP 78#define CONFIG_CMD_DATE 79#define CONFIG_CMD_DHCP 80#define CONFIG_CMD_ELF 81#define CONFIG_CMD_NFS 82#define CONFIG_CMD_PCI 83#define CONFIG_CMD_SNTP 84 85#define CONFIG_PCI 1 86#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ 87 88/* 89 * Miscellaneous configurable options 90 */ 91#define CONFIG_SYS_LONGHELP /* undef to save memory */ 92#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 93 94#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ 95#ifdef CONFIG_SYS_HUSH_PARSER 96#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 97#endif 98#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 99 100/* Print Buffer Size 101 */ 102#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 103 104#define CONFIG_SYS_MAXARGS 64 /* max number of command args */ 105#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 106#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ 107 108/*----------------------------------------------------------------------- 109 * Start addresses for the final memory configuration 110 * (Set up by the startup code) 111 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 112 */ 113#define CONFIG_SYS_SDRAM_BASE 0x00000000 114#define CONFIG_SYS_FLASH_BASE 0xFFF00000 115#define CONFIG_SYS_FLASH_MAX_SIZE 0x00100000 116/* Maximum amount of RAM. 117 */ 118#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 /* 512Mb */ 119 120#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 121 122#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 123 124#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 125#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 126 127#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_SDRAM_BASE && \ 128 CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE 129#define CONFIG_SYS_RAMBOOT 130#else 131#undef CONFIG_SYS_RAMBOOT 132#endif 133 134#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ 135#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ 136 137/*----------------------------------------------------------------------- 138 * Definitions for initial stack pointer and data area 139 */ 140 141/* Size in bytes reserved for initial data 142 */ 143 144#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 145#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 146#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 147#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 148 149#define CONFIG_SYS_INIT_RAM_LOCK 150 151/* 152 * Temporary buffer for serial data until the real serial driver 153 * is initialised (memtest will destroy this buffer) 154 */ 155#define CONFIG_SYS_SCONSOLE_ADDR CONFIG_SYS_INIT_RAM_ADDR 156#define CONFIG_SYS_SCONSOLE_SIZE 0x0002000 157 158/* SDRAM 0 - 256MB 159 */ 160#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 161#define CONFIG_SYS_DBAT0U (CONFIG_SYS_SDRAM_BASE | \ 162 BATU_BL_256M | BATU_VS | BATU_VP) 163/* SDRAM 1 - 256MB 164 */ 165#define CONFIG_SYS_DBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \ 166 BATL_PP_10 | BATL_MEMCOHERENCE) 167#define CONFIG_SYS_DBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \ 168 BATU_BL_256M | BATU_VS | BATU_VP) 169 170/* Init RAM in the CPU DCache (no backing memory) 171 */ 172#define CONFIG_SYS_DBAT2L (CONFIG_SYS_INIT_RAM_ADDR | \ 173 BATL_PP_10 | BATL_MEMCOHERENCE) 174#define CONFIG_SYS_DBAT2U (CONFIG_SYS_INIT_RAM_ADDR | \ 175 BATU_BL_128K | BATU_VS | BATU_VP) 176 177/* I/O and PCI memory at 0xf0000000 178 */ 179#define CONFIG_SYS_DBAT3L (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) 180#define CONFIG_SYS_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 181 182#define CONFIG_SYS_IBAT0L CONFIG_SYS_DBAT0L 183#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U 184#define CONFIG_SYS_IBAT1L CONFIG_SYS_DBAT1L 185#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U 186#define CONFIG_SYS_IBAT2L CONFIG_SYS_DBAT2L 187#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 188#define CONFIG_SYS_IBAT3L CONFIG_SYS_DBAT3L 189#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U 190 191/* 192 * Low Level Configuration Settings 193 * (address mappings, register initial values, etc.) 194 * You should know what you are doing if you make changes here. 195 * For the detail description refer to the PCIPPC2 user's manual. 196 */ 197#define CONFIG_SYS_HZ 1000 198#define CONFIG_SYS_BUS_CLK 100000000 /* bus speed - 100 mhz */ 199#define CONFIG_SYS_CPU_CLK 300000000 200 201/* 202 * For booting Linux, the board info and command line data 203 * have to be in the first 8 MB of memory, since this is 204 * the maximum mapped by the Linux kernel during initialization. 205 */ 206#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 207 208/*----------------------------------------------------------------------- 209 * FLASH organization 210 */ 211#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ 212#define CONFIG_SYS_MAX_FLASH_SECT 16 /* Max number of sectors in one bank */ 213 214#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 215#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ 216 217/* 218 * Note: environment is not EMBEDDED in the U-Boot code. 219 * It's stored in flash separately. 220 */ 221#define CONFIG_ENV_IS_IN_FLASH 1 222#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x70000) 223#define CONFIG_ENV_SIZE 0x1000 /* Size of the Environment */ 224#define CONFIG_ENV_SECT_SIZE 0x10000 /* Size of the Environment Sector */ 225 226/*----------------------------------------------------------------------- 227 * Cache Configuration 228 */ 229#define CONFIG_SYS_CACHELINE_SIZE 32 230#if defined(CONFIG_CMD_KGDB) 231# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 232#endif 233 234/* 235 * L2 cache 236 */ 237#undef CONFIG_SYS_L2 238#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ 239 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) 240#define L2_ENABLE (L2_INIT | L2CR_L2E) 241 242/*----------------------------------------------------------------------- 243 RTC m48t59 244*/ 245#define CONFIG_RTC_MK48T59 246 247#define CONFIG_WATCHDOG 248 249#define CONFIG_NET_MULTI /* Multi ethernet cards support */ 250 251#define CONFIG_EEPRO100 252#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ 253#define CONFIG_TULIP 254 255#endif /* __CONFIG_H */ 256