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33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37#define CONFIG_PPCHAMELEON_MODULE_BA 0
38#define CONFIG_PPCHAMELEON_MODULE_ME 1
39#define CONFIG_PPCHAMELEON_MODULE_HI 2
40#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
41#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
42#endif
43
44
45
46
47
48
49#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
50#define CONFIG_PPCHAMELEON_CLK_25
51#endif
52
53#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
54#error "* Two external frequencies (SysClk) are defined! *"
55#endif
56
57#undef CONFIG_PPCHAMELEON_SMI712
58
59
60
61
62#undef __DEBUG_START_FROM_SRAM__
63#define __DISABLE_MACHINE_EXCEPTION__
64
65#ifdef __DEBUG_START_FROM_SRAM__
66#define CONFIG_SYS_DUMMY_FLASH_SIZE 1024*1024*4
67#endif
68
69
70
71
72
73
74#define CONFIG_405EP 1
75#define CONFIG_4xx 1
76#define CONFIG_PPCHAMELEONEVB 1
77
78#define CONFIG_SYS_TEXT_BASE 0xFFFB0000
79#define CONFIG_SYS_LDSCRIPT "board/dave/PPChameleonEVB/u-boot.lds"
80
81#define CONFIG_BOARD_EARLY_INIT_F 1
82#define CONFIG_MISC_INIT_R 1
83
84
85#ifdef CONFIG_PPCHAMELEON_CLK_25
86# define CONFIG_SYS_CLK_FREQ 25000000
87#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
88# define CONFIG_SYS_CLK_FREQ 33333333
89#else
90# error "* External frequency (SysClk) not defined! *"
91#endif
92
93#define CONFIG_BAUDRATE 115200
94#define CONFIG_BOOTDELAY 5
95
96#undef CONFIG_BOOTARGS
97
98
99#define CONFIG_ENV_OVERWRITE
100#define CONFIG_ETHADDR 00:50:c2:1e:af:fe
101#define CONFIG_HAS_ETH1
102#define CONFIG_ETH1ADDR 00:50:c2:1e:af:fd
103
104#define CONFIG_LOADS_ECHO 1
105#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
106
107#undef CONFIG_EXT_PHY
108#define CONFIG_NET_MULTI 1
109
110#define CONFIG_PPC4xx_EMAC
111#define CONFIG_MII 1
112#ifndef CONFIG_EXT_PHY
113#define CONFIG_PHY_ADDR 1
114#define CONFIG_PHY1_ADDR 2
115#else
116#define CONFIG_PHY_ADDR 2
117#endif
118#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
119
120
121
122
123
124#define CONFIG_BOOTP_BOOTFILESIZE
125#define CONFIG_BOOTP_BOOTPATH
126#define CONFIG_BOOTP_GATEWAY
127#define CONFIG_BOOTP_HOSTNAME
128
129
130
131
132
133#include <config_cmd_default.h>
134
135#define CONFIG_CMD_DATE
136#define CONFIG_CMD_DHCP
137#define CONFIG_CMD_ELF
138#define CONFIG_CMD_EEPROM
139#define CONFIG_CMD_I2C
140#define CONFIG_CMD_IRQ
141#define CONFIG_CMD_JFFS2
142#define CONFIG_CMD_MII
143#define CONFIG_CMD_NAND
144#define CONFIG_CMD_NFS
145#define CONFIG_CMD_PCI
146#define CONFIG_CMD_SNTP
147
148
149#define CONFIG_MAC_PARTITION
150#define CONFIG_DOS_PARTITION
151
152#undef CONFIG_WATCHDOG
153
154#define CONFIG_RTC_M41T11 1
155#define CONFIG_SYS_I2C_RTC_ADDR 0x68
156#define CONFIG_SYS_M41T11_BASE_YEAR 1900
157
158
159
160
161#define CONFIG_SDRAM_BANK0 1
162
163
164#define CONFIG_SYS_SDRAM_CL 2
165#define CONFIG_SYS_SDRAM_tRP 20
166#define CONFIG_SYS_SDRAM_tRC 65
167#define CONFIG_SYS_SDRAM_tRCD 20
168#undef CONFIG_SYS_SDRAM_tRFC
169
170
171
172
173#define CONFIG_SYS_LONGHELP
174#define CONFIG_SYS_PROMPT "=> "
175
176#undef CONFIG_SYS_HUSH_PARSER
177#ifdef CONFIG_SYS_HUSH_PARSER
178#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
179#endif
180
181#if defined(CONFIG_CMD_KGDB)
182#define CONFIG_SYS_CBSIZE 1024
183#else
184#define CONFIG_SYS_CBSIZE 256
185#endif
186#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
187#define CONFIG_SYS_MAXARGS 16
188#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
189
190#define CONFIG_SYS_DEVICE_NULLDEV 1
191
192#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
193
194#define CONFIG_SYS_MEMTEST_START 0x0400000
195#define CONFIG_SYS_MEMTEST_END 0x0C00000
196
197#define CONFIG_CONS_INDEX 1
198#define CONFIG_SYS_NS16550
199#define CONFIG_SYS_NS16550_SERIAL
200#define CONFIG_SYS_NS16550_REG_SIZE 1
201#define CONFIG_SYS_NS16550_CLK get_serial_clock()
202
203#undef CONFIG_SYS_EXT_SERIAL_CLOCK
204#define CONFIG_SYS_BASE_BAUD 691200
205
206
207#define CONFIG_SYS_BAUDRATE_TABLE \
208 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
209 57600, 115200, 230400, 460800, 921600 }
210
211#define CONFIG_SYS_LOAD_ADDR 0x100000
212#define CONFIG_SYS_EXTBDINFO 1
213
214#define CONFIG_SYS_HZ 1000
215
216#define CONFIG_ZERO_BOOTDELAY_CHECK
217
218
219
220
221
222
223
224
225
226
227
228#define PPCHAMELON_NAND_TIMER_HACK
229
230#define CONFIG_SYS_NAND0_BASE 0xFF400000
231#define CONFIG_SYS_NAND1_BASE 0xFF000000
232#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, CONFIG_SYS_NAND1_BASE }
233#define NAND_BIG_DELAY_US 25
234#define CONFIG_SYS_MAX_NAND_DEVICE 2
235
236#define CONFIG_SYS_NAND0_CE (0x80000000 >> 1)
237#define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4)
238#define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2)
239#define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3)
240
241#define CONFIG_SYS_NAND1_CE (0x80000000 >> 14)
242#define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31)
243#define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15)
244#define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16)
245
246#define MACRO_NAND_DISABLE_CE(nandptr) do \
247{ \
248 switch((unsigned long)nandptr) \
249 { \
250 case CONFIG_SYS_NAND0_BASE: \
251 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \
252 break; \
253 case CONFIG_SYS_NAND1_BASE: \
254 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \
255 break; \
256 } \
257} while(0)
258
259#define MACRO_NAND_ENABLE_CE(nandptr) do \
260{ \
261 switch((unsigned long)nandptr) \
262 { \
263 case CONFIG_SYS_NAND0_BASE: \
264 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \
265 break; \
266 case CONFIG_SYS_NAND1_BASE: \
267 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \
268 break; \
269 } \
270} while(0)
271
272#define MACRO_NAND_CTL_CLRALE(nandptr) do \
273{ \
274 switch((unsigned long)nandptr) \
275 { \
276 case CONFIG_SYS_NAND0_BASE: \
277 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \
278 break; \
279 case CONFIG_SYS_NAND1_BASE: \
280 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \
281 break; \
282 } \
283} while(0)
284
285#define MACRO_NAND_CTL_SETALE(nandptr) do \
286{ \
287 switch((unsigned long)nandptr) \
288 { \
289 case CONFIG_SYS_NAND0_BASE: \
290 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \
291 break; \
292 case CONFIG_SYS_NAND1_BASE: \
293 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \
294 break; \
295 } \
296} while(0)
297
298#define MACRO_NAND_CTL_CLRCLE(nandptr) do \
299{ \
300 switch((unsigned long)nandptr) \
301 { \
302 case CONFIG_SYS_NAND0_BASE: \
303 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \
304 break; \
305 case CONFIG_SYS_NAND1_BASE: \
306 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \
307 break; \
308 } \
309} while(0)
310
311#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
312 switch((unsigned long)nandptr) { \
313 case CONFIG_SYS_NAND0_BASE: \
314 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \
315 break; \
316 case CONFIG_SYS_NAND1_BASE: \
317 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \
318 break; \
319 } \
320} while(0)
321
322
323
324
325
326#define PCI_HOST_ADAPTER 0
327#define PCI_HOST_FORCE 1
328#define PCI_HOST_AUTO 2
329
330#define CONFIG_PCI
331#define CONFIG_PCI_HOST PCI_HOST_FORCE
332#undef CONFIG_PCI_PNP
333
334
335#define CONFIG_PCI_SCAN_SHOW
336
337#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014
338#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000
339#define CONFIG_SYS_PCI_CLASSCODE 0x0b20
340
341#define CONFIG_SYS_PCI_PTM1LA 0x00000000
342#define CONFIG_SYS_PCI_PTM1MS 0xfc000001
343#define CONFIG_SYS_PCI_PTM1PCI 0x00000000
344#define CONFIG_SYS_PCI_PTM2LA 0xffc00000
345#define CONFIG_SYS_PCI_PTM2MS 0xffc00001
346#define CONFIG_SYS_PCI_PTM2PCI 0x04000000
347
348
349
350
351
352
353#define CONFIG_SYS_SDRAM_BASE 0x00000000
354
355
356
357
358
359
360
361
362
363#define CONFIG_SYS_FLASH_BASE 0xFFFB0000
364#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
365#define CONFIG_SYS_MONITOR_LEN (320 * 1024)
366
367#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
368
369
370
371
372
373
374#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
375
376
377
378#define CONFIG_SYS_MAX_FLASH_BANKS 1
379#define CONFIG_SYS_MAX_FLASH_SECT 256
380
381#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
382#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
383
384#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
385#define CONFIG_SYS_FLASH_ADDR0 0x5555
386#define CONFIG_SYS_FLASH_ADDR1 0x2AAA
387
388
389
390
391#define CONFIG_SYS_FLASH_READ0 0x0000
392#define CONFIG_SYS_FLASH_READ1 0x0001
393#define CONFIG_SYS_FLASH_READ2 0x0002
394
395#define CONFIG_SYS_FLASH_EMPTY_INFO
396
397
398
399
400#ifdef ENVIRONMENT_IN_EEPROM
401
402#define CONFIG_ENV_IS_IN_EEPROM 1
403#define CONFIG_ENV_OFFSET 0x100
404#define CONFIG_ENV_SIZE 0x700
405
406#else
407
408#define CONFIG_ENV_IS_IN_FLASH 1
409#define CONFIG_ENV_ADDR 0xFFFF8000
410#define CONFIG_ENV_SECT_SIZE 0x2000
411#define CONFIG_ENV_ADDR_REDUND 0xFFFFA000
412#define CONFIG_ENV_SIZE_REDUND 0x2000
413
414#define CONFIG_SYS_USE_PPCENV
415
416#endif
417
418
419#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500
420#define CONFIG_SYS_NVRAM_SIZE 242
421
422
423
424
425#define CONFIG_HARD_I2C
426#define CONFIG_PPC4XX_I2C
427#define CONFIG_SYS_I2C_SPEED 400000
428#define CONFIG_SYS_I2C_SLAVE 0x7F
429
430#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
431#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
432
433
434#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
435
436
437#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
438
439
440
441
442
443
444
445#define FLASH_BASE0_PRELIM 0xFFC00000
446
447
448
449
450
451
452#define CONFIG_SYS_EBC_PB0AP 0x92015480
453#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
454
455
456
457#define CONFIG_SYS_EBC_PB1AP 0x92015480
458#define CONFIG_SYS_EBC_PB1CR 0xFF85A000
459
460
461#define CONFIG_SYS_EBC_PB2AP 0x92015480
462#define CONFIG_SYS_EBC_PB2CR 0xFF458000
463
464
465#define CONFIG_SYS_EBC_PB3AP 0x92015480
466#define CONFIG_SYS_EBC_PB3CR 0xFF058000
467
468#ifdef CONFIG_PPCHAMELEON_SMI712
469
470
471
472#define CONFIG_VIDEO
473#define CONFIG_CFB_CONSOLE
474#define CONFIG_VIDEO_SMI_LYNXEM
475#define CONFIG_VIDEO_LOGO
476
477#define CONFIG_CONSOLE_EXTRA_INFO
478#define CONFIG_VGA_AS_SINGLE_DEVICE
479
480#define CONFIG_SYS_ISA_IO 0xE8000000
481
482#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x303
483#endif
484
485
486
487
488
489#define CONFIG_SYS_FPGA_MODE 0x00
490#define CONFIG_SYS_FPGA_STATUS 0x02
491#define CONFIG_SYS_FPGA_TS 0x04
492#define CONFIG_SYS_FPGA_TS_LOW 0x06
493#define CONFIG_SYS_FPGA_TS_CAP0 0x10
494#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
495#define CONFIG_SYS_FPGA_TS_CAP1 0x14
496#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
497#define CONFIG_SYS_FPGA_TS_CAP2 0x18
498#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
499#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
500#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
501
502
503#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
504#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
505#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
506#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
507
508
509#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
510#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
511#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
512#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
513#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
514
515#define CONFIG_SYS_FPGA_SPARTAN2 1
516#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024
517
518
519#define CONFIG_SYS_FPGA_PRG 0x04000000
520#define CONFIG_SYS_FPGA_CLK 0x02000000
521#define CONFIG_SYS_FPGA_DATA 0x01000000
522#define CONFIG_SYS_FPGA_INIT 0x00010000
523#define CONFIG_SYS_FPGA_DONE 0x00008000
524
525
526
527
528
529#define CONFIG_SYS_TEMP_STACK_OCM 1
530
531
532#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
533#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
534#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
535#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
536
537#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
538#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553#define CONFIG_SYS_GPIO0_OSRL 0x40000550
554#define CONFIG_SYS_GPIO0_OSRH 0x00000110
555#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
556
557#define CONFIG_SYS_GPIO0_ISR1H 0x15555444
558#define CONFIG_SYS_GPIO0_TSRL 0x00000000
559#define CONFIG_SYS_GPIO0_TSRH 0x00000000
560#define CONFIG_SYS_GPIO0_TCR 0xF7FF8014
561
562#define CONFIG_NO_SERIAL_EEPROM
563
564
565
566#ifdef CONFIG_NO_SERIAL_EEPROM
567
568
569
570
571
572
573
574
575#undef AUTO_MEMORY_CONFIG
576#define DIMM_READ_ADDR 0xAB
577#define DIMM_WRITE_ADDR 0xAA
578
579
580#define PLL_ACTIVE 0x80000000
581#define CPC0_PLLMR1_SSCS 0x80000000
582#define PLL_RESET 0x40000000
583#define CPC0_PLLMR1_PLLR 0x40000000
584
585#define PLL_FBKDIV 0x00F00000
586#define CPC0_PLLMR1_FBDV 0x00F00000
587#define PLL_FBKDIV_16 0x00000000
588#define PLL_FBKDIV_1 0x00100000
589#define PLL_FBKDIV_2 0x00200000
590#define PLL_FBKDIV_3 0x00300000
591#define PLL_FBKDIV_4 0x00400000
592#define PLL_FBKDIV_5 0x00500000
593#define PLL_FBKDIV_6 0x00600000
594#define PLL_FBKDIV_7 0x00700000
595#define PLL_FBKDIV_8 0x00800000
596#define PLL_FBKDIV_9 0x00900000
597#define PLL_FBKDIV_10 0x00A00000
598#define PLL_FBKDIV_11 0x00B00000
599#define PLL_FBKDIV_12 0x00C00000
600#define PLL_FBKDIV_13 0x00D00000
601#define PLL_FBKDIV_14 0x00E00000
602#define PLL_FBKDIV_15 0x00F00000
603
604#define PLL_FWDDIVA 0x00070000
605#define CPC0_PLLMR1_FWDVA 0x00070000
606#define PLL_FWDDIVA_8 0x00000000
607#define PLL_FWDDIVA_7 0x00010000
608#define PLL_FWDDIVA_6 0x00020000
609#define PLL_FWDDIVA_5 0x00030000
610#define PLL_FWDDIVA_4 0x00040000
611#define PLL_FWDDIVA_3 0x00050000
612#define PLL_FWDDIVA_2 0x00060000
613#define PLL_FWDDIVA_1 0x00070000
614
615#define PLL_FWDDIVB 0x00007000
616#define CPC0_PLLMR1_FWDVB 0x00007000
617#define PLL_FWDDIVB_8 0x00000000
618#define PLL_FWDDIVB_7 0x00001000
619#define PLL_FWDDIVB_6 0x00002000
620#define PLL_FWDDIVB_5 0x00003000
621#define PLL_FWDDIVB_4 0x00004000
622#define PLL_FWDDIVB_3 0x00005000
623#define PLL_FWDDIVB_2 0x00006000
624#define PLL_FWDDIVB_1 0x00007000
625
626#define PLL_TUNE_MASK 0x000003FF
627#define PLL_TUNE_2_M_3 0x00000133
628#define PLL_TUNE_4_M_6 0x00000134
629#define PLL_TUNE_7_M_10 0x00000138
630#define PLL_TUNE_11_M_14 0x0000013C
631#define PLL_TUNE_15_M_40 0x0000023E
632#define PLL_TUNE_VCO_LOW 0x00000000
633#define PLL_TUNE_VCO_HI 0x00000080
634
635
636
637#define PLL_CPUDIV 0x00300000
638#define CPC0_PLLMR0_CCDV 0x00300000
639#define PLL_CPUDIV_1 0x00000000
640#define PLL_CPUDIV_2 0x00100000
641#define PLL_CPUDIV_3 0x00200000
642#define PLL_CPUDIV_4 0x00300000
643
644#define PLL_PLBDIV 0x00030000
645#define CPC0_PLLMR0_CBDV 0x00030000
646#define PLL_PLBDIV_1 0x00000000
647#define PLL_PLBDIV_2 0x00010000
648#define PLL_PLBDIV_3 0x00020000
649#define PLL_PLBDIV_4 0x00030000
650
651#define PLL_OPBDIV 0x00003000
652#define CPC0_PLLMR0_OPDV 0x00003000
653#define PLL_OPBDIV_1 0x00000000
654#define PLL_OPBDIV_2 0x00001000
655#define PLL_OPBDIV_3 0x00002000
656#define PLL_OPBDIV_4 0x00003000
657
658#define PLL_EXTBUSDIV 0x00000300
659#define CPC0_PLLMR0_EPDV 0x00000300
660#define PLL_EXTBUSDIV_2 0x00000000
661#define PLL_EXTBUSDIV_3 0x00000100
662#define PLL_EXTBUSDIV_4 0x00000200
663#define PLL_EXTBUSDIV_5 0x00000300
664
665#define PLL_MALDIV 0x00000030
666#define CPC0_PLLMR0_MPDV 0x00000030
667#define PLL_MALDIV_1 0x00000000
668#define PLL_MALDIV_2 0x00000010
669#define PLL_MALDIV_3 0x00000020
670#define PLL_MALDIV_4 0x00000030
671
672#define PLL_PCIDIV 0x00000003
673#define CPC0_PLLMR0_PPFD 0x00000003
674#define PLL_PCIDIV_1 0x00000000
675#define PLL_PCIDIV_2 0x00000001
676#define PLL_PCIDIV_3 0x00000002
677#define PLL_PCIDIV_4 0x00000003
678
679#ifdef CONFIG_PPCHAMELEON_CLK_25
680
681#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
682 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
683 PLL_MALDIV_1 | PLL_PCIDIV_4)
684#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \
685 PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \
686 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
687
688#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
689 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
690 PLL_MALDIV_1 | PLL_PCIDIV_4)
691#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \
692 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
693 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
694
695#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
696 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
697 PLL_MALDIV_1 | PLL_PCIDIV_4)
698#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
699 PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
700 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
701
702#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
703 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
704 PLL_MALDIV_1 | PLL_PCIDIV_2)
705#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
706 PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
707 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
708
709#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
710
711
712#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
713 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
714 PLL_MALDIV_1 | PLL_PCIDIV_4)
715#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \
716 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
717 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
718
719#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
720 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
721 PLL_MALDIV_1 | PLL_PCIDIV_4)
722#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
723 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
724 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
725
726#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
727 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
728 PLL_MALDIV_1 | PLL_PCIDIV_4)
729#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
730 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
731 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
732
733#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
734 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
735 PLL_MALDIV_1 | PLL_PCIDIV_2)
736#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
737 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
738 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
739
740#else
741#error "* External frequency (SysClk) not defined! *"
742#endif
743
744#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
745
746#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55
747#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55
748#define CONFIG_SYS_OPB_FREQ 55555555
749
750#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
751#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33
752#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33
753#define CONFIG_SYS_OPB_FREQ 66666666
754#else
755
756#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33
757#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33
758#define CONFIG_SYS_OPB_FREQ 66666666
759#endif
760
761#endif
762
763#define CONFIG_JFFS2_NAND 1
764#define NAND_CACHE_PAGES 16
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770
771#undef CONFIG_CMD_MTDPARTS
772#define CONFIG_JFFS2_DEV "nand0"
773#define CONFIG_JFFS2_PART_SIZE 0x00400000
774#define CONFIG_JFFS2_PART_OFFSET 0x00000000
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796#endif
797