1/* 2 * (C) Copyright 2003 3 * MuLogic B.V. 4 * 5 * (C) Copyright 2002 6 * Simple Network Magic Corporation 7 * 8 * (C) Copyright 2000 9 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 10 * 11 * See file CREDITS for list of people who contributed to this 12 * project. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27 * MA 02111-1307 USA 28 */ 29 30/* 31 * board/config.h - configuration options, board specific 32 */ 33 34#ifndef __CONFIG_H 35#define __CONFIG_H 36 37/* various debug settings */ 38#undef CONFIG_SYS_DEVICE_NULLDEV /* null device */ 39#undef CONFIG_SILENT_CONSOLE /* silent console */ 40#undef CONFIG_SYS_CONSOLE_INFO_QUIET /* silent console ? */ 41#undef DEBUG_FLASH /* debug flash code */ 42#undef FLASH_DEBUG /* debug fash code */ 43#undef DEBUG_ENV /* debug environment code */ 44 45#define CONFIG_SYS_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */ 46#define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */ 47 48 49/* 50 * High Level Configuration Options 51 * (easy to change) 52 */ 53 54#define CONFIG_MPC860 1 /* This is a MPC860 CPU */ 55#define CONFIG_QS860T 1 /* ...on a QS860T module */ 56 57/* Start address of 512K Socketed Flash */ 58#define CONFIG_SYS_TEXT_BASE 0xFFF00000 59 60#define CONFIG_FEC_ENET 1 /* FEC 10/100BaseT ethernet */ 61#define CONFIG_MII 62#define FEC_INTERRUPT SIU_LEVEL1 63#undef CONFIG_SCC1_ENET /* SCC1 10BaseT ethernet */ 64#define CONFIG_SYS_DISCOVER_PHY 65 66#undef CONFIG_8xx_CONS_SMC1 67#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC */ 68#undef CONFIG_8xx_CONS_NONE 69 70#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */ 71 72#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 73 74/* Pass clocks to Linux 2.4.18 in Hz */ 75#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */ 76 77#define CONFIG_PREBOOT "echo;" \ 78 "echo 'Type \\\"run flash_nfs\\\" to mount root filesystem over NFS';" \ 79 "echo" 80 81#undef CONFIG_BOOTARGS 82/* TODO compare against CADM860 */ 83#define CONFIG_BOOTCOMMAND "bootp; " \ 84 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ 85 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ 86 "bootm" 87 88#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 89#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 90 91#undef CONFIG_WATCHDOG /* watchdog disabled */ 92 93#undef CONFIG_STATUS_LED /* Status LED disabled */ 94 95#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 96 97/* 98 * BOOTP options 99 */ 100#define CONFIG_BOOTP_SUBNETMASK 101#define CONFIG_BOOTP_GATEWAY 102#define CONFIG_BOOTP_HOSTNAME 103#define CONFIG_BOOTP_BOOTPATH 104#define CONFIG_BOOTP_BOOTFILESIZE 105 106 107#define CONFIG_MAC_PARTITION 108#define CONFIG_DOS_PARTITION 109 110#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 111 112 113/* 114 * Command line configuration. 115 */ 116#include <config_cmd_default.h> 117 118#define CONFIG_CMD_REGINFO 119#define CONFIG_CMD_IMMAP 120#define CONFIG_CMD_ASKENV 121#define CONFIG_CMD_NET 122#define CONFIG_CMD_DHCP 123#define CONFIG_CMD_DATE 124 125 126/* TODO */ 127#if 0 128/* Look at these */ 129CONFIG_IPADDR 130CONFIG_SERVERIP 131CONFIG_I2C 132CONFIG_SPI 133#endif 134 135/* 136 * Environment variable storage is in NVRAM 137 */ 138#define CONFIG_ENV_IS_IN_NVRAM 1 139#define CONFIG_ENV_SIZE 0x00001000 /* We use only the last 4K for PPCBoot */ 140#define CONFIG_ENV_ADDR 0xD100E000 141 142/* 143 * Miscellaneous configurable options 144 */ 145#define CONFIG_SYS_LONGHELP /* undef to save memory */ 146#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 147 148#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ 149#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 150 151#if defined(CONFIG_CMD_KGDB) 152#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 153#else 154#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 155#endif 156#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 157#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 158#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 159 160/* TODO - size? */ 161#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works */ 162#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 163 164#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 165 166#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 167 168#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 169 170/*----------------------------------------------------------------------- 171 * Low Level Configuration Settings 172 * (address mappings, register initial values, etc.) 173 * You should know what you are doing if you make changes here. 174 */ 175/*----------------------------------------------------------------------- 176 * Internal Memory Mapped Register 177 */ 178#define CONFIG_SYS_IMMR 0xF0000000 179 180/*----------------------------------------------------------------------- 181 * Definitions for initial stack pointer and data area (in DPRAM) 182 */ 183#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 184#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 185#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 186#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 187 188/*----------------------------------------------------------------------- 189 * Start addresses for the final memory configuration 190 * (Set up by the startup code) 191 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 192 */ 193#define CONFIG_SYS_SDRAM_BASE 0x00000000 194#define CONFIG_SYS_FLASH_BASE 0xFFF00000 195 196#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ 197#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 198#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 199 200/* 201 * For booting Linux, the board info and command line data 202 * have to be in the first 8 MB of memory, since this is 203 * the maximum mapped by the Linux kernel during initialization. 204 */ 205#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 206 207/* TODO flash parameters */ 208/*----------------------------------------------------------------------- 209 * FLASH organization for Intel Strataflash 210 */ 211#define CONFIG_SYS_FLASH_16BIT 1 /* 16-bit wide flash memory */ 212#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 213#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ 214 215#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 216#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 217 218#undef CONFIG_ENV_IS_IN_FLASH 219 220/*----------------------------------------------------------------------- 221 * Cache Configuration 222 */ 223#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 224#if defined(CONFIG_CMD_KGDB) 225#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 226#endif 227 228/*----------------------------------------------------------------------- 229 * SYPCR - System Protection Control 11-9 230 * SYPCR can only be written once after reset! 231 *----------------------------------------------------------------------- 232 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 233 */ 234#if defined(CONFIG_WATCHDOG) 235#define CONFIG_SYS_SYPCR (0xFFFFFF88 | SYPCR_SWE | SYPCR_SWRI) 236#else 237#define CONFIG_SYS_SYPCR 0xFFFFFF88 238#endif 239 240/*----------------------------------------------------------------------- 241 * SIUMCR - SIU Module Configuration 11-6 242 *----------------------------------------------------------------------- 243 */ 244#define CONFIG_SYS_SIUMCR 0x00620000 245 246/*----------------------------------------------------------------------- 247 * TBSCR - Time Base Status and Control 11-26 248 *----------------------------------------------------------------------- 249 */ 250#define CONFIG_SYS_TBSCR 0x00C3 251 252/*----------------------------------------------------------------------- 253 * RTCSC - Real-Time Clock Status and Control Register 11-27 254 *----------------------------------------------------------------------- 255 */ 256#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 257 258/*----------------------------------------------------------------------- 259 * PISCR - Periodic Interrupt Status and Control 11-31 260 *----------------------------------------------------------------------- 261 */ 262#define CONFIG_SYS_PISCR 0x0082 263 264/*----------------------------------------------------------------------- 265 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 266 *----------------------------------------------------------------------- 267 */ 268#define CONFIG_SYS_PLPRCR 0x0090D000 269 270/*----------------------------------------------------------------------- 271 * SCCR - System Clock and reset Control Register 15-27 272 *----------------------------------------------------------------------- 273 */ 274#define SCCR_MASK SCCR_EBDF11 275#define CONFIG_SYS_SCCR 0x02000000 276 277 278/*----------------------------------------------------------------------- 279 * Debug Enable Register 280 * 0x73E67C0F - All interrupts handled by BDM 281 * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM 282 *----------------------------------------------------------------------- 283#define CONFIG_SYS_DER 0x73E67C0F 284*/ 285#define CONFIG_SYS_DER 0x0082400F 286 287 288/*----------------------------------------------------------------------- 289 * Memory Controller Initialization Constants 290 *----------------------------------------------------------------------- 291 */ 292 293/* 294 * BR0 and OR0 (AMD 512K Socketed FLASH) 295 * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation) 296 */ 297#define CONFIG_SYS_PRELIM_OR_AM 298#define CONFIG_SYS_OR_TIMING_FLASH 299 300#define FLASH_BASE0_PRELIM 0xFFF00001 301#define CONFIG_SYS_OR0_PRELIM 0xFFF80D42 302#define CONFIG_SYS_BR0_PRELIM 0xFFF00401 303 304 305/* 306 * BR1 and OR1 (Intel 8M StrataFLASH) 307 * Base address = 0xD000_0000 - 0xD07F_FFFF 308 */ 309 310#define FLASH_BASE1_PRELIM 0xD0000000 311#define CONFIG_SYS_OR1_PRELIM 0xFF800D42 312#define CONFIG_SYS_BR1_PRELIM 0xD0000801 313/* #define CONFIG_SYS_OR1 0xFF800D42 */ 314/* #define CONFIG_SYS_BR1 0xD0000801 */ 315 316 317/* 318 * BR2 and OR2 (SDRAM) 319 * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation) 320 * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation) 321 * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation) 322 * 323 */ 324#define SDRAM_BASE 0x00000000 /* SDRAM bank */ 325#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ 326 327/* SDRAM timing */ 328#define SDRAM_TIMING 0x00000A00 329 330/* For boards with 16M of SDRAM */ 331#define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */ 332#define CONFIG_SYS_16M_MBMR 0x18802114 /* Mem Periodic Timer Prescaler */ 333 334/* For boards with 64M of SDRAM */ 335#define SDRAM_64M_MAX_SIZE 0x04000000 /* max 64MB SDRAM */ 336/* TODO - determine real value */ 337#define CONFIG_SYS_64M_MBMR 0x18802114 /* Mem Period Timer Prescaler */ 338 339#define CONFIG_SYS_OR2 (SDRAM_PRELIM_OR_AM | SDRAM_TIMING) 340#define CONFIG_SYS_BR2 (SDRAM_BASE | 0x000000C1) 341 342 343/* 344 * BR3 and OR3 (NVRAM, Sipex, NAND Flash) 345 * Base address = 0xD100_0000 - 0xD100_FFFF (64K NVRAM) 346 * Base address = 0xD108_0000 - 0xD108_0000 (Sipex chip ctl register) 347 * Base address = 0xD110_0000 - 0xD110_0000 (NAND ctl register) 348 * Base address = 0xD138_0000 - 0xD138_0000 (LED ctl register) 349 * 350 */ 351 352#define CONFIG_SYS_OR3_PRELIM 0xFFC00DF6 353#define CONFIG_SYS_BR3_PRELIM 0xD1000401 354/* #define CONFIG_SYS_OR3 0xFFC00DF6 */ 355/* #define CONFIG_SYS_BR3 0xD1000401 */ 356 357 358/* 359 * BR4 and OR4 (Unused) 360 * Base address = 0xE000_0000 - 0xE3FF_FFFF 361 * 362 */ 363 364#define CONFIG_SYS_OR4_PRELIM 0xFF000000 365#define CONFIG_SYS_BR4_PRELIM 0xE0000000 366/* #define CONFIG_SYS_OR4 0xFF000000 */ 367/* #define CONFIG_SYS_BR4 0xE0000000 */ 368 369 370/* 371 * BR5 and OR5 (Expansion bus) 372 * Base address = 0xE400_0000 - 0xE7FF_FFFF 373 * 374 */ 375 376#define CONFIG_SYS_OR5_PRELIM 0xFF000000 377#define CONFIG_SYS_BR5_PRELIM 0xE4000000 378/* #define CONFIG_SYS_OR5 0xFF000000 */ 379/* #define CONFIG_SYS_BR5 0xE4000000 */ 380 381 382/* 383 * BR6 and OR6 (Expansion bus) 384 * Base address = 0xE800_0000 - 0xEBFF_FFFF 385 * 386 */ 387 388#define CONFIG_SYS_OR6_PRELIM 0xFF000000 389#define CONFIG_SYS_BR6_PRELIM 0xE8000000 390/* #define CONFIG_SYS_OR6 0xFF000000 */ 391/* #define CONFIG_SYS_BR6 0xE8000000 */ 392 393 394/* 395 * BR7 and OR7 (Expansion bus) 396 * Base address = 0xEC00_0000 - 0xEFFF_FFFF 397 * 398 */ 399 400#define CONFIG_SYS_OR7_PRELIM 0xFF000000 401#define CONFIG_SYS_BR7_PRELIM 0xE8000000 402/* #define CONFIG_SYS_OR7 0xFF000000 */ 403/* #define CONFIG_SYS_BR7 0xE8000000 */ 404 405/* 406 * Sanity checks 407 */ 408#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET) 409#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured 410#endif 411 412#endif /* __CONFIG_H */ 413