LXR uboot/include/configs/SBC8540.h

   1/*
   2 * (C) Copyright 2002,2003 Motorola,Inc.
   3 * Xianghua Xiao <X.Xiao@motorola.com>
   4 *
   5 * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
   6 * Added support for Wind River SBC8540 board
   7 *
   8 * See file CREDITS for list of people who contributed to this
   9 * project.
  10 *
  11 * This program is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU General Public License as
  13 * published by the Free Software Foundation; either version 2 of
  14 * the License, or (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 * MA 02111-1307 USA
  25 */
  26
  27/*
  28 * sbc8540 board configuration file.
  29 */
  30
  31#ifndef __CONFIG_H
  32#define __CONFIG_H
  33
  34/*
  35 * Top level Makefile configuration choices
  36 */
  37#ifdef CONFIG_66
  38#define CONFIG_PCI_66
  39#endif
  40
  41#define TSEC_DEBUG
  42
  43/*
  44 * High Level Configuration Options
  45 */
  46#define CONFIG_BOOKE            1       /* BOOKE                        */
  47#define CONFIG_E500             1       /* BOOKE e500 family            */
  48#define CONFIG_MPC85xx          1       /* MPC8540/MPC8560              */
  49#define CONFIG_MPC85xx_REV1     1       /* MPC85xx Rev 1.0 chip         */
  50
  51#define CONFIG_SYS_TEXT_BASE    0xfffc0000
  52
  53
  54#define CONFIG_CPM2             1       /* has CPM2 */
  55
  56#define CONFIG_SBC8540          1       /* configuration for SBC8560 board */
  57#define CONFIG_MPC8540          1
  58
  59#define CONFIG_MPC8560ADS       1       /* MPC8560ADS board specific (supplement)       */
  60
  61#define CONFIG_TSEC_ENET                /* tsec ethernet support        */
  62#undef  CONFIG_PCI                      /* pci ethernet support         */
  63#undef  CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support     */
  64
  65#define CONFIG_FSL_LAW          1       /* Use common FSL init code */
  66
  67#define CONFIG_ENV_OVERWRITE
  68
  69/* Using Localbus SDRAM to emulate flash before we can program the flash,
  70 * normally you need a flash-boot image(u-boot.bin), if so undef this.
  71 */
  72#undef CONFIG_RAM_AS_FLASH
  73
  74#if defined(CONFIG_PCI_66)                      /* some PCI card is 33Mhz only  */
  75  #define CONFIG_SYS_CLK_FREQ   66000000        /* sysclk for MPC85xx           */
  76#else
  77  #define CONFIG_SYS_CLK_FREQ   33000000        /* most pci cards are 33Mhz     */
  78#endif
  79
  80/* below can be toggled for performance analysis. otherwise use default */
  81#define CONFIG_L2_CACHE                     /* toggle L2 cache          */
  82#undef  CONFIG_BTB                          /* toggle branch predition  */
  83
  84#define CONFIG_BOARD_EARLY_INIT_F 1         /* Call board_early_init_f  */
  85#define CONFIG_RESET_PHY_R      1           /* Call reset_phy() */
  86
  87#undef  CONFIG_SYS_DRAM_TEST                        /* memory test, takes time  */
  88#define CONFIG_SYS_MEMTEST_START        0x00200000  /* memtest region */
  89#define CONFIG_SYS_MEMTEST_END          0x00400000
  90
  91#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
  92     defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
  93     defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
  94#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
  95#endif
  96
  97/*
  98 * Base addresses -- Note these are effective addresses where the
  99 * actual resources get mapped (not physical addresses)
 100 */
 101#define CONFIG_SYS_CCSRBAR_DEFAULT      0xff700000      /* CCSRBAR Default      */
 102
 103#if XXX
 104  #define CONFIG_SYS_CCSRBAR            0xfdf00000      /* relocated CCSRBAR    */
 105#else
 106  #define CONFIG_SYS_CCSRBAR            0xff700000      /* default CCSRBAR      */
 107#endif
 108#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR      /* physical addr of CCSRBAR */
 109#define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses CONFIG_SYS_IMMR    */
 110
 111#define CONFIG_SYS_SDRAM_SIZE           512             /* DDR is 512MB */
 112
 113/* DDR Setup */
 114#define CONFIG_FSL_DDR1
 115#undef CONFIG_FSL_DDR_INTERACTIVE
 116#undef  CONFIG_DDR_ECC                          /* only for ECC DDR module      */
 117#undef  CONFIG_SPD_EEPROM                       /* Use SPD EEPROM for DDR setup */
 118#undef  CONFIG_DDR_SPD
 119
 120#if defined(CONFIG_MPC85xx_REV1)
 121  #define CONFIG_DDR_DLL                        /* possible DLL fix needed      */
 122#endif
 123
 124#undef  CONFIG_DDR_ECC                      /* only for ECC DDR module */
 125#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER        /* DDR controller or DMA? */
 126#define CONFIG_MEM_INIT_VALUE   0xDeadBeef
 127
 128#define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 129#define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 130#define CONFIG_VERY_BIG_RAM
 131
 132#define CONFIG_NUM_DDR_CONTROLLERS      1
 133#define CONFIG_DIMM_SLOTS_PER_CTLR      1
 134#define CONFIG_CHIP_SELECTS_PER_CTRL    2
 135
 136/* I2C addresses of SPD EEPROMs */
 137#define SPD_EEPROM_ADDRESS      0x55    /* CTLR 0 DIMM 0 */
 138
 139#undef CONFIG_CLOCKS_IN_MHZ
 140
 141#if defined(CONFIG_RAM_AS_FLASH)
 142  #define CONFIG_SYS_LBC_SDRAM_BASE     0xfc000000      /* Localbus SDRAM */
 143  #define CONFIG_SYS_FLASH_BASE 0xf8000000      /* start of FLASH 8M  */
 144  #define CONFIG_SYS_BR0_PRELIM 0xf8000801      /* port size 8bit */
 145  #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7      /* 8MB Flash            */
 146#else /* Boot from real Flash */
 147  #define CONFIG_SYS_LBC_SDRAM_BASE     0xf8000000      /* Localbus SDRAM */
 148  #define CONFIG_SYS_FLASH_BASE 0xff800000      /* start of FLASH 8M    */
 149  #define CONFIG_SYS_BR0_PRELIM 0xff800801      /* port size 8bit      */
 150  #define CONFIG_SYS_OR0_PRELIM 0xff800ff7      /* 8MB Flash            */
 151#endif
 152#define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB    */
 153
 154/* local bus definitions */
 155#define CONFIG_SYS_BR1_PRELIM           0xe4001801      /* 64M, 32-bit flash */
 156#define CONFIG_SYS_OR1_PRELIM           0xfc000ff7
 157
 158#define CONFIG_SYS_BR2_PRELIM           0x00000000      /* CS2 not used */
 159#define CONFIG_SYS_OR2_PRELIM           0x00000000
 160
 161#define CONFIG_SYS_BR3_PRELIM           0xf0001861      /* 64MB localbus SDRAM  */
 162#define CONFIG_SYS_OR3_PRELIM           0xfc000cc1
 163
 164#if defined(CONFIG_RAM_AS_FLASH)
 165  #define CONFIG_SYS_BR4_PRELIM 0xf4001861      /* 64M localbus SDRAM */
 166#else
 167  #define CONFIG_SYS_BR4_PRELIM 0xf8001861      /* 64M localbus SDRAM */
 168#endif
 169#define CONFIG_SYS_OR4_PRELIM           0xfc000cc1
 170
 171#define CONFIG_SYS_BR5_PRELIM           0xfc000801      /* 16M CS5 misc devices */
 172#if 1
 173  #define CONFIG_SYS_OR5_PRELIM 0xff000ff7
 174#else
 175  #define CONFIG_SYS_OR5_PRELIM 0xff0000f0
 176#endif
 177
 178#define CONFIG_SYS_BR6_PRELIM           0xe0001801      /* 64M, 32-bit flash */
 179#define CONFIG_SYS_OR6_PRELIM           0xfc000ff7
 180#define CONFIG_SYS_LBC_LCRR             0x00030002      /* local bus freq       */
 181#define CONFIG_SYS_LBC_LBCR             0x00000000
 182#define CONFIG_SYS_LBC_LSRT             0x20000000
 183#define CONFIG_SYS_LBC_MRTPR            0x20000000
 184#define CONFIG_SYS_LBC_LSDMR_1          0x2861b723
 185#define CONFIG_SYS_LBC_LSDMR_2          0x0861b723
 186#define CONFIG_SYS_LBC_LSDMR_3          0x0861b723
 187#define CONFIG_SYS_LBC_LSDMR_4          0x1861b723
 188#define CONFIG_SYS_LBC_LSDMR_5          0x4061b723
 189
 190/* just hijack the MOT BCSR def for SBC8560 misc devices */
 191#define CONFIG_SYS_BCSR         ((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000)
 192/* the size of CS5 needs to be >= 16M for TLB and LAW setups */
 193
 194#define CONFIG_SYS_INIT_RAM_LOCK        1
 195#define CONFIG_SYS_INIT_RAM_ADDR        0x70000000      /* Initial RAM address  */
 196#define CONFIG_SYS_INIT_RAM_SIZE        0x4000          /* Size of used area in RAM */
 197
 198#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 199#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 200
 201#define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon */
 202#define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserved for malloc */
 203
 204/* Serial Port */
 205#undef  CONFIG_CONS_ON_SCC                      /* define if console on SCC */
 206#undef  CONFIG_CONS_NONE                        /* define if console on something else */
 207
 208#define CONFIG_CONS_INDEX     1
 209#define CONFIG_SYS_NS16550
 210#define CONFIG_SYS_NS16550_SERIAL
 211#define CONFIG_SYS_NS16550_REG_SIZE     1
 212#if 0
 213#define CONFIG_SYS_NS16550_CLK          1843200 /* get_bus_freq(0) */
 214#else
 215#define CONFIG_SYS_NS16550_CLK          264000000 /* get_bus_freq(0) */
 216#endif
 217
 218#define CONFIG_BAUDRATE         9600
 219
 220#define CONFIG_SYS_BAUDRATE_TABLE  \
 221        {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 222
 223#if 0
 224#define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00700000)
 225#define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00800000)
 226#else
 227/* SBC8540 uses internal COMM controller */
 228#define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_CCSRBAR & 0xfff00000)+0x00004500)
 229#define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_CCSRBAR & 0xfff00000)+0x00004600)
 230#endif
 231
 232/* Use the HUSH parser */
 233#define CONFIG_SYS_HUSH_PARSER
 234#ifdef  CONFIG_SYS_HUSH_PARSER
 235#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 236#endif
 237
 238/*
 239 * I2C
 240 */
 241#define CONFIG_FSL_I2C          /* Use FSL common I2C driver */
 242#define CONFIG_HARD_I2C         /* I2C with hardware support*/
 243#undef  CONFIG_SOFT_I2C                 /* I2C bit-banged */
 244#define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address  */
 245#define CONFIG_SYS_I2C_SLAVE            0x7F
 246#define CONFIG_SYS_I2C_NOPROBES {0x69}  /* Don't probe these addrs */
 247#define CONFIG_SYS_I2C_OFFSET           0x3000
 248
 249#define CONFIG_SYS_PCI_MEM_BASE 0xC0000000
 250#define CONFIG_SYS_PCI_MEM_PHYS 0xC0000000
 251#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
 252
 253#if defined(CONFIG_TSEC_ENET)           /* TSEC Ethernet port */
 254
 255#  define CONFIG_NET_MULTI      1
 256#  define CONFIG_MPC85xx_TSEC1
 257#  define CONFIG_MPC85xx_TSEC1_NAME     "TSEC0"
 258#  define CONFIG_MII            1       /* MII PHY management           */
 259#  define TSEC1_PHY_ADDR        25
 260#  define TSEC1_PHYIDX          0
 261/* Options are: TSEC0 */
 262#  define CONFIG_ETHPRIME               "TSEC0"
 263
 264
 265#elif defined(CONFIG_ETHER_ON_FCC)      /* CPM FCC Ethernet */
 266
 267  #undef  CONFIG_ETHER_NONE             /* define if ether on something else */
 268  #define CONFIG_ETHER_ON_FCC2          /* cpm FCC ethernet support     */
 269  #define CONFIG_ETHER_INDEX    2       /* which channel for ether  */
 270
 271  #if (CONFIG_ETHER_INDEX == 2)
 272    /*
 273     * - Rx-CLK is CLK13
 274     * - Tx-CLK is CLK14
 275     * - Select bus for bd/buffers
 276     * - Full duplex
 277     */
 278    #define CONFIG_SYS_CMXFCR_MASK      (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
 279    #define CONFIG_SYS_CMXFCR_VALUE     (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 280    #define CONFIG_SYS_CPMFCR_RAMTYPE   0
 281    #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
 282
 283  #elif (CONFIG_ETHER_INDEX == 3)
 284    /* need more definitions here for FE3 */
 285  #endif                                /* CONFIG_ETHER_INDEX */
 286
 287  #define CONFIG_MII                    /* MII PHY management */
 288  #define CONFIG_BITBANGMII             /* bit-bang MII PHY management  */
 289  /*
 290   * GPIO pins used for bit-banged MII communications
 291   */
 292  #define MDIO_PORT     2               /* Port C */
 293  #define MDIO_DECLARE  volatile ioport_t *iop = ioport_addr ( \
 294                                (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
 295  #define MDC_DECLARE   MDIO_DECLARE
 296
 297  #define MDIO_ACTIVE   (iop->pdir |=  0x00400000)
 298  #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
 299  #define MDIO_READ     ((iop->pdat &  0x00400000) != 0)
 300
 301  #define MDIO(bit)     if(bit) iop->pdat |=  0x00400000; \
 302                        else    iop->pdat &= ~0x00400000
 303
 304  #define MDC(bit)      if(bit) iop->pdat |=  0x00200000; \
 305                        else    iop->pdat &= ~0x00200000
 306
 307  #define MIIDELAY      udelay(1)
 308
 309#endif
 310
 311/*-----------------------------------------------------------------------
 312 * FLASH and environment organization
 313 */
 314
 315#define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant              */
 316#define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver                */
 317#if 0
 318#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
 319#define CONFIG_SYS_FLASH_PROTECTION             /* use hardware protection              */
 320#endif
 321#define CONFIG_SYS_MAX_FLASH_SECT       64      /* max number of sectors on one chip    */
 322#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 323
 324#undef  CONFIG_SYS_FLASH_CHECKSUM
 325#define CONFIG_SYS_FLASH_ERASE_TOUT     200000          /* Timeout for Flash Erase (in ms)      */
 326#define CONFIG_SYS_FLASH_WRITE_TOUT     50000           /* Timeout for Flash Write (in ms)      */
 327
 328#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor     */
 329
 330#if 0
 331/* XXX This doesn't work and I don't want to fix it */
 332#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 333  #define CONFIG_SYS_RAMBOOT
 334#else
 335  #undef  CONFIG_SYS_RAMBOOT
 336#endif
 337#endif
 338
 339/* Environment */
 340#if !defined(CONFIG_SYS_RAMBOOT)
 341  #if defined(CONFIG_RAM_AS_FLASH)
 342    #define CONFIG_ENV_IS_NOWHERE
 343    #define CONFIG_ENV_ADDR     (CONFIG_SYS_FLASH_BASE + 0x100000)
 344    #define CONFIG_ENV_SIZE     0x2000
 345  #else
 346    #define CONFIG_ENV_IS_IN_FLASH      1
 347    #define CONFIG_ENV_SECT_SIZE        0x20000 /* 128K(one sector) for env */
 348    #define CONFIG_ENV_ADDR     (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 349    #define CONFIG_ENV_SIZE     0x2000 /* CONFIG_ENV_SECT_SIZE */
 350  #endif
 351#else
 352  #define CONFIG_SYS_NO_FLASH           1       /* Flash is not usable now      */
 353  #define CONFIG_ENV_IS_NOWHERE 1       /* Store ENV in memory only     */
 354  #define CONFIG_ENV_ADDR               (CONFIG_SYS_MONITOR_BASE - 0x1000)
 355  #define CONFIG_ENV_SIZE               0x2000
 356#endif
 357
 358#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600"
 359/*#define CONFIG_BOOTARGS      "root=/dev/ram rw console=ttyS0,115200"*/
 360#define CONFIG_BOOTCOMMAND      "bootm 0xff800000 0xffa00000"
 361#define CONFIG_BOOTDELAY        5       /* -1 disable autoboot */
 362
 363#define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 364#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 365
 366
 367/*
 368 * BOOTP options
 369 */
 370#define CONFIG_BOOTP_BOOTFILESIZE
 371#define CONFIG_BOOTP_BOOTPATH
 372#define CONFIG_BOOTP_GATEWAY
 373#define CONFIG_BOOTP_HOSTNAME
 374
 375
 376/*
 377 * Command line configuration.
 378 */
 379#include <config_cmd_default.h>
 380
 381#define CONFIG_CMD_PING
 382#define CONFIG_CMD_I2C
 383#define CONFIG_CMD_REGINFO
 384
 385#if defined(CONFIG_PCI)
 386    #define CONFIG_CMD_PCI
 387#endif
 388
 389#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 390    #define CONFIG_CMD_MII
 391#endif
 392
 393#if defined(CONFIG_SYS_RAMBOOT)
 394    #undef CONFIG_CMD_SAVEENV
 395    #undef CONFIG_CMD_LOADS
 396#endif
 397
 398
 399#undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 400
 401/*
 402 * Miscellaneous configurable options
 403 */
 404#define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 405#define CONFIG_SYS_PROMPT       "SBC8540=> " /* Monitor Command Prompt  */
 406#if defined(CONFIG_CMD_KGDB)
 407  #define CONFIG_SYS_CBSIZE     1024            /* Console I/O Buffer Size      */
 408#else
 409  #define CONFIG_SYS_CBSIZE     256             /* Console I/O Buffer Size      */
 410#endif
 411#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 412#define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 413#define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 414#define CONFIG_SYS_LOAD_ADDR    0x1000000       /* default load address */
 415#define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 416
 417/*
 418 * For booting Linux, the board info and command line data
 419 * have to be in the first 8 MB of memory, since this is
 420 * the maximum mapped by the Linux kernel during initialization.
 421 */
 422#define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 423
 424#if defined(CONFIG_CMD_KGDB)
 425  #define CONFIG_KGDB_BAUDRATE  230400  /* speed to run kgdb serial port */
 426  #define CONFIG_KGDB_SER_INDEX 2       /* which serial port to use */
 427#endif
 428
 429/*Note: change below for your network setting!!! */
 430#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
 431#  define CONFIG_ETHADDR        00:vv:ww:xx:yy:8a
 432#  define CONFIG_HAS_ETH1
 433#  define CONFIG_ETH1ADDR       00:vv:ww:xx:yy:8b
 434#  define CONFIG_HAS_ETH2
 435#  define CONFIG_ETH2ADDR       00:vv:ww:xx:yy:8c
 436#endif
 437
 438#define CONFIG_SERVERIP         YourServerIP
 439#define CONFIG_IPADDR           YourTargetIP
 440#define CONFIG_GATEWAYIP        YourGatewayIP
 441#define CONFIG_NETMASK          255.255.255.0
 442#define CONFIG_HOSTNAME         SBC8560
 443#define CONFIG_ROOTPATH         YourRootPath
 444#define CONFIG_BOOTFILE         YourImageName
 445
 446#endif  /* __CONFIG_H */
 447