1/* 2 * (C) Copyright 2003-2006 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * (C) Copyright 2004-2005 6 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27#ifndef __CONFIG_H 28#define __CONFIG_H 29 30/* 31 * High Level Configuration Options 32 * (easy to change) 33 */ 34 35#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ 36#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ 37#define CONFIG_TQM5200 1 /* ... on TQM5200 module */ 38#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ 39#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */ 40#define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */ 41#define CONFIG_AEVFIFO 1 42#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ 43 44/* 45 * Valid values for CONFIG_SYS_TEXT_BASE are: 46 * 0xFC000000 boot low (standard configuration with room for 47 * max 64 MByte Flash ROM) 48 * 0xFFF00000 boot high (for a backup copy of U-Boot) 49 * 0x00100000 boot from RAM (for testing only) 50 */ 51#ifndef CONFIG_SYS_TEXT_BASE 52#define CONFIG_SYS_TEXT_BASE 0xFC000000 53#endif 54 55#define CONFIG_HIGH_BATS 1 /* High BATs supported */ 56 57/* 58 * Serial console configuration 59 */ 60#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ 61#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ 62#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 63 64/* 65 * PCI Mapping: 66 * 0x40000000 - 0x4fffffff - PCI Memory 67 * 0x50000000 - 0x50ffffff - PCI IO Space 68 */ 69#ifdef CONFIG_AEVFIFO 70#define CONFIG_PCI 1 71#define CONFIG_PCI_PNP 1 72/* #define CONFIG_PCI_SCAN_SHOW 1 */ 73#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 74 75#define CONFIG_PCI_MEM_BUS 0x40000000 76#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 77#define CONFIG_PCI_MEM_SIZE 0x10000000 78 79#define CONFIG_PCI_IO_BUS 0x50000000 80#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 81#define CONFIG_PCI_IO_SIZE 0x01000000 82 83#define CONFIG_NET_MULTI 1 84#define CONFIG_EEPRO100 1 85#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ 86#define CONFIG_NS8382X 1 87#endif /* CONFIG_AEVFIFO */ 88 89/* Partitions */ 90#define CONFIG_MAC_PARTITION 91#define CONFIG_DOS_PARTITION 92#define CONFIG_ISO_PARTITION 93 94/* POST support */ 95#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ 96 CONFIG_SYS_POST_CPU | \ 97 CONFIG_SYS_POST_I2C) 98 99#ifdef CONFIG_POST 100/* preserve space for the post_word at end of on-chip SRAM */ 101#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 102#endif 103 104 105/* 106 * BOOTP options 107 */ 108#define CONFIG_BOOTP_BOOTFILESIZE 109#define CONFIG_BOOTP_BOOTPATH 110#define CONFIG_BOOTP_GATEWAY 111#define CONFIG_BOOTP_HOSTNAME 112 113 114/* 115 * Command line configuration. 116 */ 117#include <config_cmd_default.h> 118 119#define CONFIG_CMD_ASKENV 120#define CONFIG_CMD_DATE 121#define CONFIG_CMD_DHCP 122#define CONFIG_CMD_ECHO 123#define CONFIG_CMD_EEPROM 124#define CONFIG_CMD_I2C 125#define CONFIG_CMD_MII 126#define CONFIG_CMD_NFS 127#define CONFIG_CMD_PCI 128#define CONFIG_CMD_PING 129#define CONFIG_CMD_REGINFO 130#define CONFIG_CMD_SNTP 131 132#ifdef CONFIG_POST 133#define CONFIG_CMD_DIAG 134#endif 135 136 137#define CONFIG_TIMESTAMP /* display image timestamps */ 138 139#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */ 140# define CONFIG_SYS_LOWBOOT 1 141#endif 142 143/* 144 * Autobooting 145 */ 146#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 147 148#define CONFIG_PREBOOT "echo;" \ 149 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 150 "echo" 151 152#undef CONFIG_BOOTARGS 153 154#define CONFIG_EXTRA_ENV_SETTINGS \ 155 "netdev=eth0\0" \ 156 "rootpath=/opt/eldk/ppc_6xx\0" \ 157 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 158 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 159 "nfsroot=${serverip}:${rootpath} " \ 160 "console=ttyS0,${baudrate}\0" \ 161 "addip=setenv bootargs ${bootargs} " \ 162 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 163 ":${hostname}:${netdev}:off panic=1\0" \ 164 "flash_self=run ramargs addip;" \ 165 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 166 "flash_nfs=run nfsargs addip;" \ 167 "bootm ${kernel_addr}\0" \ 168 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 169 "bootfile=/tftpboot/tqm5200/uImage\0" \ 170 "load=tftp 200000 ${u-boot}\0" \ 171 "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \ 172 "update=protect off FC000000 FC05FFFF;" \ 173 "erase FC000000 FC05FFFF;" \ 174 "cp.b 200000 FC000000 ${filesize};" \ 175 "protect on FC000000 FC05FFFF\0" \ 176 "" 177 178#define CONFIG_BOOTCOMMAND "run net_nfs" 179 180/* 181 * IPB Bus clocking configuration. 182 */ 183#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ 184 185#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) 186/* 187 * PCI Bus clocking configuration 188 * 189 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if 190 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock 191 * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. 192 */ 193#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ 194#endif 195 196/* 197 * I2C configuration 198 */ 199#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ 200#ifdef CONFIG_TQM5200_REV100 201#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */ 202#else 203#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */ 204#endif 205 206/* 207 * I2C clock frequency 208 * 209 * Please notice, that the resulting clock frequency could differ from the 210 * configured value. This is because the I2C clock is derived from system 211 * clock over a frequency divider with only a few divider values. U-boot 212 * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated 213 * approximation allways lies below the configured value, never above. 214 */ 215#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ 216#define CONFIG_SYS_I2C_SLAVE 0x7F 217 218/* 219 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work 220 * also). For other EEPROMs configuration should be verified. On Mini-FAP the 221 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the 222 * same configuration could be used. 223 */ 224#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ 225#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 226#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ 227#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 228 229/* 230 * Flash configuration 231 */ 232#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */ 233 234/* use CFI flash driver if no module variant is spezified */ 235#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 236#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 237#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START } 238#define CONFIG_SYS_FLASH_EMPTY_INFO 239#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */ 240#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ 241#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ 242 243#if !defined(CONFIG_SYS_LOWBOOT) 244#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000) 245#else /* CONFIG_SYS_LOWBOOT */ 246#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) 247#endif /* CONFIG_SYS_LOWBOOT */ 248#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks 249 (= chip selects) */ 250#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ 251#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ 252 253 254/* 255 * Environment settings 256 */ 257#define CONFIG_ENV_IS_IN_FLASH 1 258#define CONFIG_ENV_SIZE 0x10000 259#define CONFIG_ENV_SECT_SIZE 0x20000 260#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 261#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 262 263/* 264 * Memory map 265 */ 266#define CONFIG_SYS_MBAR 0xF0000000 267#define CONFIG_SYS_SDRAM_BASE 0x00000000 268#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 269 270/* Use ON-Chip SRAM until RAM will be available */ 271#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM 272#ifdef CONFIG_POST 273/* preserve space for the post_word at end of on-chip SRAM */ 274#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE 275#else 276#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE 277#endif 278 279 280#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 281#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 282 283#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 284#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 285# define CONFIG_SYS_RAMBOOT 1 286#endif 287 288#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ 289#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 290#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 291 292/* 293 * Ethernet configuration 294 */ 295#define CONFIG_MPC5xxx_FEC 1 296#define CONFIG_MPC5xxx_FEC_MII100 297/* 298 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb 299 */ 300/* #define CONFIG_MPC5xxx_FEC_MII10 */ 301#define CONFIG_PHY_ADDR 0x00 302 303/* 304 * GPIO configuration 305 * 306 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): 307 * Bit 0 (mask: 0x80000000): 1 308 * use ALT CAN position: Bits 2-3 (mask: 0x30000000): 309 * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. 310 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. 311 * Use for REV200 STK52XX boards. Do not use with REV100 modules 312 * (because, there I2C1 is used as I2C bus) 313 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 314 * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) 315 * 000 -> All PSC2 pins are GIOPs 316 * 001 -> CAN1/2 on PSC2 pins 317 * Use for REV100 STK52xx boards 318 * use PSC6: 319 * on STK52xx: 320 * use as UART. Pins PSC6_0 to PSC6_3 are used. 321 * Bits 9:11 (mask: 0x00700000): 322 * 101 -> PSC6 : Extended POST test is not available 323 * on MINI-FAP and TQM5200_IB: 324 * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000): 325 * 000 -> PSC6 could not be used as UART, CODEC or IrDA 326 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST 327 * tests. 328 */ 329#define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014 330 331/* 332 * RTC configuration 333 */ 334#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ 335 336/* 337 * Miscellaneous configurable options 338 */ 339#define CONFIG_SYS_LONGHELP /* undef to save memory */ 340#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 341#if defined(CONFIG_CMD_KGDB) 342#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 343#else 344#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 345#endif 346#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 347#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 348#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 349 350/* Enable an alternate, more extensive memory test */ 351#define CONFIG_SYS_ALT_MEMTEST 352 353#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 354#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ 355 356#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 357 358#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 359 360#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ 361#if defined(CONFIG_CMD_KGDB) 362# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 363#endif 364 365/* 366 * Enable loopw command. 367 */ 368#define CONFIG_LOOPW 369 370/* 371 * Various low-level settings 372 */ 373#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI 374#define CONFIG_SYS_HID0_FINAL HID0_ICE 375 376#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE 377#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE 378#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 379#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ 380#else 381#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ 382#endif 383#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE 384#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE 385 386#define CONFIG_LAST_STAGE_INIT 387 388/* 389 * SRAM - Do not map below 2 GB in address space, because this area is used 390 * for SDRAM autosizing. 391 */ 392#define CONFIG_SYS_CS2_START 0xE5000000 393#define CONFIG_SYS_CS2_SIZE 0x80000 /* 512 kByte */ 394#define CONFIG_SYS_CS2_CFG 0x0004D930 395 396/* 397 * Grafic controller - Do not map below 2 GB in address space, because this 398 * area is used for SDRAM autosizing. 399 */ 400#define SM501_FB_BASE 0xE0000000 401#define CONFIG_SYS_CS1_START (SM501_FB_BASE) 402#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */ 403#define CONFIG_SYS_CS1_CFG 0x8F48FF70 404#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000 405 406#define CONFIG_SYS_CS_BURST 0x00000000 407#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ 408 409#define CONFIG_SYS_RESET_ADDRESS 0xff000000 410 411#endif /* __CONFIG_H */ 412