1/* 2 * U-boot - Configuration file for BF537 STAMP board 3 */ 4 5#ifndef __CONFIG_BF537_STAMP_H__ 6#define __CONFIG_BF537_STAMP_H__ 7 8#include <asm/config-pre.h> 9 10 11/* 12 * Processor Settings 13 */ 14#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS 15 16 17/* 18 * Clock Settings 19 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV 20 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV 21 */ 22/* CONFIG_CLKIN_HZ is any value in Hz */ 23#define CONFIG_CLKIN_HZ 25000000 24/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ 25/* 1 = CLKIN / 2 */ 26#define CONFIG_CLKIN_HALF 0 27/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ 28/* 1 = bypass PLL */ 29#define CONFIG_PLL_BYPASS 0 30/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ 31/* Values can range from 0-63 (where 0 means 64) */ 32#define CONFIG_VCO_MULT 20 33/* CCLK_DIV controls the core clock divider */ 34/* Values can be 1, 2, 4, or 8 ONLY */ 35#define CONFIG_CCLK_DIV 1 36/* SCLK_DIV controls the system clock divider */ 37/* Values can range from 1-15 */ 38#define CONFIG_SCLK_DIV 4 39 40 41/* 42 * Memory Settings 43 */ 44#define CONFIG_MEM_ADD_WDTH 10 45#define CONFIG_MEM_SIZE 64 46 47#define CONFIG_EBIU_SDRRC_VAL 0x306 48#define CONFIG_EBIU_SDGCTL_VAL 0x91114d 49 50#define CONFIG_EBIU_AMGCTL_VAL 0xFF 51#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 52#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 53 54#define CONFIG_SYS_MONITOR_LEN (512 * 1024) 55#define CONFIG_SYS_MALLOC_LEN (384 * 1024) 56 57 58/* 59 * Network Settings 60 */ 61#ifndef __ADSPBF534__ 62#define ADI_CMDS_NETWORK 1 63#define CONFIG_BFIN_MAC 64#define CONFIG_NETCONSOLE 1 65#define CONFIG_NET_MULTI 1 66#endif 67#define CONFIG_HOSTNAME bf537-stamp 68/* Uncomment next line to use fixed MAC address */ 69/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ 70 71 72/* 73 * Flash Settings 74 */ 75#define CONFIG_FLASH_CFI_DRIVER 76#define CONFIG_SYS_FLASH_BASE 0x20000000 77#define CONFIG_SYS_FLASH_CFI 78#define CONFIG_SYS_FLASH_PROTECTION 79#define CONFIG_SYS_MAX_FLASH_BANKS 1 80/* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */ 81#define CONFIG_SYS_MAX_FLASH_SECT 71 82 83 84/* 85 * SPI Settings 86 */ 87#define CONFIG_BFIN_SPI 88#define CONFIG_ENV_SPI_MAX_HZ 30000000 89#define CONFIG_SF_DEFAULT_SPEED 30000000 90#define CONFIG_SPI_FLASH 91#define CONFIG_SPI_FLASH_ALL 92 93 94/* 95 * Env Storage Settings 96 */ 97#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) 98#define CONFIG_ENV_IS_IN_SPI_FLASH 99#define CONFIG_ENV_OFFSET 0x10000 100#define CONFIG_ENV_SIZE 0x2000 101#define CONFIG_ENV_SECT_SIZE 0x10000 102#else 103#define CONFIG_ENV_IS_IN_FLASH 104#define CONFIG_ENV_OFFSET 0x4000 105#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) 106#define CONFIG_ENV_SIZE 0x2000 107#define CONFIG_ENV_SECT_SIZE 0x2000 108#endif 109#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) 110#define ENV_IS_EMBEDDED 111#else 112#define CONFIG_ENV_IS_EMBEDDED_IN_LDR 113#endif 114#ifdef ENV_IS_EMBEDDED 115/* WARNING - the following is hand-optimized to fit within 116 * the sector before the environment sector. If it throws 117 * an error during compilation remove an object here to get 118 * it linked after the configuration sector. 119 */ 120# define LDS_BOARD_TEXT \ 121 arch/blackfin/lib/libblackfin.o (.text*); \ 122 arch/blackfin/cpu/libblackfin.o (.text*); \ 123 . = DEFINED(env_offset) ? env_offset : .; \ 124 common/env_embedded.o (.text*); 125#endif 126 127 128/* 129 * I2C Settings 130 */ 131#define CONFIG_BFIN_TWI_I2C 1 132#define CONFIG_HARD_I2C 1 133 134 135/* 136 * SPI_MMC Settings 137 */ 138#define CONFIG_MMC 139#define CONFIG_SPI_MMC 140 141 142/* 143 * NAND Settings 144 */ 145/* #define CONFIG_NAND_PLAT */ 146#define CONFIG_SYS_NAND_BASE 0x20212000 147#define CONFIG_SYS_MAX_NAND_DEVICE 1 148 149#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) 150#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) 151#define BFIN_NAND_WRITE(addr, cmd) \ 152 do { \ 153 bfin_write8(addr, cmd); \ 154 SSYNC(); \ 155 } while (0) 156 157#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) 158#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) 159#define NAND_PLAT_GPIO_DEV_READY GPIO_PF3 160 161 162/* 163 * CF-CARD IDE-HDD Support 164 */ 165 166/* 167 * Add CF flash card support in TRUE-IDE Mode (CF-IDE-NAND Card) 168 * Strange address mapping Blackfin A13 connects to CF_A0 169 */ 170 171/* #define CONFIG_BFIN_TRUE_IDE */ 172 173/* 174 * Add CF flash card support in Common Memory Mode (CF-IDE-NAND Card) 175 * This should be the preferred mode 176 */ 177 178/* #define CONFIG_BFIN_CF_IDE */ 179 180/* 181 * Add IDE Disk Drive (HDD) support 182 * See example interface here: 183 * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:ide-blackfin 184 */ 185 186/* #define CONFIG_BFIN_HDD_IDE */ 187 188#if defined(CONFIG_BFIN_CF_IDE) || \ 189 defined(CONFIG_BFIN_HDD_IDE) || \ 190 defined(CONFIG_BFIN_TRUE_IDE) 191# define CONFIG_BFIN_IDE 1 192# define CONFIG_CMD_IDE 193#endif 194 195#if defined(CONFIG_BFIN_IDE) 196 197#define CONFIG_DOS_PARTITION 1 198/* 199 * IDE/ATA stuff 200 */ 201#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ 202#undef CONFIG_IDE_LED /* no led for ide supported */ 203#undef CONFIG_IDE_RESET /* no reset for ide supported */ 204 205#define CONFIG_SYS_IDE_MAXBUS 1 206#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1) 207 208#undef CONFIG_EBIU_AMBCTL1_VAL 209#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC3FFC3 210 211#define CONFIG_CF_ATASEL_DIS 0x20311800 212#define CONFIG_CF_ATASEL_ENA 0x20311802 213 214#if defined(CONFIG_BFIN_TRUE_IDE) 215/* 216 * Note that these settings aren't for the most part used in include/ata.h 217 * when all of the ATA registers are setup 218 */ 219#define CONFIG_SYS_ATA_BASE_ADDR 0x2031C000 220#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 221#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */ 222#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */ 223#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */ 224#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A13 */ 225 226#elif defined(CONFIG_BFIN_CF_IDE) 227#define CONFIG_SYS_ATA_BASE_ADDR 0x20211800 228#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 229#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* data I/O */ 230#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* normal register accesses */ 231#define CONFIG_SYS_ATA_ALT_OFFSET 0x000E /* alternate registers */ 232#define CONFIG_SYS_ATA_STRIDE 1 /* CF_A0=0, with /CE1 /CE2 odd/even byte selects */ 233 234#elif defined(CONFIG_BFIN_HDD_IDE) 235#define CONFIG_SYS_ATA_BASE_ADDR 0x20314000 236#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 237#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */ 238#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */ 239#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */ 240#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */ 241#undef CONFIG_SCLK_DIV 242#define CONFIG_SCLK_DIV 8 243#endif 244 245#endif 246 247 248/* 249 * Misc Settings 250 */ 251#define CONFIG_MISC_INIT_R 252#define CONFIG_RTC_BFIN 253#define CONFIG_UART_CONSOLE 0 254 255/* Define if want to do post memory test */ 256#undef CONFIG_POST 257#ifdef CONFIG_POST 258#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */ 259#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */ 260#endif 261#define CONFIG_SYS_POST_WORD_ADDR 0xFF903FFC 262 263/* These are for board tests */ 264#if 0 265#define CONFIG_BOOTCOMMAND "bootldr 0x203f0100" 266#define CONFIG_AUTOBOOT_KEYED 267#define CONFIG_AUTOBOOT_PROMPT \ 268 "autoboot in %d seconds: press space to stop\n", bootdelay 269#define CONFIG_AUTOBOOT_STOP_STR " " 270#endif 271 272 273/* 274 * Pull in common ADI header for remaining command/environment setup 275 */ 276#include <configs/bfin_adi_common.h> 277 278#endif 279