1/* 2 * (C) Copyright 2000 3 * Murray Jensen <Murray.Jensen@cmst.csiro.au> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * Config header file for Hymod board 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31/* 32 * High Level Configuration Options 33 * (easy to change) 34 */ 35 36#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ 37#define CONFIG_HYMOD 1 /* ...on a Hymod board */ 38#define CONFIG_CPM2 1 /* Has a CPM2 */ 39 40#define CONFIG_SYS_TEXT_BASE 0x40000000 41 42#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ 43 44#define CONFIG_BOARD_POSTCLK_INIT /* have board_postclk_init() function */ 45 46/* 47 * select serial console configuration 48 * 49 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then 50 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 51 * for SCC). 52 * 53 * if CONFIG_CONS_NONE is defined, then the serial console routines must 54 * defined elsewhere (for example, on the cogent platform, there are serial 55 * ports on the motherboard which are used for the serial console - see 56 * cogent/cma101/serial.[ch]). 57 */ 58#undef CONFIG_CONS_ON_SMC /* define if console on SMC */ 59#define CONFIG_CONS_ON_SCC /* define if console on SCC */ 60#undef CONFIG_CONS_NONE /* define if console on something else*/ 61#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ 62#define CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ 63#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ 64#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/ 65 66/* 67 * select ethernet configuration 68 * 69 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then 70 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 71 * for FCC) 72 * 73 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be 74 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. 75 */ 76#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ 77#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ 78#undef CONFIG_ETHER_NONE /* define if ether on something else */ 79#define CONFIG_ETHER_INDEX 1 /* which channel for ether */ 80#define CONFIG_ETHER_LOOPBACK_TEST /* add ether external loopback test */ 81 82#ifdef CONFIG_ETHER_ON_FCC 83 84#if (CONFIG_ETHER_INDEX == 1) 85 86/* 87 * - Rx-CLK is CLK10 88 * - Tx-CLK is CLK11 89 * - RAM for BD/Buffers is on the 60x Bus (see 28-13) 90 * - Enable Full Duplex in FSMR 91 */ 92# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) 93# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11) 94# define CONFIG_SYS_CPMFCR_RAMTYPE 0 95# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) 96 97# define MDIO_PORT 0 /* Port A */ 98# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ 99 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) 100# define MDC_DECLARE MDIO_DECLARE 101 102# define MDIO_DATA_PINMASK 0x00040000 /* Pin 13 */ 103# define MDIO_CLCK_PINMASK 0x00080000 /* Pin 12 */ 104 105#elif (CONFIG_ETHER_INDEX == 2) 106 107/* 108 * - Rx-CLK is CLK13 109 * - Tx-CLK is CLK14 110 * - RAM for BD/Buffers is on the 60x Bus (see 28-13) 111 * - Enable Full Duplex in FSMR 112 */ 113# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) 114# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) 115# define CONFIG_SYS_CPMFCR_RAMTYPE 0 116# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) 117 118# define MDIO_PORT 0 /* Port A */ 119# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ 120 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) 121# define MDC_DECLARE MDIO_DECLARE 122 123# define MDIO_DATA_PINMASK 0x00000040 /* Pin 25 */ 124# define MDIO_CLCK_PINMASK 0x00000080 /* Pin 24 */ 125 126#elif (CONFIG_ETHER_INDEX == 3) 127 128/* 129 * - Rx-CLK is CLK15 130 * - Tx-CLK is CLK16 131 * - RAM for BD/Buffers is on the 60x Bus (see 28-13) 132 * - Enable Full Duplex in FSMR 133 */ 134# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK) 135# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16) 136# define CONFIG_SYS_CPMFCR_RAMTYPE 0 137# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) 138 139# define MDIO_PORT 0 /* Port A */ 140# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ 141 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) 142# define MDC_DECLARE MDIO_DECLARE 143 144# define MDIO_DATA_PINMASK 0x00000100 /* Pin 23 */ 145# define MDIO_CLCK_PINMASK 0x00000200 /* Pin 22 */ 146 147#endif /* CONFIG_ETHER_INDEX */ 148 149#define CONFIG_MII /* MII PHY management */ 150#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 151 152#define MDIO_ACTIVE (iop->pdir |= MDIO_DATA_PINMASK) 153#define MDIO_TRISTATE (iop->pdir &= ~MDIO_DATA_PINMASK) 154#define MDIO_READ ((iop->pdat & MDIO_DATA_PINMASK) != 0) 155 156#define MDIO(bit) if(bit) iop->pdat |= MDIO_DATA_PINMASK; \ 157 else iop->pdat &= ~MDIO_DATA_PINMASK 158 159#define MDC(bit) if(bit) iop->pdat |= MDIO_CLCK_PINMASK; \ 160 else iop->pdat &= ~MDIO_CLCK_PINMASK 161 162#define MIIDELAY udelay(1) 163 164#endif /* CONFIG_ETHER_ON_FCC */ 165 166 167/* other options */ 168#define CONFIG_HARD_I2C 1 /* To enable I2C hardware support */ 169#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */ 170 171/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ 172#ifdef DEBUG 173#define CONFIG_8260_CLKIN 33333333 /* in Hz */ 174#else 175#define CONFIG_8260_CLKIN 66666666 /* in Hz */ 176#endif 177 178#if defined(CONFIG_CONS_USE_EXTC) 179#define CONFIG_BAUDRATE 115200 180#else 181#define CONFIG_BAUDRATE 9600 182#endif 183 184/* default ip addresses - these will be overridden */ 185#define CONFIG_IPADDR 192.168.1.1 /* hymod "boot" address */ 186#define CONFIG_SERVERIP 192.168.1.254 /* hymod "server" address */ 187 188#define CONFIG_LAST_STAGE_INIT 189 190/* 191 * BOOTP options 192 */ 193#define CONFIG_BOOTP_BOOTFILESIZE 194#define CONFIG_BOOTP_BOOTPATH 195#define CONFIG_BOOTP_GATEWAY 196#define CONFIG_BOOTP_HOSTNAME 197 198 199/* 200 * Command line configuration. 201 */ 202#include <config_cmd_default.h> 203 204#define CONFIG_CMD_ASKENV 205#define CONFIG_CMD_BSP 206#define CONFIG_CMD_CACHE 207#define CONFIG_CMD_CDP 208#define CONFIG_CMD_DATE 209#define CONFIG_CMD_DHCP 210#define CONFIG_CMD_DIAG 211#define CONFIG_CMD_DTT 212#define CONFIG_CMD_EEPROM 213#define CONFIG_CMD_ELF 214#define CONFIG_CMD_FAT 215#define CONFIG_CMD_I2C 216#define CONFIG_CMD_IMMAP 217#define CONFIG_CMD_IRQ 218#define CONFIG_CMD_KGDB 219#define CONFIG_CMD_MII 220#define CONFIG_CMD_PING 221#define CONFIG_CMD_PORTIO 222#define CONFIG_CMD_REGINFO 223#define CONFIG_CMD_SAVES 224#define CONFIG_CMD_SDRAM 225#define CONFIG_CMD_SNTP 226 227#undef CONFIG_CMD_FPGA 228#undef CONFIG_CMD_XIMG 229 230#ifdef DEBUG 231#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 232#else 233#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 234#define CONFIG_BOOT_RETRY_TIME 30 /* retry autoboot after 30 secs */ 235#define CONFIG_BOOT_RETRY_MIN 1 /* can go down to 1 second timeout */ 236/* Be selective on what keys can delay or stop the autoboot process 237 * To stop use: " " 238 */ 239#define CONFIG_AUTOBOOT_KEYED 240#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \ 241 "press <SPACE> to stop\n", bootdelay 242#define CONFIG_AUTOBOOT_STOP_STR " " 243#undef CONFIG_AUTOBOOT_DELAY_STR 244#define DEBUG_BOOTKEYS 0 245#endif 246 247#if defined(CONFIG_CMD_KGDB) 248#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ 249#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ 250#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ 251#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ 252#define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ 253#define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */ 254#define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/ 255# if defined(CONFIG_KGDB_USE_EXTC) 256#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ 257# else 258#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */ 259# endif 260#endif 261 262#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ 263 264#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ 265 266/* 267 * Hymod specific configurable options 268 */ 269#undef CONFIG_SYS_HYMOD_DBLEDS /* walk mezz board LEDs */ 270 271/* 272 * Miscellaneous configurable options 273 */ 274#define CONFIG_SYS_LONGHELP /* undef to save memory */ 275#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 276#if defined(CONFIG_CMD_KGDB) 277#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 278#else 279#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 280#endif 281#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 282#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 283#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 284 285#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ 286#define CONFIG_SYS_MEMTEST_END 0x03c00000 /* 4 ... 60 MB in DRAM */ 287 288#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 289 290#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 291 292#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 293 294#define CONFIG_SYS_I2C_SPEED 50000 295#define CONFIG_SYS_I2C_SLAVE 0x7e 296 297/* these are for the ST M24C02 2kbit serial i2c eeprom */ 298#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */ 299#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ 300/* mask of address bits that overflow into the "EEPROM chip address" */ 301#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 302 303#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16 byte write page size */ 304#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 305 306#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* hymod has two eeproms */ 307 308#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* philips PCF8563 RTC address */ 309 310/* 311 * standard dtt sensor configuration - bottom bit will determine local or 312 * remote sensor of the ADM1021, the rest determines index into 313 * CONFIG_SYS_DTT_ADM1021 array below. 314 * 315 * On HYMOD board, the remote sensor should be connected to the MPC8260 316 * temperature diode thingy, but an errata said this didn't work and 317 * should be disabled - so it isn't connected. 318 */ 319#if 0 320#define CONFIG_DTT_SENSORS { 0, 1 } 321#else 322#define CONFIG_DTT_SENSORS { 0 } 323#endif 324 325/* 326 * ADM1021 temp sensor configuration (see dtt/adm1021.c for details). 327 * there will be one entry in this array for each two (dummy) sensors in 328 * CONFIG_DTT_SENSORS. 329 * 330 * For HYMOD board: 331 * - only one ADM1021 332 * - i2c addr 0x2a (both ADD0 and ADD1 are N/C) 333 * - conversion rate 0x02 = 0.25 conversions/second 334 * - ALERT ouput disabled 335 * - local temp sensor enabled, min set to 0 deg, max set to 85 deg 336 * - remote temp sensor disabled (see comment for CONFIG_DTT_SENSORS above) 337 */ 338#define CONFIG_SYS_DTT_ADM1021 { { 0x2a, 0x02, 0, 1, 0, 85, 0, } } 339 340/* 341 * Low Level Configuration Settings 342 * (address mappings, register initial values, etc.) 343 * You should know what you are doing if you make changes here. 344 */ 345 346/*----------------------------------------------------------------------- 347 * Hard Reset Configuration Words 348 * 349 * if you change bits in the HRCW, you must also change the CONFIG_SYS_* 350 * defines for the various registers affected by the HRCW e.g. changing 351 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. 352 */ 353#ifdef DEBUG 354#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\ 355 HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\ 356 HRCW_MODCK_H0010) 357#else 358#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\ 359 HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\ 360 HRCW_MODCK_H0101) 361#endif 362/* no slaves so just duplicate the master hrcw */ 363#define CONFIG_SYS_HRCW_SLAVE1 CONFIG_SYS_HRCW_MASTER 364#define CONFIG_SYS_HRCW_SLAVE2 CONFIG_SYS_HRCW_MASTER 365#define CONFIG_SYS_HRCW_SLAVE3 CONFIG_SYS_HRCW_MASTER 366#define CONFIG_SYS_HRCW_SLAVE4 CONFIG_SYS_HRCW_MASTER 367#define CONFIG_SYS_HRCW_SLAVE5 CONFIG_SYS_HRCW_MASTER 368#define CONFIG_SYS_HRCW_SLAVE6 CONFIG_SYS_HRCW_MASTER 369#define CONFIG_SYS_HRCW_SLAVE7 CONFIG_SYS_HRCW_MASTER 370 371/*----------------------------------------------------------------------- 372 * Internal Memory Mapped Register 373 */ 374#define CONFIG_SYS_IMMR 0xF0000000 375 376/*----------------------------------------------------------------------- 377 * Definitions for initial stack pointer and data area (in DPRAM) 378 */ 379#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 380#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */ 381#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 382#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 383 384/*----------------------------------------------------------------------- 385 * Start addresses for the final memory configuration 386 * (Set up by the startup code) 387 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 388 */ 389#define CONFIG_SYS_SDRAM_BASE 0x00000000 390#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE 391#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 392#define CONFIG_SYS_FPGA_BASE 0x80000000 393/* 394 * unfortunately, CONFIG_SYS_MONITOR_LEN must include the 395 * (very large i.e. 256kB) environment flash sector 396 */ 397#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor*/ 398#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ 399 400/* 401 * For booting Linux, the board info and command line data 402 * have to be in the first 8 MB of memory, since this is 403 * the maximum mapped by the Linux kernel during initialization. 404 */ 405#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ 406 407/*----------------------------------------------------------------------- 408 * FLASH organization 409 */ 410#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */ 411#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */ 412 413#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */ 414#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ 415 416#define CONFIG_ENV_IS_IN_FLASH 1 417#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */ 418#define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sect real size */ 419#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-CONFIG_ENV_SECT_SIZE) 420#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 421 422/*----------------------------------------------------------------------- 423 * Cache Configuration 424 */ 425#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ 426#if defined(CONFIG_CMD_KGDB) 427#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ 428#endif 429 430/*----------------------------------------------------------------------- 431 * HIDx - Hardware Implementation-dependent Registers 2-11 432 *----------------------------------------------------------------------- 433 * HID0 also contains cache control - initially enable both caches and 434 * invalidate contents, then the final state leaves only the instruction 435 * cache enabled. Note that Power-On and Hard reset invalidate the caches, 436 * but Soft reset does not. 437 * 438 * HID1 has only read-only information - nothing to set. 439 */ 440#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ 441 HID0_IFEM|HID0_ABE) 442#ifdef DEBUG 443#define CONFIG_SYS_HID0_FINAL 0 444#else 445#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) 446#endif 447#define CONFIG_SYS_HID2 0 448 449/*----------------------------------------------------------------------- 450 * RMR - Reset Mode Register 5-5 451 *----------------------------------------------------------------------- 452 * turn on Checkstop Reset Enable 453 */ 454#ifdef DEBUG 455#define CONFIG_SYS_RMR 0 456#else 457#define CONFIG_SYS_RMR RMR_CSRE 458#endif 459 460/*----------------------------------------------------------------------- 461 * BCR - Bus Configuration 4-25 462 *----------------------------------------------------------------------- 463 */ 464#define CONFIG_SYS_BCR (BCR_ETM) 465 466/*----------------------------------------------------------------------- 467 * SIUMCR - SIU Module Configuration 4-31 468 *----------------------------------------------------------------------- 469 */ 470#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_L2CPC01|\ 471 SIUMCR_APPC10|SIUMCR_MMR11) 472 473/*----------------------------------------------------------------------- 474 * SYPCR - System Protection Control 4-35 475 * SYPCR can only be written once after reset! 476 *----------------------------------------------------------------------- 477 * Watchdog & Bus Monitor Timer max, 60x & Local Bus Monitor enable 478 */ 479#if defined(CONFIG_WATCHDOG) 480#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 481 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) 482#else 483#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 484 SYPCR_SWRI|SYPCR_SWP) 485#endif /* CONFIG_WATCHDOG */ 486 487/*----------------------------------------------------------------------- 488 * TMCNTSC - Time Counter Status and Control 4-40 489 *----------------------------------------------------------------------- 490 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, 491 * and enable Time Counter 492 */ 493#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) 494 495/*----------------------------------------------------------------------- 496 * PISCR - Periodic Interrupt Status and Control 4-42 497 *----------------------------------------------------------------------- 498 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable 499 * Periodic timer 500 */ 501#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) 502 503/*----------------------------------------------------------------------- 504 * SCCR - System Clock Control 9-8 505 *----------------------------------------------------------------------- 506 * Ensure DFBRG is Divide by 16 507 */ 508#define CONFIG_SYS_SCCR (SCCR_DFBRG01) 509 510/*----------------------------------------------------------------------- 511 * RCCR - RISC Controller Configuration 13-7 512 *----------------------------------------------------------------------- 513 */ 514#define CONFIG_SYS_RCCR 0 515 516/* 517 * Init Memory Controller: 518 * 519 * Bank Bus Machine PortSz Device 520 * ---- --- ------- ------ ------ 521 * 0 60x GPCM 32 bit FLASH 522 * 1 60x GPCM 32 bit FLASH (same as 0 - unused for now) 523 * 2 60x SDRAM 64 bit SDRAM 524 * 3 Local UPMC 8 bit Main Xilinx configuration 525 * 4 Local GPCM 32 bit Main Xilinx register mode 526 * 5 Local UPMB 32 bit Main Xilinx port mode 527 * 6 Local UPMC 8 bit Mezz Xilinx configuration 528 */ 529 530/* 531 * Bank 0 - FLASH 532 * 533 * Quotes from the HYMOD IO Board Reference manual: 534 * 535 * "The flash memory is two Intel StrataFlash chips, each configured for 536 * 16 bit operation and connected to give a 32 bit wide port." 537 * 538 * "The chip select logic is configured to respond to both *CS0 and *CS1. 539 * Therefore the FLASH memory will be mapped to both bank 0 and bank 1. 540 * It is suggested that bank 0 be read-only and bank 1 be read/write. The 541 * FLASH will then appear as ROM during boot." 542 * 543 * Initially, we are only going to use bank 0 in read/write mode. 544 */ 545 546/* 32 bit, read-write, GPCM on 60x bus */ 547#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE&BRx_BA_MSK)|\ 548 BRx_PS_32|BRx_MS_GPCM_P|BRx_V) 549/* up to 32 Mb */ 550#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(32)|ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK) 551 552/* 553 * Bank 2 - SDRAM 554 * 555 * Quotes from the HYMOD IO Board Reference manual: 556 * 557 * "The main memory is implemented using TC59SM716FTL-10 SDRAM and has a 558 * fixed size of 64 Mbytes. The Toshiba TC59SM716FTL-10 is a CMOS synchronous 559 * dynamic random access memory organised as 4 banks by 4096 rows by 512 560 * columns by 16 bits. Four chips provide a 64-bit port on the 60x bus." 561 * 562 * "The locations in SDRAM are accessed using multiplexed address pins to 563 * specify row and column. The pins also act to specify commands. The state 564 * of the inputs *RAS, *CAS and *WE defines the required action. The a10/AP 565 * pin may function as a row address or as the AUTO PRECHARGE control line, 566 * depending on the cycle type. The 60x bus SDRAM machine allows the MPC8260 567 * address lines to be configured to the required multiplexing scheme." 568 */ 569 570#define CONFIG_SYS_SDRAM_SIZE 64 571 572/* 64 bit, read-write, SDRAM on 60x bus */ 573#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE&BRx_BA_MSK)|\ 574 BRx_PS_64|BRx_MS_SDRAM_P|BRx_V) 575/* 64 Mb, 4 int banks per dev, row start addr bit = A6, 12 row addr lines */ 576#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM_SIZE)|\ 577 ORxS_BPD_4|ORxS_ROWST_PBI1_A6|ORxS_NUMR_12) 578 579/* 580 * The 60x Bus SDRAM Mode Register (PDSMR) is set as follows: 581 * 582 * Page Based Interleaving, Refresh Enable, Address Multiplexing where A5 583 * is output on A16 pin (A6 on A17, and so on), use address pins A14-A16 584 * as bank select, A7 is output on SDA10 during an ACTIVATE command, 585 * earliest timing for ACTIVATE command after REFRESH command is 6 clocks, 586 * earliest timing for ACTIVATE or REFRESH command after PRECHARGE command 587 * is 2 clocks, earliest timing for READ/WRITE command after ACTIVATE 588 * command is 2 clocks, earliest timing for PRECHARGE after last data 589 * was read is 1 clock, earliest timing for PRECHARGE after last data 590 * was written is 1 clock, CAS Latency is 2. 591 */ 592 593#define CONFIG_SYS_PSDMR (PSDMR_PBI|PSDMR_SDAM_A16_IS_A5|\ 594 PSDMR_BSMA_A14_A16|PSDMR_SDA10_PBI1_A7|\ 595 PSDMR_RFRC_6_CLK|PSDMR_PRETOACT_2W|\ 596 PSDMR_ACTTORW_2W|PSDMR_LDOTOPRE_1C|\ 597 PSDMR_WRC_1C|PSDMR_CL_2) 598 599/* 600 * The 60x bus-assigned SDRAM Refresh Timer (PSRT) (10-31) and the Refresh 601 * Timers Prescale (PTP) value in the Memory Refresh Timer Prescaler Register 602 * (MPTPR) (10-32) must also be set up (it used to be called the Periodic Timer 603 * Prescaler, hence the P instead of the R). The refresh timer period is given 604 * by (note that there was a change in the 8260 UM Errata): 605 * 606 * TimerPeriod = (PSRT + 1) / Fmptc 607 * 608 * where Fmptc is the BusClock divided by PTP. i.e. 609 * 610 * TimerPeriod = (PSRT + 1) / (BusClock / PTP) 611 * 612 * or 613 * 614 * TImerPeriod = (PTP * (PSRT + 1)) / BusClock 615 * 616 * The requirement for the Toshiba TC59SM716FTL-10 is that there must be 617 * 4K refresh cycles every 64 ms. i.e. one refresh cycle every 64000/4096 618 * = 15.625 usecs. 619 * 620 * So PTP * (PSRT + 1) <= 15.625 * BusClock. At 66.666MHz, PSRT=31 and PTP=32 621 * appear to be reasonable. 622 */ 623 624#ifdef DEBUG 625#define CONFIG_SYS_PSRT 39 626#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV8 627#else 628#define CONFIG_SYS_PSRT 31 629#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32 630#endif 631 632/* 633 * Banks 3,4,5 and 6 - FPGA access 634 * 635 * Quotes from the HYMOD IO Board Reference manual: 636 * 637 * "The IO Board is fitted with a Xilinx XCV300E main FPGA. Provision is made 638 * for configuring an optional FPGA on the mezzanine interface. 639 * 640 * Access to the FPGAs may be divided into several catagories: 641 * 642 * 1. Configuration 643 * 2. Register mode access 644 * 3. Port mode access 645 * 646 * The main FPGA is supported for modes 1, 2 and 3. The mezzanine FPGA can be 647 * configured only (mode 1). Consequently there are four access types. 648 * 649 * To improve interface performance and simplify software design, the four 650 * possible access types are separately mapped to different memory banks. 651 * 652 * All are accessed using the local bus." 653 * 654 * Device Mode Memory Bank Machine Port Size Access 655 * 656 * Main Configuration 3 UPMC 8bit R/W 657 * Main Register 4 GPCM 32bit R/W 658 * Main Port 5 UPMB 32bit R/W 659 * Mezzanine Configuration 6 UPMC 8bit W/O 660 * 661 * "Note that mezzanine mode 1 access is write-only." 662 */ 663 664/* all the bank sizes must be a power of two, greater or equal to 32768 */ 665#define FPGA_MAIN_CFG_BASE (CONFIG_SYS_FPGA_BASE) 666#define FPGA_MAIN_CFG_SIZE 32768 667#define FPGA_MAIN_REG_BASE (FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE) 668#define FPGA_MAIN_REG_SIZE 32768 669#define FPGA_MAIN_PORT_BASE (FPGA_MAIN_REG_BASE + FPGA_MAIN_REG_SIZE) 670#define FPGA_MAIN_PORT_SIZE 32768 671#define FPGA_MEZZ_CFG_BASE (FPGA_MAIN_PORT_BASE + FPGA_MAIN_PORT_SIZE) 672#define FPGA_MEZZ_CFG_SIZE 32768 673 674/* 8 bit, read-write, UPMC */ 675#define CONFIG_SYS_BR3_PRELIM (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V) 676/* up to 32Kbyte, burst inhibit */ 677#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI) 678 679/* 32 bit, read-write, GPCM */ 680#define CONFIG_SYS_BR4_PRELIM (FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V) 681/* up to 32Kbyte */ 682#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(FPGA_MAIN_REG_SIZE)) 683 684/* 32 bit, read-write, UPMB */ 685#define CONFIG_SYS_BR5_PRELIM (FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V) 686/* up to 32Kbyte */ 687#define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI) 688 689/* 8 bit, write-only, UPMC */ 690#define CONFIG_SYS_BR6_PRELIM (FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V) 691/* up to 32Kbyte, burst inhibit */ 692#define CONFIG_SYS_OR6_PRELIM (P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI) 693 694/*----------------------------------------------------------------------- 695 * MBMR - Machine B Mode 10-27 696 *----------------------------------------------------------------------- 697 */ 698#define CONFIG_SYS_MBMR (MxMR_BSEL|MxMR_OP_NORM) /* XXX - needs more */ 699 700/*----------------------------------------------------------------------- 701 * MCMR - Machine C Mode 10-27 702 *----------------------------------------------------------------------- 703 */ 704#define CONFIG_SYS_MCMR (MxMR_BSEL|MxMR_DSx_2_CYCL) /* XXX - needs more */ 705 706/* 707 * FPGA I/O Port/Bit information 708 */ 709 710#define FPGA_MAIN_PROG_PORT IOPIN_PORTA 711#define FPGA_MAIN_PROG_PIN 4 /* PA4 */ 712#define FPGA_MAIN_INIT_PORT IOPIN_PORTA 713#define FPGA_MAIN_INIT_PIN 5 /* PA5 */ 714#define FPGA_MAIN_DONE_PORT IOPIN_PORTA 715#define FPGA_MAIN_DONE_PIN 6 /* PA6 */ 716 717#define FPGA_MEZZ_PROG_PORT IOPIN_PORTA 718#define FPGA_MEZZ_PROG_PIN 0 /* PA0 */ 719#define FPGA_MEZZ_INIT_PORT IOPIN_PORTA 720#define FPGA_MEZZ_INIT_PIN 1 /* PA1 */ 721#define FPGA_MEZZ_DONE_PORT IOPIN_PORTA 722#define FPGA_MEZZ_DONE_PIN 2 /* PA2 */ 723#define FPGA_MEZZ_ENABLE_PORT IOPIN_PORTA 724#define FPGA_MEZZ_ENABLE_PIN 3 /* PA3 */ 725 726/* 727 * FPGA Interrupt configuration 728 */ 729#define FPGA_MAIN_IRQ SIU_INT_IRQ2 730 731/* 732 * JFFS2 partitions 733 * 734 */ 735/* No command line, one static partition, whole device */ 736#undef CONFIG_CMD_MTDPARTS 737#define CONFIG_JFFS2_DEV "nor0" 738#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF 739#define CONFIG_JFFS2_PART_OFFSET 0x00000000 740 741/* mtdparts command line support */ 742/* 743#define CONFIG_CMD_MTDPARTS 744#define MTDIDS_DEFAULT "" 745#define MTDPARTS_DEFAULT "" 746*/ 747 748#endif /* __CONFIG_H */ 749